drm/amdgpu: add smuio v13_0_3 ip headers

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add smuio v13_0_3 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by

Alex Deucher 2 years ago 63121b11 ebadc106

+605

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

smuio

smuio_13_0_3_offset.h

smuio_13_0_3_sh_mask.h

+177

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_3_offset.h

+428

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_3_sh_mask.h

··· 1 + /* 2 + * Copyright 2022 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _smuio_13_0_3_SH_MASK_HEADER 24 + #define _smuio_13_0_3_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: aid_smuio_smuio_reset_SmuSmuioDec 28 + //SMUIO_MP_RESET_INTR 29 + #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 30 + #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L 31 + //SMUIO_SOC_HALT 32 + #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 33 + #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 34 + #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L 35 + #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L 36 + 37 + 38 + // addressBlock: aid_smuio_smuio_tsc_SmuSmuioDec 39 + //PWROK_REFCLK_GAP_CYCLES 40 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 41 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 42 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 43 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 44 + //GOLDEN_TSC_INCREMENT_UPPER 45 + #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 46 + #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 47 + //GOLDEN_TSC_INCREMENT_LOWER 48 + #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 49 + #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 50 + //GOLDEN_TSC_COUNT_UPPER 51 + #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 52 + #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 53 + //GOLDEN_TSC_COUNT_LOWER 54 + #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 55 + #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 56 + //SOC_GOLDEN_TSC_SHADOW_UPPER 57 + #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 58 + #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL 59 + //SOC_GOLDEN_TSC_SHADOW_LOWER 60 + #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 61 + #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL 62 + //SOC_GAP_PWROK 63 + #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 64 + #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 65 + 66 + 67 + // addressBlock: aid_smuio_smuio_swtimer_SmuSmuioDec 68 + //PWR_VIRT_RESET_REQ 69 + #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 70 + #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f 71 + #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL 72 + #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L 73 + //PWR_DISP_TIMER_CONTROL 74 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 75 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 76 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 77 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 78 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 79 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 80 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 81 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 82 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 83 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 84 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 85 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 86 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 87 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 88 + //PWR_DISP_TIMER_DEBUG 89 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 90 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 91 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 92 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 93 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 94 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 95 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 96 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 97 + //PWR_DISP_TIMER2_CONTROL 98 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 99 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 100 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 101 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 102 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 103 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 104 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 105 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 106 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 107 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 108 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 109 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 110 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 111 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 112 + //PWR_DISP_TIMER2_DEBUG 113 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 114 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 115 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 116 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 117 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 118 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 119 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 120 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 121 + //PWR_DISP_TIMER_GLOBAL_CONTROL 122 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 123 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 124 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 125 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 126 + //PWR_IH_CONTROL 127 + #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 128 + #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 129 + #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 130 + #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f 131 + #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 132 + #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 133 + #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 134 + #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L 135 + 136 + 137 + // addressBlock: aid_smuio_smuio_misc_SmuSmuioDec 138 + //SMUIO_MCM_CONFIG 139 + #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 140 + #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 141 + #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 142 + #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0xc 143 + #define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 144 + #define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 145 + #define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0x12 146 + #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 147 + #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000003CL 148 + #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000F00L 149 + #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00001000L 150 + #define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L 151 + #define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L 152 + #define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x007C0000L 153 + //IP_DISCOVERY_VERSION 154 + #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 155 + #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 156 + //SCRATCH_REGISTER0 157 + #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 158 + #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 159 + //SCRATCH_REGISTER1 160 + #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 161 + #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 162 + //SCRATCH_REGISTER2 163 + #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 164 + #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 165 + //SCRATCH_REGISTER3 166 + #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 167 + #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 168 + //SCRATCH_REGISTER4 169 + #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 170 + #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 171 + //SCRATCH_REGISTER5 172 + #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 173 + #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 174 + //SCRATCH_REGISTER6 175 + #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 176 + #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 177 + //SCRATCH_REGISTER7 178 + #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 179 + #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 180 + 181 + 182 + // addressBlock: aid_smuio_smuio_gpio_SmuSmuioDec 183 + //SMU_GPIOPAD_SW_INT_STAT 184 + #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 185 + #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 186 + //SMU_GPIOPAD_MASK 187 + #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 188 + #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 189 + //SMU_GPIOPAD_A 190 + #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 191 + #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 192 + //SMU_GPIOPAD_TXIMPSEL 193 + #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 194 + #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 195 + //SMU_GPIOPAD_EN 196 + #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 197 + #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 198 + //SMU_GPIOPAD_Y 199 + #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 200 + #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 201 + //SMU_GPIOPAD_RXEN 202 + #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 203 + #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 204 + //SMU_GPIOPAD_RCVR_SEL0 205 + #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 206 + #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 207 + //SMU_GPIOPAD_RCVR_SEL1 208 + #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 209 + #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 210 + //SMU_GPIOPAD_PU_EN 211 + #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 212 + #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 213 + //SMU_GPIOPAD_PD_EN 214 + #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 215 + #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 216 + //SMU_GPIOPAD_PINSTRAPS 217 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 218 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 219 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 220 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 221 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 222 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 223 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 224 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 225 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 226 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 227 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 228 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 229 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 230 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 231 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 232 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 233 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 234 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 235 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 236 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 237 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 238 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 239 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 240 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 241 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 242 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 243 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 244 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 245 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 246 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 247 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 248 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 249 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 250 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 251 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 252 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 253 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 254 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 255 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 256 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 257 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 258 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 259 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 260 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 261 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 262 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 263 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 264 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 265 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 266 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 267 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 268 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 269 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 270 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 271 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 272 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 273 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 274 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 275 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 276 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 277 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 278 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 279 + //DFT_PINSTRAPS 280 + #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 281 + #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL 282 + //SMU_GPIOPAD_INT_STAT_EN 283 + #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 284 + #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 285 + #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 286 + #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 287 + //SMU_GPIOPAD_INT_STAT 288 + #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 289 + #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 290 + #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 291 + #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 292 + //SMU_GPIOPAD_INT_STAT_AK 293 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 294 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 295 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 296 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 297 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 298 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 299 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 300 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 301 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 302 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 303 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 304 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 305 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 306 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 307 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 308 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 309 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 310 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 311 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 312 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 313 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 314 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 315 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 316 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 317 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 318 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 319 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 320 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 321 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 322 + #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 323 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 324 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 325 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 326 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 327 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 328 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 329 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 330 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 331 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 332 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 333 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 334 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 335 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 336 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 337 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 338 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 339 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 340 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 341 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 342 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 343 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 344 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 345 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 346 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 347 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 348 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 349 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 350 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 351 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 352 + #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 353 + //SMU_GPIOPAD_INT_EN 354 + #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 355 + #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 356 + #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 357 + #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 358 + //SMU_GPIOPAD_INT_TYPE 359 + #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 360 + #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 361 + #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 362 + #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 363 + //SMU_GPIOPAD_INT_POLARITY 364 + #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 365 + #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 366 + #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 367 + #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 368 + //SMUIO_PCC_GPIO_SELECT 369 + #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 370 + #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 371 + //SMU_GPIOPAD_S0 372 + #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 373 + #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 374 + //SMU_GPIOPAD_S1 375 + #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 376 + #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 377 + //SMU_GPIOPAD_SCHMEN 378 + #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 379 + #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 380 + //SMU_GPIOPAD_SCL_EN 381 + #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 382 + #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 383 + //SMU_GPIOPAD_SDA_EN 384 + #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 385 + #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 386 + //SMUIO_GPIO_INT0_SELECT 387 + #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 388 + #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 389 + //SMUIO_GPIO_INT1_SELECT 390 + #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 391 + #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 392 + //SMUIO_GPIO_INT2_SELECT 393 + #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 394 + #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 395 + //SMUIO_GPIO_INT3_SELECT 396 + #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 397 + #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 398 + //SMU_GPIOPAD_MP_INT0_STAT 399 + #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 400 + #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 401 + //SMU_GPIOPAD_MP_INT1_STAT 402 + #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 403 + #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 404 + //SMU_GPIOPAD_MP_INT2_STAT 405 + #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 406 + #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 407 + //SMU_GPIOPAD_MP_INT3_STAT 408 + #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 409 + #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 410 + //SMIO_INDEX 411 + #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 412 + #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 413 + //S0_VID_SMIO_CNTL 414 + #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 415 + #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 416 + //S1_VID_SMIO_CNTL 417 + #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 418 + #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 419 + //OPEN_DRAIN_SELECT 420 + #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 421 + #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 422 + #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 423 + #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 424 + //SMIO_ENABLE 425 + #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 426 + #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 427 + 428 + #endif