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RISC-V: KVM: Improve vector save/restore functions

Make two nonfunctional changes to the vector get/set vector reg
functions and their supporting function for simplification and
readability. The first is to not pass KVM_REG_RISCV_VECTOR, but
rather integrate it directly into the masking. The second is to
rename reg_val to reg_addr where and address is used instead of
a value.

Also opportunistically touch up some of the code formatting for
a third nonfunctional change.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>

authored by

Andrew Jones and committed by
Anup Patel 630b4cee e47f3c28

+23 -35
+2 -4
arch/riscv/include/asm/kvm_vcpu_vector.h
··· 74 74 #endif 75 75 76 76 int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, 77 - const struct kvm_one_reg *reg, 78 - unsigned long rtype); 77 + const struct kvm_one_reg *reg); 79 78 int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, 80 - const struct kvm_one_reg *reg, 81 - unsigned long rtype); 79 + const struct kvm_one_reg *reg); 82 80 #endif
+2 -4
arch/riscv/kvm/vcpu_onereg.c
··· 645 645 case KVM_REG_RISCV_SBI_EXT: 646 646 return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg); 647 647 case KVM_REG_RISCV_VECTOR: 648 - return kvm_riscv_vcpu_set_reg_vector(vcpu, reg, 649 - KVM_REG_RISCV_VECTOR); 648 + return kvm_riscv_vcpu_set_reg_vector(vcpu, reg); 650 649 default: 651 650 break; 652 651 } ··· 676 677 case KVM_REG_RISCV_SBI_EXT: 677 678 return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg); 678 679 case KVM_REG_RISCV_VECTOR: 679 - return kvm_riscv_vcpu_get_reg_vector(vcpu, reg, 680 - KVM_REG_RISCV_VECTOR); 680 + return kvm_riscv_vcpu_get_reg_vector(vcpu, reg); 681 681 default: 682 682 break; 683 683 }
+19 -27
arch/riscv/kvm/vcpu_vector.c
··· 92 92 #endif 93 93 94 94 static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, 95 - unsigned long reg_num, 96 - size_t reg_size, 97 - void **reg_val) 95 + unsigned long reg_num, 96 + size_t reg_size, 97 + void **reg_addr) 98 98 { 99 99 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 100 100 size_t vlenb = riscv_v_vsize / 32; ··· 104 104 return -EINVAL; 105 105 switch (reg_num) { 106 106 case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): 107 - *reg_val = &cntx->vector.vstart; 107 + *reg_addr = &cntx->vector.vstart; 108 108 break; 109 109 case KVM_REG_RISCV_VECTOR_CSR_REG(vl): 110 - *reg_val = &cntx->vector.vl; 110 + *reg_addr = &cntx->vector.vl; 111 111 break; 112 112 case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): 113 - *reg_val = &cntx->vector.vtype; 113 + *reg_addr = &cntx->vector.vtype; 114 114 break; 115 115 case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): 116 - *reg_val = &cntx->vector.vcsr; 116 + *reg_addr = &cntx->vector.vcsr; 117 117 break; 118 118 case KVM_REG_RISCV_VECTOR_CSR_REG(datap): 119 119 default: ··· 122 122 } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { 123 123 if (reg_size != vlenb) 124 124 return -EINVAL; 125 - *reg_val = cntx->vector.datap 126 - + (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; 125 + *reg_addr = cntx->vector.datap + 126 + (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; 127 127 } else { 128 128 return -ENOENT; 129 129 } ··· 132 132 } 133 133 134 134 int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, 135 - const struct kvm_one_reg *reg, 136 - unsigned long rtype) 135 + const struct kvm_one_reg *reg) 137 136 { 138 137 unsigned long *isa = vcpu->arch.isa; 139 138 unsigned long __user *uaddr = 140 139 (unsigned long __user *)(unsigned long)reg->addr; 141 140 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 142 141 KVM_REG_SIZE_MASK | 143 - rtype); 142 + KVM_REG_RISCV_VECTOR); 144 143 size_t reg_size = KVM_REG_SIZE(reg->id); 145 - void *reg_val; 144 + void *reg_addr; 146 145 int rc; 147 - 148 - if (rtype != KVM_REG_RISCV_VECTOR) 149 - return -EINVAL; 150 146 151 147 if (!riscv_isa_extension_available(isa, v)) 152 148 return -ENOENT; 153 149 154 - rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_val); 150 + rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); 155 151 if (rc) 156 152 return rc; 157 153 158 - if (copy_to_user(uaddr, reg_val, reg_size)) 154 + if (copy_to_user(uaddr, reg_addr, reg_size)) 159 155 return -EFAULT; 160 156 161 157 return 0; 162 158 } 163 159 164 160 int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, 165 - const struct kvm_one_reg *reg, 166 - unsigned long rtype) 161 + const struct kvm_one_reg *reg) 167 162 { 168 163 unsigned long *isa = vcpu->arch.isa; 169 164 unsigned long __user *uaddr = 170 165 (unsigned long __user *)(unsigned long)reg->addr; 171 166 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 172 167 KVM_REG_SIZE_MASK | 173 - rtype); 168 + KVM_REG_RISCV_VECTOR); 174 169 size_t reg_size = KVM_REG_SIZE(reg->id); 175 - void *reg_val; 170 + void *reg_addr; 176 171 int rc; 177 - 178 - if (rtype != KVM_REG_RISCV_VECTOR) 179 - return -EINVAL; 180 172 181 173 if (!riscv_isa_extension_available(isa, v)) 182 174 return -ENOENT; 183 175 184 - rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_val); 176 + rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); 185 177 if (rc) 186 178 return rc; 187 179 188 - if (copy_from_user(reg_val, uaddr, reg_size)) 180 + if (copy_from_user(reg_addr, uaddr, reg_size)) 189 181 return -EFAULT; 190 182 191 183 return 0;