tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/display: Add missing dcn35 RCO registers

[Why]
Some registers needed for root clock gating in dcn35 are not defined in
the dccg header.

[How]
Add the needed registers and temporarily disable some register writes
that are now taking place successfully until the registers can be
properly enabled.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Daniel Miess and committed by
Alex Deucher 62fbfdbb a546a276

+143 -2
+32
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
··· 296 296 type DTBCLK_P1_GATE_DISABLE;\ 297 297 type DTBCLK_P2_GATE_DISABLE;\ 298 298 type DTBCLK_P3_GATE_DISABLE;\ 299 + type DSCCLK0_ROOT_GATE_DISABLE;\ 300 + type DSCCLK1_ROOT_GATE_DISABLE;\ 301 + type DSCCLK2_ROOT_GATE_DISABLE;\ 302 + type DSCCLK3_ROOT_GATE_DISABLE;\ 303 + type SYMCLKA_FE_ROOT_GATE_DISABLE;\ 304 + type SYMCLKB_FE_ROOT_GATE_DISABLE;\ 305 + type SYMCLKC_FE_ROOT_GATE_DISABLE;\ 306 + type SYMCLKD_FE_ROOT_GATE_DISABLE;\ 307 + type SYMCLKE_FE_ROOT_GATE_DISABLE;\ 308 + type DPPCLK0_ROOT_GATE_DISABLE;\ 309 + type DPPCLK1_ROOT_GATE_DISABLE;\ 310 + type DPPCLK2_ROOT_GATE_DISABLE;\ 311 + type DPPCLK3_ROOT_GATE_DISABLE;\ 312 + type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\ 313 + type SYMCLKA_ROOT_GATE_DISABLE;\ 314 + type SYMCLKB_ROOT_GATE_DISABLE;\ 315 + type SYMCLKC_ROOT_GATE_DISABLE;\ 316 + type SYMCLKD_ROOT_GATE_DISABLE;\ 317 + type SYMCLKE_ROOT_GATE_DISABLE;\ 318 + type PHYA_REFCLK_ROOT_GATE_DISABLE;\ 319 + type PHYB_REFCLK_ROOT_GATE_DISABLE;\ 320 + type PHYC_REFCLK_ROOT_GATE_DISABLE;\ 321 + type PHYD_REFCLK_ROOT_GATE_DISABLE;\ 322 + type PHYE_REFCLK_ROOT_GATE_DISABLE;\ 323 + type DPSTREAMCLK0_ROOT_GATE_DISABLE;\ 324 + type DPSTREAMCLK1_ROOT_GATE_DISABLE;\ 325 + type DPSTREAMCLK2_ROOT_GATE_DISABLE;\ 326 + type DPSTREAMCLK3_ROOT_GATE_DISABLE;\ 327 + type DPSTREAMCLK0_GATE_DISABLE;\ 328 + type DPSTREAMCLK1_GATE_DISABLE;\ 329 + type DPSTREAMCLK2_GATE_DISABLE;\ 330 + type DPSTREAMCLK3_GATE_DISABLE;\ 299 331 300 332 struct dccg_shift { 301 333 DCCG_REG_FIELD_LIST(uint8_t)
+60 -2
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
··· 506 506 dccg->dpp_clock_gated[dpp_inst] = !clock_on; 507 507 } 508 508 509 + static void dccg35_disable_symclk32_se( 510 + struct dccg *dccg, 511 + int hpo_se_inst) 512 + { 513 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 514 + 515 + /* set refclk as the source for symclk32_se */ 516 + switch (hpo_se_inst) { 517 + case 0: 518 + REG_UPDATE_2(SYMCLK32_SE_CNTL, 519 + SYMCLK32_SE0_SRC_SEL, 0, 520 + SYMCLK32_SE0_EN, 0); 521 + if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { 522 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 523 + SYMCLK32_SE0_GATE_DISABLE, 0); 524 + // REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 525 + // SYMCLK32_ROOT_SE0_GATE_DISABLE, 0); 526 + } 527 + break; 528 + case 1: 529 + REG_UPDATE_2(SYMCLK32_SE_CNTL, 530 + SYMCLK32_SE1_SRC_SEL, 0, 531 + SYMCLK32_SE1_EN, 0); 532 + if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { 533 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 534 + SYMCLK32_SE1_GATE_DISABLE, 0); 535 + // REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 536 + // SYMCLK32_ROOT_SE1_GATE_DISABLE, 0); 537 + } 538 + break; 539 + case 2: 540 + REG_UPDATE_2(SYMCLK32_SE_CNTL, 541 + SYMCLK32_SE2_SRC_SEL, 0, 542 + SYMCLK32_SE2_EN, 0); 543 + if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { 544 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 545 + SYMCLK32_SE2_GATE_DISABLE, 0); 546 + // REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 547 + // SYMCLK32_ROOT_SE2_GATE_DISABLE, 0); 548 + } 549 + break; 550 + case 3: 551 + REG_UPDATE_2(SYMCLK32_SE_CNTL, 552 + SYMCLK32_SE3_SRC_SEL, 0, 553 + SYMCLK32_SE3_EN, 0); 554 + if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { 555 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 556 + SYMCLK32_SE3_GATE_DISABLE, 0); 557 + // REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, 558 + // SYMCLK32_ROOT_SE3_GATE_DISABLE, 0); 559 + } 560 + break; 561 + default: 562 + BREAK_TO_DEBUGGER(); 563 + return; 564 + } 565 + } 566 + 509 567 void dccg35_init(struct dccg *dccg) 510 568 { 511 569 int otg_inst; ··· 572 514 * will cause DCN to hang. 573 515 */ 574 516 for (otg_inst = 0; otg_inst < 4; otg_inst++) 575 - dccg31_disable_symclk32_se(dccg, otg_inst); 517 + dccg35_disable_symclk32_se(dccg, otg_inst); 576 518 577 519 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 578 520 for (otg_inst = 0; otg_inst < 2; otg_inst++) ··· 846 788 .dccg_init = dccg35_init, 847 789 .set_dpstreamclk = dccg35_set_dpstreamclk, 848 790 .enable_symclk32_se = dccg31_enable_symclk32_se, 849 - .disable_symclk32_se = dccg31_disable_symclk32_se, 791 + .disable_symclk32_se = dccg35_disable_symclk32_se, 850 792 .enable_symclk32_le = dccg31_enable_symclk32_le, 851 793 .disable_symclk32_le = dccg31_disable_symclk32_le, 852 794 .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,
+51
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
··· 34 34 #define DCCG_REG_LIST_DCN35() \ 35 35 DCCG_REG_LIST_DCN314(),\ 36 36 SR(DPPCLK_CTRL),\ 37 + SR(DCCG_GATE_DISABLE_CNTL4),\ 37 38 SR(DCCG_GATE_DISABLE_CNTL5),\ 38 39 SR(DCCG_GATE_DISABLE_CNTL6),\ 39 40 SR(DCCG_GLOBAL_FGCG_REP_CNTL),\ ··· 181 180 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ 182 181 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ 183 182 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ 183 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\ 184 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\ 185 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\ 186 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\ 187 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\ 188 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\ 189 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\ 190 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\ 191 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\ 192 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\ 193 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\ 194 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\ 195 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\ 196 + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\ 197 + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\ 198 + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ 199 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\ 200 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\ 201 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\ 202 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\ 203 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\ 204 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ 205 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ 206 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ 207 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\ 208 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\ 209 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\ 210 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\ 211 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\ 212 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\ 213 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\ 214 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\ 215 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\ 216 + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ 217 + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ 218 + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ 219 + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ 220 + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ 221 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ 222 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\ 223 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\ 224 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\ 225 + DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\ 226 + DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\ 227 + DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\ 228 + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\ 229 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ 230 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ 231 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ 232 + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ 184 233 185 234 struct dccg *dccg35_create( 186 235 struct dc_context *ctx,