tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Export except_vec_vi_{mori,lui,ori} as text symbols.
[MIPS] mips-boards: More liberal check for mips-board console
[MIPS] Misc fixes for plat_irq_dispatch functions
[MIPS] Qemu: Fix Symmetric Uniprocessor support.
[MIPS] VI: TRACE_IRQS_OFF clobbers $v0, so save & restore around call.

Linus Torvalds 62b6e9ff 8718d75e

+49 -24
unified split
+12 -3
arch/mips/Kconfig
··· 542 542 select SYS_SUPPORTS_LITTLE_ENDIAN 543 543 select ARCH_SPARSEMEM_ENABLE 544 544 select GENERIC_HARDIRQS_NO__DO_IRQ 545 + select NR_CPUS_DEFAULT_1 546 + select SYS_SUPPORTS_SMP 545 547 help 546 548 Qemu is a software emulator which among other architectures also 547 549 can simulate a MIPS32 4Kc system. This patch adds support for the ··· 1807 1805 config SYS_SUPPORTS_SMP 1808 1806 bool 1809 1807 1808 + config NR_CPUS_DEFAULT_1 1809 + bool 1810 + 1810 1811 config NR_CPUS_DEFAULT_2 1811 1812 bool 1812 1813 ··· 1830 1825 1831 1826 config NR_CPUS 1832 1827 int "Maximum number of CPUs (2-64)" 1833 - range 2 64 1828 + range 1 64 if NR_CPUS_DEFAULT_1 1834 1829 depends on SMP 1830 + default "1" if NR_CPUS_DEFAULT_1 1835 1831 default "2" if NR_CPUS_DEFAULT_2 1836 1832 default "4" if NR_CPUS_DEFAULT_4 1837 1833 default "8" if NR_CPUS_DEFAULT_8 ··· 1843 1837 This allows you to specify the maximum number of CPUs which this 1844 1838 kernel will support. The maximum supported value is 32 for 32-bit 1845 1839 kernel and 64 for 64-bit kernels; the minimum value which makes 1846 - sense is 2. 1840 + sense is 1 for Qemu (useful only for kernel debugging purposes) 1841 + and 2 for all others. 1847 1842 1848 1843 This is purely to save memory - each supported CPU adds 1849 - approximately eight kilobytes to the kernel image. 1844 + approximately eight kilobytes to the kernel image. For best 1845 + performance should round up your number of processors to the next 1846 + power of two. 1850 1847 1851 1848 # 1852 1849 # Timer Interrupt Frequency Configuration
+1 -1
arch/mips/ddb5xxx/ddb5477/irq.c
··· 194 194 195 195 asmlinkage void plat_irq_dispatch(void) 196 196 { 197 - unsigned int pending = read_c0_cause() & read_c0_status(); 197 + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 198 198 199 199 if (pending & STATUSF_IP7) 200 200 do_IRQ(CPU_IRQ_BASE + 7);
+1 -1
arch/mips/emma2rh/markeins/irq.c
··· 115 115 116 116 asmlinkage void plat_irq_dispatch(void) 117 117 { 118 - unsigned int pending = read_c0_status() & read_c0_cause(); 118 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 119 119 120 120 if (pending & STATUSF_IP7) 121 121 do_IRQ(CPU_IRQ_BASE + 7);
+1 -1
arch/mips/gt64120/ev64120/irq.c
··· 48 48 49 49 asmlinkage void plat_irq_dispatch(void) 50 50 { 51 - unsigned int pending = read_c0_status() & read_c0_cause(); 51 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 52 52 53 53 if (pending & STATUSF_IP4) /* int2 hardware line (timer) */ 54 54 do_IRQ(4);
+1 -1
arch/mips/gt64120/wrppmc/irq.c
··· 32 32 33 33 asmlinkage void plat_irq_dispatch(void) 34 34 { 35 - unsigned int pending = read_c0_status() & read_c0_cause(); 35 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 36 36 37 37 if (pending & STATUSF_IP7) 38 38 do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
+1 -1
arch/mips/jazz/irq.c
··· 122 122 123 123 asmlinkage void plat_irq_dispatch(void) 124 124 { 125 - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 125 + unsigned int pending = read_c0_cause() & read_c0_status(); 126 126 127 127 if (pending & IE_IRQ5) 128 128 write_c0_compare(0);
+13 -3
arch/mips/kernel/genex.S
··· 181 181 * during service by SMTC kernel, we also want to 182 182 * pass the IM value to be cleared. 183 183 */ 184 - EXPORT(except_vec_vi_mori) 184 + FEXPORT(except_vec_vi_mori) 185 185 ori a0, $0, 0 186 186 #endif /* CONFIG_MIPS_MT_SMTC */ 187 - EXPORT(except_vec_vi_lui) 187 + FEXPORT(except_vec_vi_lui) 188 188 lui v0, 0 /* Patched */ 189 189 j except_vec_vi_handler 190 - EXPORT(except_vec_vi_ori) 190 + FEXPORT(except_vec_vi_ori) 191 191 ori v0, 0 /* Patched */ 192 192 .set pop 193 193 END(except_vec_vi) ··· 220 220 _ehb 221 221 #endif /* CONFIG_MIPS_MT_SMTC */ 222 222 CLI 223 + #ifdef CONFIG_TRACE_IRQFLAGS 224 + move s0, v0 225 + #ifdef CONFIG_MIPS_MT_SMTC 226 + move s1, a0 227 + #endif 223 228 TRACE_IRQS_OFF 229 + #ifdef CONFIG_MIPS_MT_SMTC 230 + move a0, s1 231 + #endif 232 + move v0, s0 233 + #endif 224 234 225 235 LONG_L s0, TI_REGS($28) 226 236 LONG_S sp, TI_REGS($28)
+1 -1
arch/mips/mips-boards/generic/init.c
··· 145 145 char parity = '\0', bits = '\0', flow = '\0'; 146 146 char *s; 147 147 148 - if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) { 148 + if ((strstr(prom_getcmdline(), "console=")) == NULL) { 149 149 s = prom_getenv("modetty0"); 150 150 if (s) { 151 151 while (*s >= '0' && *s <= '9')
+1 -1
arch/mips/momentum/ocelot_c/irq.c
··· 64 64 65 65 asmlinkage void plat_irq_dispatch(void) 66 66 { 67 - unsigned int pending = read_c0_cause() & read_c0_status(); 67 + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 68 68 69 69 if (pending & STATUSF_IP0) 70 70 do_IRQ(0);
+3 -4
arch/mips/philips/pnx8550/common/int.c
··· 83 83 84 84 asmlinkage void plat_irq_dispatch(void) 85 85 { 86 - unsigned int pending = read_c0_status() & read_c0_cause(); 86 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 87 87 88 88 if (pending & STATUSF_IP2) 89 89 hw0_irqdispatch(2); 90 90 else if (pending & STATUSF_IP7) { 91 91 if (read_c0_config7() & 0x01c0) 92 92 timer_irqdispatch(7); 93 - } 94 - 95 - spurious_interrupt(); 93 + } else 94 + spurious_interrupt(); 96 95 } 97 96 98 97 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
+7
arch/mips/qemu/q-smp.c
··· 46 46 void prom_boot_secondary(int cpu, struct task_struct *idle) 47 47 { 48 48 } 49 + 50 + void __init plat_smp_setup(void) 51 + { 52 + } 53 + void __init plat_prepare_cpus(unsigned int max_cpus) 54 + { 55 + }
+1 -1
arch/mips/sgi-ip22/ip22-int.c
··· 237 237 238 238 asmlinkage void plat_irq_dispatch(void) 239 239 { 240 - unsigned int pending = read_c0_cause(); 240 + unsigned int pending = read_c0_status() & read_c0_cause(); 241 241 242 242 /* 243 243 * First we check for r4k counter/timer IRQ.
+1 -1
arch/mips/sgi-ip32/ip32-irq.c
··· 454 454 455 455 asmlinkage void plat_irq_dispatch(void) 456 456 { 457 - unsigned int pending = read_c0_cause(); 457 + unsigned int pending = read_c0_status() & read_c0_cause(); 458 458 459 459 if (likely(pending & IE_IRQ0)) 460 460 ip32_irq0();
+1 -1
arch/mips/sibyte/sb1250/irq.c
··· 421 421 * blasting the high 32 bits. 422 422 */ 423 423 424 - pending = read_c0_cause() & read_c0_status(); 424 + pending = read_c0_cause() & read_c0_status() & ST0_IM; 425 425 426 426 #ifdef CONFIG_SIBYTE_SB1250_PROF 427 427 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
+1 -1
arch/mips/sni/pcimt.c
··· 333 333 334 334 static void sni_pcimt_hwint(void) 335 335 { 336 - u32 pending = (read_c0_cause() & read_c0_status()); 336 + u32 pending = read_c0_cause() & read_c0_status(); 337 337 338 338 if (pending & C_IRQ5) 339 339 do_IRQ (MIPS_CPU_IRQ_BASE + 7);
+2 -2
arch/mips/sni/pcit.c
··· 271 271 272 272 static void sni_pcit_hwint(void) 273 273 { 274 - u32 pending = (read_c0_cause() & read_c0_status()); 274 + u32 pending = read_c0_cause() & read_c0_status(); 275 275 276 276 if (pending & C_IRQ1) 277 277 pcit_hwint1(); ··· 285 285 286 286 static void sni_pcit_hwint_cplus(void) 287 287 { 288 - u32 pending = (read_c0_cause() & read_c0_status()); 288 + u32 pending = read_c0_cause() & read_c0_status(); 289 289 290 290 if (pending & C_IRQ0) 291 291 pcit_hwint0();
+1 -1
arch/mips/tx4927/common/tx4927_irq.c
··· 416 416 417 417 asmlinkage void plat_irq_dispatch(void) 418 418 { 419 - unsigned int pending = read_c0_status() & read_c0_cause(); 419 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 420 420 421 421 if (pending & STATUSF_IP7) /* cpu timer */ 422 422 do_IRQ(TX4927_IRQ_CPU_TIMER);