tjh.dev / kernel
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[PATCH] ppc32: Check return of ppc_sys_get_pdata before accessing pointer

Ensure that the returned pointer from ppc_sys_get_pdata is not NULL before we
start using it. This handles any cases where we have variants of processors
on the same board with different functionality.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

authored by

Kumar Gala and committed by
Linus Torvalds 62aa751d 09ffd94f

+88 -66
+16 -12
arch/ppc/platforms/83xx/mpc834x_sys.c
··· 94 94 95 95 /* setup the board related information for the enet controllers */ 96 96 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1); 97 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 98 - pdata->interruptPHY = MPC83xx_IRQ_EXT1; 99 - pdata->phyid = 0; 100 - /* fixup phy address */ 101 - pdata->phy_reg_addr += binfo->bi_immr_base; 102 - memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 97 + if (pdata) { 98 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 99 + pdata->interruptPHY = MPC83xx_IRQ_EXT1; 100 + pdata->phyid = 0; 101 + /* fixup phy address */ 102 + pdata->phy_reg_addr += binfo->bi_immr_base; 103 + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 104 + } 103 105 104 106 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2); 105 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 106 - pdata->interruptPHY = MPC83xx_IRQ_EXT2; 107 - pdata->phyid = 1; 108 - /* fixup phy address */ 109 - pdata->phy_reg_addr += binfo->bi_immr_base; 110 - memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 107 + if (pdata) { 108 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 109 + pdata->interruptPHY = MPC83xx_IRQ_EXT2; 110 + pdata->phyid = 1; 111 + /* fixup phy address */ 112 + pdata->phy_reg_addr += binfo->bi_immr_base; 113 + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 114 + } 111 115 112 116 #ifdef CONFIG_BLK_DEV_INITRD 113 117 if (initrd_start)
+25 -19
arch/ppc/platforms/85xx/mpc8540_ads.c
··· 92 92 93 93 /* setup the board related information for the enet controllers */ 94 94 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 95 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 96 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 97 - pdata->phyid = 0; 98 - /* fixup phy address */ 99 - pdata->phy_reg_addr += binfo->bi_immr_base; 100 - memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 95 + if (pdata) { 96 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 97 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 98 + pdata->phyid = 0; 99 + /* fixup phy address */ 100 + pdata->phy_reg_addr += binfo->bi_immr_base; 101 + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 102 + } 101 103 102 104 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 103 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 104 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 105 - pdata->phyid = 1; 106 - /* fixup phy address */ 107 - pdata->phy_reg_addr += binfo->bi_immr_base; 108 - memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 105 + if (pdata) { 106 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 107 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 108 + pdata->phyid = 1; 109 + /* fixup phy address */ 110 + pdata->phy_reg_addr += binfo->bi_immr_base; 111 + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 112 + } 109 113 110 - pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); 111 - pdata->board_flags = 0; 112 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 113 - pdata->phyid = 3; 114 - /* fixup phy address */ 115 - pdata->phy_reg_addr += binfo->bi_immr_base; 116 - memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); 114 + if (pdata) { 115 + pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); 116 + pdata->board_flags = 0; 117 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 118 + pdata->phyid = 3; 119 + /* fixup phy address */ 120 + pdata->phy_reg_addr += binfo->bi_immr_base; 121 + memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); 122 + } 117 123 118 124 #ifdef CONFIG_BLK_DEV_INITRD 119 125 if (initrd_start)
+16 -12
arch/ppc/platforms/85xx/mpc8560_ads.c
··· 90 90 91 91 /* setup the board related information for the enet controllers */ 92 92 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 93 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 94 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 95 - pdata->phyid = 0; 96 - /* fixup phy address */ 97 - pdata->phy_reg_addr += binfo->bi_immr_base; 98 - memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 93 + if (pdata) { 94 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 95 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 96 + pdata->phyid = 0; 97 + /* fixup phy address */ 98 + pdata->phy_reg_addr += binfo->bi_immr_base; 99 + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 100 + } 99 101 100 102 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 101 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 102 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 103 - pdata->phyid = 1; 104 - /* fixup phy address */ 105 - pdata->phy_reg_addr += binfo->bi_immr_base; 106 - memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 103 + if (pdata) { 104 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 105 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 106 + pdata->phyid = 1; 107 + /* fixup phy address */ 108 + pdata->phy_reg_addr += binfo->bi_immr_base; 109 + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 110 + } 107 111 108 112 #ifdef CONFIG_BLK_DEV_INITRD 109 113 if (initrd_start)
+16 -12
arch/ppc/platforms/85xx/sbc8560.c
··· 129 129 130 130 /* setup the board related information for the enet controllers */ 131 131 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 132 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 133 - pdata->interruptPHY = MPC85xx_IRQ_EXT6; 134 - pdata->phyid = 25; 135 - /* fixup phy address */ 136 - pdata->phy_reg_addr += binfo->bi_immr_base; 137 - memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 132 + if (pdata) { 133 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 134 + pdata->interruptPHY = MPC85xx_IRQ_EXT6; 135 + pdata->phyid = 25; 136 + /* fixup phy address */ 137 + pdata->phy_reg_addr += binfo->bi_immr_base; 138 + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 139 + } 138 140 139 141 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 140 - pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 141 - pdata->interruptPHY = MPC85xx_IRQ_EXT7; 142 - pdata->phyid = 26; 143 - /* fixup phy address */ 144 - pdata->phy_reg_addr += binfo->bi_immr_base; 145 - memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 142 + if (pdata) { 143 + pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 144 + pdata->interruptPHY = MPC85xx_IRQ_EXT7; 145 + pdata->phyid = 26; 146 + /* fixup phy address */ 147 + pdata->phy_reg_addr += binfo->bi_immr_base; 148 + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 149 + } 146 150 147 151 #ifdef CONFIG_BLK_DEV_INITRD 148 152 if (initrd_start)
+15 -11
arch/ppc/platforms/85xx/stx_gp3.c
··· 122 122 123 123 /* setup the board related information for the enet controllers */ 124 124 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 125 - /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 126 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 127 - pdata->phyid = 2; 128 - pdata->phy_reg_addr += binfo->bi_immr_base; 129 - memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 125 + if (pdata) { 126 + /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 127 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 128 + pdata->phyid = 2; 129 + pdata->phy_reg_addr += binfo->bi_immr_base; 130 + memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 131 + } 130 132 131 133 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 132 - /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 133 - pdata->interruptPHY = MPC85xx_IRQ_EXT5; 134 - pdata->phyid = 4; 135 - /* fixup phy address */ 136 - pdata->phy_reg_addr += binfo->bi_immr_base; 137 - memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 134 + if (pdata) { 135 + /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 136 + pdata->interruptPHY = MPC85xx_IRQ_EXT5; 137 + pdata->phyid = 4; 138 + /* fixup phy address */ 139 + pdata->phy_reg_addr += binfo->bi_immr_base; 140 + memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 141 + } 138 142 139 143 #ifdef CONFIG_BLK_DEV_INITRD 140 144 if (initrd_start)