tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: add mp 13.0.5 header files

This patch is to add mp 13.0.5 header files.

v2: update headers

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yifan Zhang and committed by
Alex Deucher 62640f25 068ea8bd

+1127
+455
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h
··· 1 + /* 2 + * Copyright 2022 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * 23 + */ 24 + #ifndef _mp_13_0_5_OFFSET_HEADER 25 + #define _mp_13_0_5_OFFSET_HEADER 26 + 27 + 28 + 29 + // addressBlock: mp_SmuMp0_SmnDec 30 + // base address: 0x0 31 + #define regMP0_SMN_C2PMSG_32 0x0060 32 + #define regMP0_SMN_C2PMSG_32_BASE_IDX 0 33 + #define regMP0_SMN_C2PMSG_33 0x0061 34 + #define regMP0_SMN_C2PMSG_33_BASE_IDX 0 35 + #define regMP0_SMN_C2PMSG_34 0x0062 36 + #define regMP0_SMN_C2PMSG_34_BASE_IDX 0 37 + #define regMP0_SMN_C2PMSG_35 0x0063 38 + #define regMP0_SMN_C2PMSG_35_BASE_IDX 0 39 + #define regMP0_SMN_C2PMSG_36 0x0064 40 + #define regMP0_SMN_C2PMSG_36_BASE_IDX 0 41 + #define regMP0_SMN_C2PMSG_37 0x0065 42 + #define regMP0_SMN_C2PMSG_37_BASE_IDX 0 43 + #define regMP0_SMN_C2PMSG_38 0x0066 44 + #define regMP0_SMN_C2PMSG_38_BASE_IDX 0 45 + #define regMP0_SMN_C2PMSG_39 0x0067 46 + #define regMP0_SMN_C2PMSG_39_BASE_IDX 0 47 + #define regMP0_SMN_C2PMSG_40 0x0068 48 + #define regMP0_SMN_C2PMSG_40_BASE_IDX 0 49 + #define regMP0_SMN_C2PMSG_41 0x0069 50 + #define regMP0_SMN_C2PMSG_41_BASE_IDX 0 51 + #define regMP0_SMN_C2PMSG_42 0x006a 52 + #define regMP0_SMN_C2PMSG_42_BASE_IDX 0 53 + #define regMP0_SMN_C2PMSG_43 0x006b 54 + #define regMP0_SMN_C2PMSG_43_BASE_IDX 0 55 + #define regMP0_SMN_C2PMSG_44 0x006c 56 + #define regMP0_SMN_C2PMSG_44_BASE_IDX 0 57 + #define regMP0_SMN_C2PMSG_45 0x006d 58 + #define regMP0_SMN_C2PMSG_45_BASE_IDX 0 59 + #define regMP0_SMN_C2PMSG_46 0x006e 60 + #define regMP0_SMN_C2PMSG_46_BASE_IDX 0 61 + #define regMP0_SMN_C2PMSG_47 0x006f 62 + #define regMP0_SMN_C2PMSG_47_BASE_IDX 0 63 + #define regMP0_SMN_C2PMSG_48 0x0070 64 + #define regMP0_SMN_C2PMSG_48_BASE_IDX 0 65 + #define regMP0_SMN_C2PMSG_49 0x0071 66 + #define regMP0_SMN_C2PMSG_49_BASE_IDX 0 67 + #define regMP0_SMN_C2PMSG_50 0x0072 68 + #define regMP0_SMN_C2PMSG_50_BASE_IDX 0 69 + #define regMP0_SMN_C2PMSG_51 0x0073 70 + #define regMP0_SMN_C2PMSG_51_BASE_IDX 0 71 + #define regMP0_SMN_C2PMSG_52 0x0074 72 + #define regMP0_SMN_C2PMSG_52_BASE_IDX 0 73 + #define regMP0_SMN_C2PMSG_53 0x0075 74 + #define regMP0_SMN_C2PMSG_53_BASE_IDX 0 75 + #define regMP0_SMN_C2PMSG_54 0x0076 76 + #define regMP0_SMN_C2PMSG_54_BASE_IDX 0 77 + #define regMP0_SMN_C2PMSG_55 0x0077 78 + #define regMP0_SMN_C2PMSG_55_BASE_IDX 0 79 + #define regMP0_SMN_C2PMSG_56 0x0078 80 + #define regMP0_SMN_C2PMSG_56_BASE_IDX 0 81 + #define regMP0_SMN_C2PMSG_57 0x0079 82 + #define regMP0_SMN_C2PMSG_57_BASE_IDX 0 83 + #define regMP0_SMN_C2PMSG_58 0x007a 84 + #define regMP0_SMN_C2PMSG_58_BASE_IDX 0 85 + #define regMP0_SMN_C2PMSG_59 0x007b 86 + #define regMP0_SMN_C2PMSG_59_BASE_IDX 0 87 + #define regMP0_SMN_C2PMSG_60 0x007c 88 + #define regMP0_SMN_C2PMSG_60_BASE_IDX 0 89 + #define regMP0_SMN_C2PMSG_61 0x007d 90 + #define regMP0_SMN_C2PMSG_61_BASE_IDX 0 91 + #define regMP0_SMN_C2PMSG_62 0x007e 92 + #define regMP0_SMN_C2PMSG_62_BASE_IDX 0 93 + #define regMP0_SMN_C2PMSG_63 0x007f 94 + #define regMP0_SMN_C2PMSG_63_BASE_IDX 0 95 + #define regMP0_SMN_C2PMSG_64 0x0080 96 + #define regMP0_SMN_C2PMSG_64_BASE_IDX 0 97 + #define regMP0_SMN_C2PMSG_65 0x0081 98 + #define regMP0_SMN_C2PMSG_65_BASE_IDX 0 99 + #define regMP0_SMN_C2PMSG_66 0x0082 100 + #define regMP0_SMN_C2PMSG_66_BASE_IDX 0 101 + #define regMP0_SMN_C2PMSG_67 0x0083 102 + #define regMP0_SMN_C2PMSG_67_BASE_IDX 0 103 + #define regMP0_SMN_C2PMSG_68 0x0084 104 + #define regMP0_SMN_C2PMSG_68_BASE_IDX 0 105 + #define regMP0_SMN_C2PMSG_69 0x0085 106 + #define regMP0_SMN_C2PMSG_69_BASE_IDX 0 107 + #define regMP0_SMN_C2PMSG_70 0x0086 108 + #define regMP0_SMN_C2PMSG_70_BASE_IDX 0 109 + #define regMP0_SMN_C2PMSG_71 0x0087 110 + #define regMP0_SMN_C2PMSG_71_BASE_IDX 0 111 + #define regMP0_SMN_C2PMSG_72 0x0088 112 + #define regMP0_SMN_C2PMSG_72_BASE_IDX 0 113 + #define regMP0_SMN_C2PMSG_73 0x0089 114 + #define regMP0_SMN_C2PMSG_73_BASE_IDX 0 115 + #define regMP0_SMN_C2PMSG_74 0x008a 116 + #define regMP0_SMN_C2PMSG_74_BASE_IDX 0 117 + #define regMP0_SMN_C2PMSG_75 0x008b 118 + #define regMP0_SMN_C2PMSG_75_BASE_IDX 0 119 + #define regMP0_SMN_C2PMSG_76 0x008c 120 + #define regMP0_SMN_C2PMSG_76_BASE_IDX 0 121 + #define regMP0_SMN_C2PMSG_77 0x008d 122 + #define regMP0_SMN_C2PMSG_77_BASE_IDX 0 123 + #define regMP0_SMN_C2PMSG_78 0x008e 124 + #define regMP0_SMN_C2PMSG_78_BASE_IDX 0 125 + #define regMP0_SMN_C2PMSG_79 0x008f 126 + #define regMP0_SMN_C2PMSG_79_BASE_IDX 0 127 + #define regMP0_SMN_C2PMSG_80 0x0090 128 + #define regMP0_SMN_C2PMSG_80_BASE_IDX 0 129 + #define regMP0_SMN_C2PMSG_81 0x0091 130 + #define regMP0_SMN_C2PMSG_81_BASE_IDX 0 131 + #define regMP0_SMN_C2PMSG_82 0x0092 132 + #define regMP0_SMN_C2PMSG_82_BASE_IDX 0 133 + #define regMP0_SMN_C2PMSG_83 0x0093 134 + #define regMP0_SMN_C2PMSG_83_BASE_IDX 0 135 + #define regMP0_SMN_C2PMSG_84 0x0094 136 + #define regMP0_SMN_C2PMSG_84_BASE_IDX 0 137 + #define regMP0_SMN_C2PMSG_85 0x0095 138 + #define regMP0_SMN_C2PMSG_85_BASE_IDX 0 139 + #define regMP0_SMN_C2PMSG_86 0x0096 140 + #define regMP0_SMN_C2PMSG_86_BASE_IDX 0 141 + #define regMP0_SMN_C2PMSG_87 0x0097 142 + #define regMP0_SMN_C2PMSG_87_BASE_IDX 0 143 + #define regMP0_SMN_C2PMSG_88 0x0098 144 + #define regMP0_SMN_C2PMSG_88_BASE_IDX 0 145 + #define regMP0_SMN_C2PMSG_89 0x0099 146 + #define regMP0_SMN_C2PMSG_89_BASE_IDX 0 147 + #define regMP0_SMN_C2PMSG_90 0x009a 148 + #define regMP0_SMN_C2PMSG_90_BASE_IDX 0 149 + #define regMP0_SMN_C2PMSG_91 0x009b 150 + #define regMP0_SMN_C2PMSG_91_BASE_IDX 0 151 + #define regMP0_SMN_C2PMSG_92 0x009c 152 + #define regMP0_SMN_C2PMSG_92_BASE_IDX 0 153 + #define regMP0_SMN_C2PMSG_93 0x009d 154 + #define regMP0_SMN_C2PMSG_93_BASE_IDX 0 155 + #define regMP0_SMN_C2PMSG_94 0x009e 156 + #define regMP0_SMN_C2PMSG_94_BASE_IDX 0 157 + #define regMP0_SMN_C2PMSG_95 0x009f 158 + #define regMP0_SMN_C2PMSG_95_BASE_IDX 0 159 + #define regMP0_SMN_C2PMSG_96 0x00a0 160 + #define regMP0_SMN_C2PMSG_96_BASE_IDX 0 161 + #define regMP0_SMN_C2PMSG_97 0x00a1 162 + #define regMP0_SMN_C2PMSG_97_BASE_IDX 0 163 + #define regMP0_SMN_C2PMSG_98 0x00a2 164 + #define regMP0_SMN_C2PMSG_98_BASE_IDX 0 165 + #define regMP0_SMN_C2PMSG_99 0x00a3 166 + #define regMP0_SMN_C2PMSG_99_BASE_IDX 0 167 + #define regMP0_SMN_C2PMSG_100 0x00a4 168 + #define regMP0_SMN_C2PMSG_100_BASE_IDX 0 169 + #define regMP0_SMN_C2PMSG_101 0x00a5 170 + #define regMP0_SMN_C2PMSG_101_BASE_IDX 0 171 + #define regMP0_SMN_C2PMSG_102 0x00a6 172 + #define regMP0_SMN_C2PMSG_102_BASE_IDX 0 173 + #define regMP0_SMN_C2PMSG_103 0x00a7 174 + #define regMP0_SMN_C2PMSG_103_BASE_IDX 0 175 + #define regMP0_SMN_IH_CREDIT 0x00c1 176 + #define regMP0_SMN_IH_CREDIT_BASE_IDX 0 177 + #define regMP0_SMN_IH_SW_INT 0x00c2 178 + #define regMP0_SMN_IH_SW_INT_BASE_IDX 0 179 + #define regMP0_SMN_IH_SW_INT_CTRL 0x00c3 180 + #define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 181 + 182 + 183 + // addressBlock: mp_SmuMp1_SmnDec 184 + // base address: 0x0 185 + #define regMP1_SMN_C2PMSG_32 0x0260 186 + #define regMP1_SMN_C2PMSG_32_BASE_IDX 0 187 + #define regMP1_SMN_C2PMSG_33 0x0261 188 + #define regMP1_SMN_C2PMSG_33_BASE_IDX 0 189 + #define regMP1_SMN_C2PMSG_34 0x0262 190 + #define regMP1_SMN_C2PMSG_34_BASE_IDX 0 191 + #define regMP1_SMN_C2PMSG_35 0x0263 192 + #define regMP1_SMN_C2PMSG_35_BASE_IDX 0 193 + #define regMP1_SMN_C2PMSG_36 0x0264 194 + #define regMP1_SMN_C2PMSG_36_BASE_IDX 0 195 + #define regMP1_SMN_C2PMSG_37 0x0265 196 + #define regMP1_SMN_C2PMSG_37_BASE_IDX 0 197 + #define regMP1_SMN_C2PMSG_38 0x0266 198 + #define regMP1_SMN_C2PMSG_38_BASE_IDX 0 199 + #define regMP1_SMN_C2PMSG_39 0x0267 200 + #define regMP1_SMN_C2PMSG_39_BASE_IDX 0 201 + #define regMP1_SMN_C2PMSG_40 0x0268 202 + #define regMP1_SMN_C2PMSG_40_BASE_IDX 0 203 + #define regMP1_SMN_C2PMSG_41 0x0269 204 + #define regMP1_SMN_C2PMSG_41_BASE_IDX 0 205 + #define regMP1_SMN_C2PMSG_42 0x026a 206 + #define regMP1_SMN_C2PMSG_42_BASE_IDX 0 207 + #define regMP1_SMN_C2PMSG_43 0x026b 208 + #define regMP1_SMN_C2PMSG_43_BASE_IDX 0 209 + #define regMP1_SMN_C2PMSG_44 0x026c 210 + #define regMP1_SMN_C2PMSG_44_BASE_IDX 0 211 + #define regMP1_SMN_C2PMSG_45 0x026d 212 + #define regMP1_SMN_C2PMSG_45_BASE_IDX 0 213 + #define regMP1_SMN_C2PMSG_46 0x026e 214 + #define regMP1_SMN_C2PMSG_46_BASE_IDX 0 215 + #define regMP1_SMN_C2PMSG_47 0x026f 216 + #define regMP1_SMN_C2PMSG_47_BASE_IDX 0 217 + #define regMP1_SMN_C2PMSG_48 0x0270 218 + #define regMP1_SMN_C2PMSG_48_BASE_IDX 0 219 + #define regMP1_SMN_C2PMSG_49 0x0271 220 + #define regMP1_SMN_C2PMSG_49_BASE_IDX 0 221 + #define regMP1_SMN_C2PMSG_50 0x0272 222 + #define regMP1_SMN_C2PMSG_50_BASE_IDX 0 223 + #define regMP1_SMN_C2PMSG_51 0x0273 224 + #define regMP1_SMN_C2PMSG_51_BASE_IDX 0 225 + #define regMP1_SMN_C2PMSG_52 0x0274 226 + #define regMP1_SMN_C2PMSG_52_BASE_IDX 0 227 + #define regMP1_SMN_C2PMSG_53 0x0275 228 + #define regMP1_SMN_C2PMSG_53_BASE_IDX 0 229 + #define regMP1_SMN_C2PMSG_54 0x0276 230 + #define regMP1_SMN_C2PMSG_54_BASE_IDX 0 231 + #define regMP1_SMN_C2PMSG_55 0x0277 232 + #define regMP1_SMN_C2PMSG_55_BASE_IDX 0 233 + #define regMP1_SMN_C2PMSG_56 0x0278 234 + #define regMP1_SMN_C2PMSG_56_BASE_IDX 0 235 + #define regMP1_SMN_C2PMSG_57 0x0279 236 + #define regMP1_SMN_C2PMSG_57_BASE_IDX 0 237 + #define regMP1_SMN_C2PMSG_58 0x027a 238 + #define regMP1_SMN_C2PMSG_58_BASE_IDX 0 239 + #define regMP1_SMN_C2PMSG_59 0x027b 240 + #define regMP1_SMN_C2PMSG_59_BASE_IDX 0 241 + #define regMP1_SMN_C2PMSG_60 0x027c 242 + #define regMP1_SMN_C2PMSG_60_BASE_IDX 0 243 + #define regMP1_SMN_C2PMSG_61 0x027d 244 + #define regMP1_SMN_C2PMSG_61_BASE_IDX 0 245 + #define regMP1_SMN_C2PMSG_62 0x027e 246 + #define regMP1_SMN_C2PMSG_62_BASE_IDX 0 247 + #define regMP1_SMN_C2PMSG_63 0x027f 248 + #define regMP1_SMN_C2PMSG_63_BASE_IDX 0 249 + #define regMP1_SMN_C2PMSG_64 0x0280 250 + #define regMP1_SMN_C2PMSG_64_BASE_IDX 0 251 + #define regMP1_SMN_C2PMSG_65 0x0281 252 + #define regMP1_SMN_C2PMSG_65_BASE_IDX 0 253 + #define regMP1_SMN_C2PMSG_66 0x0282 254 + #define regMP1_SMN_C2PMSG_66_BASE_IDX 0 255 + #define regMP1_SMN_C2PMSG_67 0x0283 256 + #define regMP1_SMN_C2PMSG_67_BASE_IDX 0 257 + #define regMP1_SMN_C2PMSG_68 0x0284 258 + #define regMP1_SMN_C2PMSG_68_BASE_IDX 0 259 + #define regMP1_SMN_C2PMSG_69 0x0285 260 + #define regMP1_SMN_C2PMSG_69_BASE_IDX 0 261 + #define regMP1_SMN_C2PMSG_70 0x0286 262 + #define regMP1_SMN_C2PMSG_70_BASE_IDX 0 263 + #define regMP1_SMN_C2PMSG_71 0x0287 264 + #define regMP1_SMN_C2PMSG_71_BASE_IDX 0 265 + #define regMP1_SMN_C2PMSG_72 0x0288 266 + #define regMP1_SMN_C2PMSG_72_BASE_IDX 0 267 + #define regMP1_SMN_C2PMSG_73 0x0289 268 + #define regMP1_SMN_C2PMSG_73_BASE_IDX 0 269 + #define regMP1_SMN_C2PMSG_74 0x028a 270 + #define regMP1_SMN_C2PMSG_74_BASE_IDX 0 271 + #define regMP1_SMN_C2PMSG_75 0x028b 272 + #define regMP1_SMN_C2PMSG_75_BASE_IDX 0 273 + #define regMP1_SMN_C2PMSG_76 0x028c 274 + #define regMP1_SMN_C2PMSG_76_BASE_IDX 0 275 + #define regMP1_SMN_C2PMSG_77 0x028d 276 + #define regMP1_SMN_C2PMSG_77_BASE_IDX 0 277 + #define regMP1_SMN_C2PMSG_78 0x028e 278 + #define regMP1_SMN_C2PMSG_78_BASE_IDX 0 279 + #define regMP1_SMN_C2PMSG_79 0x028f 280 + #define regMP1_SMN_C2PMSG_79_BASE_IDX 0 281 + #define regMP1_SMN_C2PMSG_80 0x0290 282 + #define regMP1_SMN_C2PMSG_80_BASE_IDX 0 283 + #define regMP1_SMN_C2PMSG_81 0x0291 284 + #define regMP1_SMN_C2PMSG_81_BASE_IDX 0 285 + #define regMP1_SMN_C2PMSG_82 0x0292 286 + #define regMP1_SMN_C2PMSG_82_BASE_IDX 0 287 + #define regMP1_SMN_C2PMSG_83 0x0293 288 + #define regMP1_SMN_C2PMSG_83_BASE_IDX 0 289 + #define regMP1_SMN_C2PMSG_84 0x0294 290 + #define regMP1_SMN_C2PMSG_84_BASE_IDX 0 291 + #define regMP1_SMN_C2PMSG_85 0x0295 292 + #define regMP1_SMN_C2PMSG_85_BASE_IDX 0 293 + #define regMP1_SMN_C2PMSG_86 0x0296 294 + #define regMP1_SMN_C2PMSG_86_BASE_IDX 0 295 + #define regMP1_SMN_C2PMSG_87 0x0297 296 + #define regMP1_SMN_C2PMSG_87_BASE_IDX 0 297 + #define regMP1_SMN_C2PMSG_88 0x0298 298 + #define regMP1_SMN_C2PMSG_88_BASE_IDX 0 299 + #define regMP1_SMN_C2PMSG_89 0x0299 300 + #define regMP1_SMN_C2PMSG_89_BASE_IDX 0 301 + #define regMP1_SMN_C2PMSG_90 0x029a 302 + #define regMP1_SMN_C2PMSG_90_BASE_IDX 0 303 + #define regMP1_SMN_C2PMSG_91 0x029b 304 + #define regMP1_SMN_C2PMSG_91_BASE_IDX 0 305 + #define regMP1_SMN_C2PMSG_92 0x029c 306 + #define regMP1_SMN_C2PMSG_92_BASE_IDX 0 307 + #define regMP1_SMN_C2PMSG_93 0x029d 308 + #define regMP1_SMN_C2PMSG_93_BASE_IDX 0 309 + #define regMP1_SMN_C2PMSG_94 0x029e 310 + #define regMP1_SMN_C2PMSG_94_BASE_IDX 0 311 + #define regMP1_SMN_C2PMSG_95 0x029f 312 + #define regMP1_SMN_C2PMSG_95_BASE_IDX 0 313 + #define regMP1_SMN_C2PMSG_96 0x02a0 314 + #define regMP1_SMN_C2PMSG_96_BASE_IDX 0 315 + #define regMP1_SMN_C2PMSG_97 0x02a1 316 + #define regMP1_SMN_C2PMSG_97_BASE_IDX 0 317 + #define regMP1_SMN_C2PMSG_98 0x02a2 318 + #define regMP1_SMN_C2PMSG_98_BASE_IDX 0 319 + #define regMP1_SMN_C2PMSG_99 0x02a3 320 + #define regMP1_SMN_C2PMSG_99_BASE_IDX 0 321 + #define regMP1_SMN_C2PMSG_100 0x02a4 322 + #define regMP1_SMN_C2PMSG_100_BASE_IDX 0 323 + #define regMP1_SMN_C2PMSG_101 0x02a5 324 + #define regMP1_SMN_C2PMSG_101_BASE_IDX 0 325 + #define regMP1_SMN_C2PMSG_102 0x02a6 326 + #define regMP1_SMN_C2PMSG_102_BASE_IDX 0 327 + #define regMP1_SMN_C2PMSG_103 0x02a7 328 + #define regMP1_SMN_C2PMSG_103_BASE_IDX 0 329 + #define regMP1_SMN_C2PMSG_104 0x02a8 330 + #define regMP1_SMN_C2PMSG_104_BASE_IDX 0 331 + #define regMP1_SMN_C2PMSG_105 0x02a9 332 + #define regMP1_SMN_C2PMSG_105_BASE_IDX 0 333 + #define regMP1_SMN_C2PMSG_106 0x02aa 334 + #define regMP1_SMN_C2PMSG_106_BASE_IDX 0 335 + #define regMP1_SMN_C2PMSG_107 0x02ab 336 + #define regMP1_SMN_C2PMSG_107_BASE_IDX 0 337 + #define regMP1_SMN_C2PMSG_108 0x02ac 338 + #define regMP1_SMN_C2PMSG_108_BASE_IDX 0 339 + #define regMP1_SMN_C2PMSG_109 0x02ad 340 + #define regMP1_SMN_C2PMSG_109_BASE_IDX 0 341 + #define regMP1_SMN_C2PMSG_110 0x02ae 342 + #define regMP1_SMN_C2PMSG_110_BASE_IDX 0 343 + #define regMP1_SMN_C2PMSG_111 0x02af 344 + #define regMP1_SMN_C2PMSG_111_BASE_IDX 0 345 + #define regMP1_SMN_C2PMSG_112 0x02b0 346 + #define regMP1_SMN_C2PMSG_112_BASE_IDX 0 347 + #define regMP1_SMN_C2PMSG_113 0x02b1 348 + #define regMP1_SMN_C2PMSG_113_BASE_IDX 0 349 + #define regMP1_SMN_C2PMSG_114 0x02b2 350 + #define regMP1_SMN_C2PMSG_114_BASE_IDX 0 351 + #define regMP1_SMN_C2PMSG_115 0x02b3 352 + #define regMP1_SMN_C2PMSG_115_BASE_IDX 0 353 + #define regMP1_SMN_C2PMSG_116 0x02b4 354 + #define regMP1_SMN_C2PMSG_116_BASE_IDX 0 355 + #define regMP1_SMN_C2PMSG_117 0x02b5 356 + #define regMP1_SMN_C2PMSG_117_BASE_IDX 0 357 + #define regMP1_SMN_C2PMSG_118 0x02b6 358 + #define regMP1_SMN_C2PMSG_118_BASE_IDX 0 359 + #define regMP1_SMN_C2PMSG_119 0x02b7 360 + #define regMP1_SMN_C2PMSG_119_BASE_IDX 0 361 + #define regMP1_SMN_C2PMSG_120 0x02b8 362 + #define regMP1_SMN_C2PMSG_120_BASE_IDX 0 363 + #define regMP1_SMN_C2PMSG_121 0x02b9 364 + #define regMP1_SMN_C2PMSG_121_BASE_IDX 0 365 + #define regMP1_SMN_C2PMSG_122 0x02ba 366 + #define regMP1_SMN_C2PMSG_122_BASE_IDX 0 367 + #define regMP1_SMN_C2PMSG_123 0x02bb 368 + #define regMP1_SMN_C2PMSG_123_BASE_IDX 0 369 + #define regMP1_SMN_C2PMSG_124 0x02bc 370 + #define regMP1_SMN_C2PMSG_124_BASE_IDX 0 371 + #define regMP1_SMN_C2PMSG_125 0x02bd 372 + #define regMP1_SMN_C2PMSG_125_BASE_IDX 0 373 + #define regMP1_SMN_C2PMSG_126 0x02be 374 + #define regMP1_SMN_C2PMSG_126_BASE_IDX 0 375 + #define regMP1_SMN_C2PMSG_127 0x02bf 376 + #define regMP1_SMN_C2PMSG_127_BASE_IDX 0 377 + #define regMP1_SMN_IH_CREDIT 0x02c1 378 + #define regMP1_SMN_IH_CREDIT_BASE_IDX 0 379 + #define regMP1_SMN_IH_SW_INT 0x02c2 380 + #define regMP1_SMN_IH_SW_INT_BASE_IDX 0 381 + #define regMP1_SMN_IH_SW_INT_CTRL 0x02c3 382 + #define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 383 + #define regMP1_SMN_FPS_CNT 0x02c4 384 + #define regMP1_SMN_FPS_CNT_BASE_IDX 0 385 + #define regMP1_SMN_EXT_SCRATCH0 0x0340 386 + #define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 387 + #define regMP1_SMN_EXT_SCRATCH1 0x0341 388 + #define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 389 + #define regMP1_SMN_EXT_SCRATCH2 0x0342 390 + #define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 391 + #define regMP1_SMN_EXT_SCRATCH3 0x0343 392 + #define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 393 + #define regMP1_SMN_EXT_SCRATCH4 0x0344 394 + #define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 395 + #define regMP1_SMN_EXT_SCRATCH5 0x0345 396 + #define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 397 + #define regMP1_SMN_EXT_SCRATCH6 0x0346 398 + #define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 399 + #define regMP1_SMN_EXT_SCRATCH7 0x0347 400 + #define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 401 + #define regMP1_SMN_EXT_SCRATCH8 0x0348 402 + #define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 403 + #define regMP1_SMN_EXT_SCRATCH10 0x034a 404 + #define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0 405 + #define regMP1_SMN_EXT_SCRATCH11 0x034b 406 + #define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0 407 + #define regMP1_SMN_EXT_SCRATCH12 0x034c 408 + #define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0 409 + #define regMP1_SMN_EXT_SCRATCH13 0x034d 410 + #define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0 411 + #define regMP1_SMN_EXT_SCRATCH14 0x034e 412 + #define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0 413 + #define regMP1_SMN_EXT_SCRATCH15 0x034f 414 + #define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0 415 + #define regMP1_SMN_EXT_SCRATCH16 0x0350 416 + #define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0 417 + #define regMP1_SMN_EXT_SCRATCH17 0x0351 418 + #define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0 419 + #define regMP1_SMN_EXT_SCRATCH18 0x0352 420 + #define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0 421 + #define regMP1_SMN_EXT_SCRATCH19 0x0353 422 + #define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0 423 + #define regMP1_SMN_EXT_SCRATCH20 0x0354 424 + #define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0 425 + #define regMP1_SMN_EXT_SCRATCH21 0x0355 426 + #define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0 427 + #define regMP1_SMN_EXT_SCRATCH22 0x0356 428 + #define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0 429 + #define regMP1_SMN_EXT_SCRATCH23 0x0357 430 + #define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0 431 + #define regMP1_SMN_EXT_SCRATCH24 0x0358 432 + #define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0 433 + #define regMP1_SMN_EXT_SCRATCH25 0x0359 434 + #define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0 435 + #define regMP1_SMN_EXT_SCRATCH26 0x035a 436 + #define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0 437 + #define regMP1_SMN_EXT_SCRATCH27 0x035b 438 + #define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0 439 + #define regMP1_SMN_EXT_SCRATCH28 0x035c 440 + #define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0 441 + #define regMP1_SMN_EXT_SCRATCH29 0x035d 442 + #define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0 443 + #define regMP1_SMN_EXT_SCRATCH30 0x035e 444 + #define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0 445 + #define regMP1_SMN_EXT_SCRATCH31 0x035f 446 + #define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0 447 + 448 + 449 + // addressBlock: mp_SmuMp1Pub_CruDec 450 + // base address: 0x0 451 + #define regMP1_FIRMWARE_FLAGS 0xbee009 452 + #define regMP1_FIRMWARE_FLAGS_BASE_IDX 0 453 + 454 + 455 + #endif
+672
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h
··· 1 + /* 2 + * Copyright 2022 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * 23 + */ 24 + #ifndef _mp_13_0_5_SH_MASK_HEADER 25 + #define _mp_13_0_5_SH_MASK_HEADER 26 + 27 + 28 + // addressBlock: mp_SmuMp0_SmnDec 29 + //MP0_SMN_C2PMSG_32 30 + #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 31 + #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 32 + //MP0_SMN_C2PMSG_33 33 + #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 34 + #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 35 + //MP0_SMN_C2PMSG_34 36 + #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 37 + #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 38 + //MP0_SMN_C2PMSG_35 39 + #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 40 + #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 41 + //MP0_SMN_C2PMSG_36 42 + #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 43 + #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 44 + //MP0_SMN_C2PMSG_37 45 + #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 46 + #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 47 + //MP0_SMN_C2PMSG_38 48 + #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 49 + #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 50 + //MP0_SMN_C2PMSG_39 51 + #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 52 + #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 53 + //MP0_SMN_C2PMSG_40 54 + #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 55 + #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 56 + //MP0_SMN_C2PMSG_41 57 + #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 58 + #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 59 + //MP0_SMN_C2PMSG_42 60 + #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 61 + #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 62 + //MP0_SMN_C2PMSG_43 63 + #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 64 + #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 65 + //MP0_SMN_C2PMSG_44 66 + #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 67 + #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 68 + //MP0_SMN_C2PMSG_45 69 + #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 70 + #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 71 + //MP0_SMN_C2PMSG_46 72 + #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 73 + #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 74 + //MP0_SMN_C2PMSG_47 75 + #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 76 + #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 77 + //MP0_SMN_C2PMSG_48 78 + #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 79 + #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 80 + //MP0_SMN_C2PMSG_49 81 + #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 82 + #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 83 + //MP0_SMN_C2PMSG_50 84 + #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 85 + #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 86 + //MP0_SMN_C2PMSG_51 87 + #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 88 + #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 89 + //MP0_SMN_C2PMSG_52 90 + #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 91 + #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 92 + //MP0_SMN_C2PMSG_53 93 + #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 94 + #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 95 + //MP0_SMN_C2PMSG_54 96 + #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 97 + #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 98 + //MP0_SMN_C2PMSG_55 99 + #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 100 + #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 101 + //MP0_SMN_C2PMSG_56 102 + #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 103 + #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 104 + //MP0_SMN_C2PMSG_57 105 + #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 106 + #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 107 + //MP0_SMN_C2PMSG_58 108 + #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 109 + #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 110 + //MP0_SMN_C2PMSG_59 111 + #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 112 + #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 113 + //MP0_SMN_C2PMSG_60 114 + #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 115 + #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 116 + //MP0_SMN_C2PMSG_61 117 + #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 118 + #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 119 + //MP0_SMN_C2PMSG_62 120 + #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 121 + #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 122 + //MP0_SMN_C2PMSG_63 123 + #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 124 + #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 125 + //MP0_SMN_C2PMSG_64 126 + #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 127 + #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 128 + //MP0_SMN_C2PMSG_65 129 + #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 130 + #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 131 + //MP0_SMN_C2PMSG_66 132 + #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 133 + #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 134 + //MP0_SMN_C2PMSG_67 135 + #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 136 + #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 137 + //MP0_SMN_C2PMSG_68 138 + #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 139 + #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 140 + //MP0_SMN_C2PMSG_69 141 + #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 142 + #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 143 + //MP0_SMN_C2PMSG_70 144 + #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 145 + #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 146 + //MP0_SMN_C2PMSG_71 147 + #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 148 + #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 149 + //MP0_SMN_C2PMSG_72 150 + #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 151 + #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 152 + //MP0_SMN_C2PMSG_73 153 + #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 154 + #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 155 + //MP0_SMN_C2PMSG_74 156 + #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 157 + #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 158 + //MP0_SMN_C2PMSG_75 159 + #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 160 + #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 161 + //MP0_SMN_C2PMSG_76 162 + #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 163 + #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 164 + //MP0_SMN_C2PMSG_77 165 + #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 166 + #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 167 + //MP0_SMN_C2PMSG_78 168 + #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 169 + #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 170 + //MP0_SMN_C2PMSG_79 171 + #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 172 + #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 173 + //MP0_SMN_C2PMSG_80 174 + #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 175 + #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 176 + //MP0_SMN_C2PMSG_81 177 + #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 178 + #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 179 + //MP0_SMN_C2PMSG_82 180 + #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 181 + #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 182 + //MP0_SMN_C2PMSG_83 183 + #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 184 + #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 185 + //MP0_SMN_C2PMSG_84 186 + #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 187 + #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 188 + //MP0_SMN_C2PMSG_85 189 + #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 190 + #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 191 + //MP0_SMN_C2PMSG_86 192 + #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 193 + #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 194 + //MP0_SMN_C2PMSG_87 195 + #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 196 + #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 197 + //MP0_SMN_C2PMSG_88 198 + #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 199 + #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 200 + //MP0_SMN_C2PMSG_89 201 + #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 202 + #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 203 + //MP0_SMN_C2PMSG_90 204 + #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 205 + #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 206 + //MP0_SMN_C2PMSG_91 207 + #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 208 + #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 209 + //MP0_SMN_C2PMSG_92 210 + #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 211 + #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 212 + //MP0_SMN_C2PMSG_93 213 + #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 214 + #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 215 + //MP0_SMN_C2PMSG_94 216 + #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 217 + #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 218 + //MP0_SMN_C2PMSG_95 219 + #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 220 + #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 221 + //MP0_SMN_C2PMSG_96 222 + #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 223 + #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 224 + //MP0_SMN_C2PMSG_97 225 + #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 226 + #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 227 + //MP0_SMN_C2PMSG_98 228 + #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 229 + #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 230 + //MP0_SMN_C2PMSG_99 231 + #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 232 + #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 233 + //MP0_SMN_C2PMSG_100 234 + #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 235 + #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 236 + //MP0_SMN_C2PMSG_101 237 + #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 238 + #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 239 + //MP0_SMN_C2PMSG_102 240 + #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 241 + #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 242 + //MP0_SMN_C2PMSG_103 243 + #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 244 + #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 245 + //MP0_SMN_IH_CREDIT 246 + #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 247 + #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 248 + #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 249 + #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 250 + //MP0_SMN_IH_SW_INT 251 + #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 252 + #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 253 + #define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL 254 + #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L 255 + //MP0_SMN_IH_SW_INT_CTRL 256 + #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 257 + #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 258 + #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 259 + #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 260 + 261 + 262 + // addressBlock: mp_SmuMp1_SmnDec 263 + //MP1_SMN_C2PMSG_32 264 + #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 265 + #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 266 + //MP1_SMN_C2PMSG_33 267 + #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 268 + #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 269 + //MP1_SMN_C2PMSG_34 270 + #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 271 + #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 272 + //MP1_SMN_C2PMSG_35 273 + #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 274 + #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 275 + //MP1_SMN_C2PMSG_36 276 + #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 277 + #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 278 + //MP1_SMN_C2PMSG_37 279 + #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 280 + #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 281 + //MP1_SMN_C2PMSG_38 282 + #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 283 + #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 284 + //MP1_SMN_C2PMSG_39 285 + #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 286 + #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 287 + //MP1_SMN_C2PMSG_40 288 + #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 289 + #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 290 + //MP1_SMN_C2PMSG_41 291 + #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 292 + #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 293 + //MP1_SMN_C2PMSG_42 294 + #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 295 + #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 296 + //MP1_SMN_C2PMSG_43 297 + #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 298 + #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 299 + //MP1_SMN_C2PMSG_44 300 + #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 301 + #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 302 + //MP1_SMN_C2PMSG_45 303 + #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 304 + #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 305 + //MP1_SMN_C2PMSG_46 306 + #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 307 + #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 308 + //MP1_SMN_C2PMSG_47 309 + #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 310 + #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 311 + //MP1_SMN_C2PMSG_48 312 + #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 313 + #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 314 + //MP1_SMN_C2PMSG_49 315 + #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 316 + #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 317 + //MP1_SMN_C2PMSG_50 318 + #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 319 + #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 320 + //MP1_SMN_C2PMSG_51 321 + #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 322 + #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 323 + //MP1_SMN_C2PMSG_52 324 + #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 325 + #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 326 + //MP1_SMN_C2PMSG_53 327 + #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 328 + #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 329 + //MP1_SMN_C2PMSG_54 330 + #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 331 + #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 332 + //MP1_SMN_C2PMSG_55 333 + #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 334 + #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 335 + //MP1_SMN_C2PMSG_56 336 + #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 337 + #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 338 + //MP1_SMN_C2PMSG_57 339 + #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 340 + #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 341 + //MP1_SMN_C2PMSG_58 342 + #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 343 + #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 344 + //MP1_SMN_C2PMSG_59 345 + #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 346 + #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 347 + //MP1_SMN_C2PMSG_60 348 + #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 349 + #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 350 + //MP1_SMN_C2PMSG_61 351 + #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 352 + #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 353 + //MP1_SMN_C2PMSG_62 354 + #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 355 + #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 356 + //MP1_SMN_C2PMSG_63 357 + #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 358 + #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 359 + //MP1_SMN_C2PMSG_64 360 + #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 361 + #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 362 + //MP1_SMN_C2PMSG_65 363 + #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 364 + #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 365 + //MP1_SMN_C2PMSG_66 366 + #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 367 + #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 368 + //MP1_SMN_C2PMSG_67 369 + #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 370 + #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 371 + //MP1_SMN_C2PMSG_68 372 + #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 373 + #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 374 + //MP1_SMN_C2PMSG_69 375 + #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 376 + #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 377 + //MP1_SMN_C2PMSG_70 378 + #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 379 + #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 380 + //MP1_SMN_C2PMSG_71 381 + #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 382 + #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 383 + //MP1_SMN_C2PMSG_72 384 + #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 385 + #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 386 + //MP1_SMN_C2PMSG_73 387 + #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 388 + #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 389 + //MP1_SMN_C2PMSG_74 390 + #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 391 + #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 392 + //MP1_SMN_C2PMSG_75 393 + #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 394 + #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 395 + //MP1_SMN_C2PMSG_76 396 + #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 397 + #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 398 + //MP1_SMN_C2PMSG_77 399 + #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 400 + #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 401 + //MP1_SMN_C2PMSG_78 402 + #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 403 + #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 404 + //MP1_SMN_C2PMSG_79 405 + #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 406 + #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 407 + //MP1_SMN_C2PMSG_80 408 + #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 409 + #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 410 + //MP1_SMN_C2PMSG_81 411 + #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 412 + #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 413 + //MP1_SMN_C2PMSG_82 414 + #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 415 + #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 416 + //MP1_SMN_C2PMSG_83 417 + #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 418 + #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 419 + //MP1_SMN_C2PMSG_84 420 + #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 421 + #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 422 + //MP1_SMN_C2PMSG_85 423 + #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 424 + #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 425 + //MP1_SMN_C2PMSG_86 426 + #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 427 + #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 428 + //MP1_SMN_C2PMSG_87 429 + #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 430 + #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 431 + //MP1_SMN_C2PMSG_88 432 + #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 433 + #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 434 + //MP1_SMN_C2PMSG_89 435 + #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 436 + #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 437 + //MP1_SMN_C2PMSG_90 438 + #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 439 + #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 440 + //MP1_SMN_C2PMSG_91 441 + #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 442 + #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 443 + //MP1_SMN_C2PMSG_92 444 + #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 445 + #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 446 + //MP1_SMN_C2PMSG_93 447 + #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 448 + #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 449 + //MP1_SMN_C2PMSG_94 450 + #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 451 + #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 452 + //MP1_SMN_C2PMSG_95 453 + #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 454 + #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 455 + //MP1_SMN_C2PMSG_96 456 + #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 457 + #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 458 + //MP1_SMN_C2PMSG_97 459 + #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 460 + #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 461 + //MP1_SMN_C2PMSG_98 462 + #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 463 + #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 464 + //MP1_SMN_C2PMSG_99 465 + #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 466 + #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 467 + //MP1_SMN_C2PMSG_100 468 + #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 469 + #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 470 + //MP1_SMN_C2PMSG_101 471 + #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 472 + #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 473 + //MP1_SMN_C2PMSG_102 474 + #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 475 + #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 476 + //MP1_SMN_C2PMSG_103 477 + #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 478 + #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 479 + //MP1_SMN_C2PMSG_104 480 + #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 481 + #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 482 + //MP1_SMN_C2PMSG_105 483 + #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 484 + #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 485 + //MP1_SMN_C2PMSG_106 486 + #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 487 + #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 488 + //MP1_SMN_C2PMSG_107 489 + #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 490 + #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 491 + //MP1_SMN_C2PMSG_108 492 + #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 493 + #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 494 + //MP1_SMN_C2PMSG_109 495 + #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 496 + #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 497 + //MP1_SMN_C2PMSG_110 498 + #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 499 + #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 500 + //MP1_SMN_C2PMSG_111 501 + #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 502 + #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 503 + //MP1_SMN_C2PMSG_112 504 + #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 505 + #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 506 + //MP1_SMN_C2PMSG_113 507 + #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 508 + #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 509 + //MP1_SMN_C2PMSG_114 510 + #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 511 + #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 512 + //MP1_SMN_C2PMSG_115 513 + #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 514 + #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 515 + //MP1_SMN_C2PMSG_116 516 + #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 517 + #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 518 + //MP1_SMN_C2PMSG_117 519 + #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 520 + #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 521 + //MP1_SMN_C2PMSG_118 522 + #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 523 + #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 524 + //MP1_SMN_C2PMSG_119 525 + #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 526 + #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 527 + //MP1_SMN_C2PMSG_120 528 + #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 529 + #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 530 + //MP1_SMN_C2PMSG_121 531 + #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 532 + #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 533 + //MP1_SMN_C2PMSG_122 534 + #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 535 + #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 536 + //MP1_SMN_C2PMSG_123 537 + #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 538 + #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 539 + //MP1_SMN_C2PMSG_124 540 + #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 541 + #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 542 + //MP1_SMN_C2PMSG_125 543 + #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 544 + #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 545 + //MP1_SMN_C2PMSG_126 546 + #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 547 + #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 548 + //MP1_SMN_C2PMSG_127 549 + #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 550 + #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 551 + //MP1_SMN_IH_CREDIT 552 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 553 + #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 554 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 555 + #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 556 + //MP1_SMN_IH_SW_INT 557 + #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 558 + #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 559 + #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 560 + #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 561 + //MP1_SMN_IH_SW_INT_CTRL 562 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 563 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 564 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 565 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 566 + //MP1_SMN_FPS_CNT 567 + #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 568 + #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 569 + //MP1_SMN_EXT_SCRATCH0 570 + #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 571 + #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 572 + //MP1_SMN_EXT_SCRATCH1 573 + #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 574 + #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 575 + //MP1_SMN_EXT_SCRATCH2 576 + #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 577 + #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 578 + //MP1_SMN_EXT_SCRATCH3 579 + #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 580 + #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 581 + //MP1_SMN_EXT_SCRATCH4 582 + #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 583 + #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 584 + //MP1_SMN_EXT_SCRATCH5 585 + #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 586 + #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 587 + //MP1_SMN_EXT_SCRATCH6 588 + #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 589 + #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 590 + //MP1_SMN_EXT_SCRATCH7 591 + #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 592 + #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 593 + //MP1_SMN_EXT_SCRATCH8 594 + #define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 595 + #define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL 596 + //MP1_SMN_EXT_SCRATCH10 597 + #define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 598 + #define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL 599 + //MP1_SMN_EXT_SCRATCH11 600 + #define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 601 + #define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL 602 + //MP1_SMN_EXT_SCRATCH12 603 + #define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 604 + #define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL 605 + //MP1_SMN_EXT_SCRATCH13 606 + #define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 607 + #define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL 608 + //MP1_SMN_EXT_SCRATCH14 609 + #define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 610 + #define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL 611 + //MP1_SMN_EXT_SCRATCH15 612 + #define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 613 + #define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL 614 + //MP1_SMN_EXT_SCRATCH16 615 + #define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 616 + #define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL 617 + //MP1_SMN_EXT_SCRATCH17 618 + #define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 619 + #define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL 620 + //MP1_SMN_EXT_SCRATCH18 621 + #define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 622 + #define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL 623 + //MP1_SMN_EXT_SCRATCH19 624 + #define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 625 + #define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL 626 + //MP1_SMN_EXT_SCRATCH20 627 + #define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 628 + #define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL 629 + //MP1_SMN_EXT_SCRATCH21 630 + #define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 631 + #define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL 632 + //MP1_SMN_EXT_SCRATCH22 633 + #define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 634 + #define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL 635 + //MP1_SMN_EXT_SCRATCH23 636 + #define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 637 + #define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL 638 + //MP1_SMN_EXT_SCRATCH24 639 + #define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 640 + #define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL 641 + //MP1_SMN_EXT_SCRATCH25 642 + #define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 643 + #define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL 644 + //MP1_SMN_EXT_SCRATCH26 645 + #define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 646 + #define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL 647 + //MP1_SMN_EXT_SCRATCH27 648 + #define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 649 + #define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL 650 + //MP1_SMN_EXT_SCRATCH28 651 + #define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 652 + #define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL 653 + //MP1_SMN_EXT_SCRATCH29 654 + #define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 655 + #define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL 656 + //MP1_SMN_EXT_SCRATCH30 657 + #define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 658 + #define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL 659 + //MP1_SMN_EXT_SCRATCH31 660 + #define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 661 + #define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL 662 + 663 + 664 + // addressBlock: mp_SmuMp1Pub_CruDec 665 + //MP1_FIRMWARE_FLAGS 666 + #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 667 + #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 668 + #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 669 + #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 670 + 671 + 672 + #endif