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kernel
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linux
ARM: shmobile: r8a7778: common clock framework CPG driver
Driver for the r8a7778's clocks that depend on the mode bits.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
authored by
Ulrich Hecht
and committed by
Simon Horman
6232c51c
a5dc23f6
+170
+25
Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
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Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
···
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* Renesas R8A7778 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7778. It includes two PLLs and
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several fixed ratio dividers
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Required Properties:
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- compatible: Must be "renesas,r8a7778-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"plla", "pllb", "b", "out", "p", "s", and "s1".
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Example
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-------
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7778-cpg-clocks";
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reg = <0xffc80000 0x80>;
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#clock-cells = <1>;
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clocks = <&extal_clk>;
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clock-output-names = "plla", "pllb", "b",
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"out", "p", "s", "s1";
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};
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drivers/clk/shmobile/Makefile
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drivers/clk/shmobile/Makefile
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obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
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obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
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obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
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drivers/clk/shmobile/clk-r8a7778.c
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drivers/clk/shmobile/clk-r8a7778.c
···
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/*
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* r8a7778 Core CPG Clocks
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*
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/shmobile.h>
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#include <linux/of_address.h>
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struct r8a7778_cpg {
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struct clk_onecell_data data;
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spinlock_t lock;
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void __iomem *reg;
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};
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/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
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struct {
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unsigned long plla_mult;
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unsigned long pllb_mult;
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} r8a7778_rates[] __initdata = {
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[0] = { 21, 21 },
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[1] = { 24, 24 },
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[2] = { 28, 28 },
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[3] = { 32, 32 },
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[5] = { 24, 21 },
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[6] = { 28, 21 },
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[7] = { 32, 24 },
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};
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/* Clock dividers per bits 1 and 2 of MODEMR */
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struct {
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const char *name;
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unsigned int div[4];
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} r8a7778_divs[6] __initdata = {
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{ "b", { 12, 12, 16, 18 } },
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{ "out", { 12, 12, 16, 18 } },
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{ "p", { 16, 12, 16, 12 } },
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{ "s", { 4, 3, 4, 3 } },
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{ "s1", { 8, 6, 8, 6 } },
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};
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static u32 cpg_mode_rates __initdata;
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static u32 cpg_mode_divs __initdata;
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static struct clk * __init
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r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
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const char *name)
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{
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if (!strcmp(name, "plla")) {
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return clk_register_fixed_factor(NULL, "plla",
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of_clk_get_parent_name(np, 0), 0,
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r8a7778_rates[cpg_mode_rates].plla_mult, 1);
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} else if (!strcmp(name, "pllb")) {
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return clk_register_fixed_factor(NULL, "pllb",
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of_clk_get_parent_name(np, 0), 0,
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r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
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} else {
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
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if (!strcmp(name, r8a7778_divs[i].name)) {
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return clk_register_fixed_factor(NULL,
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r8a7778_divs[i].name,
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"plla", 0, 1,
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r8a7778_divs[i].div[cpg_mode_divs]);
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}
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static void __init r8a7778_cpg_clocks_init(struct device_node *np)
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{
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struct r8a7778_cpg *cpg;
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struct clk **clks;
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unsigned int i;
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int num_clks;
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (num_clks < 0) {
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pr_err("%s: failed to count clocks\n", __func__);
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return;
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}
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
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clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
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if (cpg == NULL || clks == NULL) {
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/* We're leaking memory on purpose, there's no point in cleaning
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* up as the system won't boot anyway.
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*/
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return;
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}
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spin_lock_init(&cpg->lock);
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cpg->data.clks = clks;
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cpg->data.clk_num = num_clks;
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cpg->reg = of_iomap(np, 0);
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if (WARN_ON(cpg->reg == NULL))
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return;
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i,
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&name);
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clk = r8a7778_cpg_register_clock(np, cpg, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %s %s clock (%ld)\n",
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__func__, np->name, name, PTR_ERR(clk));
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else
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cpg->data.clks[i] = clk;
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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}
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CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
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r8a7778_cpg_clocks_init);
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void __init r8a7778_clocks_init(u32 mode)
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{
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BUG_ON(!(mode & BIT(19)));
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cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
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(!!(mode & BIT(12)) << 1) |
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(!!(mode & BIT(11)));
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cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
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(!!(mode & BIT(1)));
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of_clk_init(NULL);
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}