Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/gma500: begin pruning dead bits of API

At this point we won't add an external set of definitions. We want to get
everything out before we admit to a public API beyond the standardised
ones.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

authored by

Alan Cox and committed by
Dave Airlie
61bedf70 04b3924d

+24 -644
+23 -136
drivers/gpu/drm/gma500/psb_drm.h
··· 24 24 25 25 #define PSB_NUM_PIPE 3 26 26 27 - #define PSB_GPU_ACCESS_READ (1ULL << 32) 28 - #define PSB_GPU_ACCESS_WRITE (1ULL << 33) 29 - #define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE) 30 - 31 - #define PSB_BO_FLAG_COMMAND (1ULL << 52) 32 27 33 28 /* 34 - * Feedback components: 29 + * Manage the LUT for an output 35 30 */ 36 - 37 - struct drm_psb_sizes_arg { 38 - u32 ta_mem_size; 39 - u32 mmu_size; 40 - u32 pds_size; 41 - u32 rastgeom_size; 42 - u32 tt_size; 43 - u32 vram_size; 44 - }; 45 - 46 31 struct drm_psb_dpst_lut_arg { 47 32 uint8_t lut[256]; 48 33 int output_id; 49 34 }; 50 35 51 - #define PSB_DC_CRTC_SAVE 0x01 52 - #define PSB_DC_CRTC_RESTORE 0x02 53 - #define PSB_DC_OUTPUT_SAVE 0x04 54 - #define PSB_DC_OUTPUT_RESTORE 0x08 55 - #define PSB_DC_CRTC_MASK 0x03 56 - #define PSB_DC_OUTPUT_MASK 0x0C 57 - 58 - struct drm_psb_dc_state_arg { 59 - u32 flags; 60 - u32 obj_id; 61 - }; 62 - 36 + /* 37 + * Validate modes 38 + */ 63 39 struct drm_psb_mode_operation_arg { 64 40 u32 obj_id; 65 41 u16 operation; 66 42 struct drm_mode_modeinfo mode; 67 - void *data; 43 + u64 data; 68 44 }; 69 45 46 + /* 47 + * Query the stolen memory for smarter management of 48 + * memory by the server 49 + */ 70 50 struct drm_psb_stolen_memory_arg { 71 51 u32 base; 72 52 u32 size; 73 53 }; 74 54 75 - /*Display Register Bits*/ 76 - #define REGRWBITS_PFIT_CONTROLS (1 << 0) 77 - #define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1) 78 - #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2) 79 - #define REGRWBITS_PIPEASRC (1 << 3) 80 - #define REGRWBITS_PIPEBSRC (1 << 4) 81 - #define REGRWBITS_VTOTAL_A (1 << 5) 82 - #define REGRWBITS_VTOTAL_B (1 << 6) 83 - #define REGRWBITS_DSPACNTR (1 << 8) 84 - #define REGRWBITS_DSPBCNTR (1 << 9) 85 - #define REGRWBITS_DSPCCNTR (1 << 10) 86 - 87 - /*Overlay Register Bits*/ 88 - #define OV_REGRWBITS_OVADD (1 << 0) 89 - #define OV_REGRWBITS_OGAM_ALL (1 << 1) 90 - 91 - #define OVC_REGRWBITS_OVADD (1 << 2) 92 - #define OVC_REGRWBITS_OGAM_ALL (1 << 3) 93 - 94 - struct drm_psb_register_rw_arg { 95 - u32 b_force_hw_on; 96 - 97 - u32 display_read_mask; 98 - u32 display_write_mask; 99 - 100 - struct { 101 - u32 pfit_controls; 102 - u32 pfit_autoscale_ratios; 103 - u32 pfit_programmed_scale_ratios; 104 - u32 pipeasrc; 105 - u32 pipebsrc; 106 - u32 vtotal_a; 107 - u32 vtotal_b; 108 - } display; 109 - 110 - u32 overlay_read_mask; 111 - u32 overlay_write_mask; 112 - 113 - struct { 114 - u32 OVADD; 115 - u32 OGAMC0; 116 - u32 OGAMC1; 117 - u32 OGAMC2; 118 - u32 OGAMC3; 119 - u32 OGAMC4; 120 - u32 OGAMC5; 121 - u32 IEP_ENABLED; 122 - u32 IEP_BLE_MINMAX; 123 - u32 IEP_BSSCC_CONTROL; 124 - u32 b_wait_vblank; 125 - } overlay; 126 - 127 - u32 sprite_enable_mask; 128 - u32 sprite_disable_mask; 129 - 130 - struct { 131 - u32 dspa_control; 132 - u32 dspa_key_value; 133 - u32 dspa_key_mask; 134 - u32 dspc_control; 135 - u32 dspc_stride; 136 - u32 dspc_position; 137 - u32 dspc_linear_offset; 138 - u32 dspc_size; 139 - u32 dspc_surface; 140 - } sprite; 141 - 142 - u32 subpicture_enable_mask; 143 - u32 subpicture_disable_mask; 144 - }; 145 - 146 - /* Controlling the kernel modesetting buffers */ 147 - 148 - #define DRM_PSB_SIZES 0x07 149 - #define DRM_PSB_FUSE_REG 0x08 150 - #define DRM_PSB_DC_STATE 0x0A 151 - #define DRM_PSB_ADB 0x0B 152 - #define DRM_PSB_MODE_OPERATION 0x0C 153 - #define DRM_PSB_STOLEN_MEMORY 0x0D 154 - #define DRM_PSB_REGISTER_RW 0x0E 155 - 156 - /* 157 - * NOTE: Add new commands here, but increment 158 - * the values below and increment their 159 - * corresponding defines where they're 160 - * defined elsewhere. 161 - */ 162 - 163 - #define DRM_PSB_GEM_CREATE 0x10 164 - #define DRM_PSB_2D_OP 0x11 /* Will be merged later */ 165 - #define DRM_PSB_GEM_MMAP 0x12 166 - #define DRM_PSB_DPST 0x1B 167 - #define DRM_PSB_GAMMA 0x1C 168 - #define DRM_PSB_DPST_BL 0x1D 169 - #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F 170 - 171 - #define PSB_MODE_OPERATION_MODE_VALID 0x01 172 - #define PSB_MODE_OPERATION_SET_DC_BASE 0x02 173 - 174 55 struct drm_psb_get_pipe_from_crtc_id_arg { 175 56 /** ID of CRTC being requested **/ 176 57 u32 crtc_id; 177 - 178 58 /** pipe of requested CRTC **/ 179 59 u32 pipe; 180 60 }; 181 - 182 - /* FIXME: move this into a medfield header once we are sure it isn't needed for an 183 - ioctl */ 184 - struct psb_drm_dpu_rect { 185 - int x, y; 186 - int width, height; 187 - }; 188 61 189 62 struct drm_psb_gem_create { 190 63 __u64 size; ··· 76 203 */ 77 204 __u64 offset; 78 205 }; 206 + 207 + /* Controlling the kernel modesetting buffers */ 208 + 209 + #define DRM_PSB_GEM_CREATE 0x00 /* Create a GEM object */ 210 + #define DRM_PSB_GEM_MMAP 0x01 /* Map GEM memory */ 211 + #define DRM_PSB_STOLEN_MEMORY 0x02 /* Report stolen memory */ 212 + #define DRM_PSB_2D_OP 0x03 /* Will be merged later */ 213 + #define DRM_PSB_GAMMA 0x04 /* Set gamma table */ 214 + #define DRM_PSB_ADB 0x05 /* Get backlight */ 215 + #define DRM_PSB_DPST_BL 0x06 /* Set backlight */ 216 + #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1 /* CRTC to physical pipe# */ 217 + #define DRM_PSB_MODE_OPERATION 0x07 /* Mode validation/DC set */ 218 + #define PSB_MODE_OPERATION_MODE_VALID 0x01 219 + 79 220 80 221 #endif
+1 -506
drivers/gpu/drm/gma500/psb_drv.c
··· 80 80 * Standard IOCTLs. 81 81 */ 82 82 83 - #define DRM_IOCTL_PSB_SIZES \ 84 - DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \ 85 - struct drm_psb_sizes_arg) 86 - #define DRM_IOCTL_PSB_FUSE_REG \ 87 - DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t) 88 - #define DRM_IOCTL_PSB_DC_STATE \ 89 - DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \ 90 - struct drm_psb_dc_state_arg) 91 83 #define DRM_IOCTL_PSB_ADB \ 92 84 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t) 93 85 #define DRM_IOCTL_PSB_MODE_OPERATION \ ··· 88 96 #define DRM_IOCTL_PSB_STOLEN_MEMORY \ 89 97 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \ 90 98 struct drm_psb_stolen_memory_arg) 91 - #define DRM_IOCTL_PSB_REGISTER_RW \ 92 - DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \ 93 - struct drm_psb_register_rw_arg) 94 - #define DRM_IOCTL_PSB_DPST \ 95 - DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \ 96 - uint32_t) 97 99 #define DRM_IOCTL_PSB_GAMMA \ 98 100 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \ 99 101 struct drm_psb_dpst_lut_arg) ··· 104 118 DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \ 105 119 struct drm_psb_gem_mmap) 106 120 107 - static int psb_sizes_ioctl(struct drm_device *dev, void *data, 108 - struct drm_file *file_priv); 109 - static int psb_dc_state_ioctl(struct drm_device *dev, void * data, 110 - struct drm_file *file_priv); 111 121 static int psb_adb_ioctl(struct drm_device *dev, void *data, 112 122 struct drm_file *file_priv); 113 123 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data, 114 124 struct drm_file *file_priv); 115 125 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data, 116 126 struct drm_file *file_priv); 117 - static int psb_register_rw_ioctl(struct drm_device *dev, void *data, 118 - struct drm_file *file_priv); 119 - static int psb_dpst_ioctl(struct drm_device *dev, void *data, 120 - struct drm_file *file_priv); 121 127 static int psb_gamma_ioctl(struct drm_device *dev, void *data, 122 128 struct drm_file *file_priv); 123 129 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data, ··· 119 141 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func} 120 142 121 143 static struct drm_ioctl_desc psb_ioctls[] = { 122 - PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH), 123 - PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH), 124 144 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH), 125 145 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl, 126 146 DRM_AUTH), 127 147 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl, 128 148 DRM_AUTH), 129 - PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl, 130 - DRM_AUTH), 131 - PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH), 132 149 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH), 133 150 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH), 134 151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID, ··· 415 442 return 0; 416 443 } 417 444 418 - 419 - static int psb_sizes_ioctl(struct drm_device *dev, void *data, 420 - struct drm_file *file_priv) 421 - { 422 - struct drm_psb_private *dev_priv = psb_priv(dev); 423 - struct drm_psb_sizes_arg *arg = 424 - (struct drm_psb_sizes_arg *) data; 425 - 426 - *arg = dev_priv->sizes; 427 - return 0; 428 - } 429 - 430 - static int psb_dc_state_ioctl(struct drm_device *dev, void * data, 431 - struct drm_file *file_priv) 432 - { 433 - uint32_t flags; 434 - uint32_t obj_id; 435 - struct drm_mode_object *obj; 436 - struct drm_connector *connector; 437 - struct drm_crtc *crtc; 438 - struct drm_psb_dc_state_arg *arg = data; 439 - 440 - 441 - /* Double check MRST case */ 442 - if (IS_MRST(dev) || IS_MFLD(dev)) 443 - return -EOPNOTSUPP; 444 - 445 - flags = arg->flags; 446 - obj_id = arg->obj_id; 447 - 448 - if (flags & PSB_DC_CRTC_MASK) { 449 - obj = drm_mode_object_find(dev, obj_id, 450 - DRM_MODE_OBJECT_CRTC); 451 - if (!obj) { 452 - dev_dbg(dev->dev, "Invalid CRTC object.\n"); 453 - return -EINVAL; 454 - } 455 - 456 - crtc = obj_to_crtc(obj); 457 - 458 - mutex_lock(&dev->mode_config.mutex); 459 - if (drm_helper_crtc_in_use(crtc)) { 460 - if (flags & PSB_DC_CRTC_SAVE) 461 - crtc->funcs->save(crtc); 462 - else 463 - crtc->funcs->restore(crtc); 464 - } 465 - mutex_unlock(&dev->mode_config.mutex); 466 - 467 - return 0; 468 - } else if (flags & PSB_DC_OUTPUT_MASK) { 469 - obj = drm_mode_object_find(dev, obj_id, 470 - DRM_MODE_OBJECT_CONNECTOR); 471 - if (!obj) { 472 - dev_dbg(dev->dev, "Invalid connector id.\n"); 473 - return -EINVAL; 474 - } 475 - 476 - connector = obj_to_connector(obj); 477 - if (flags & PSB_DC_OUTPUT_SAVE) 478 - connector->funcs->save(connector); 479 - else 480 - connector->funcs->restore(connector); 481 - 482 - return 0; 483 - } 484 - return -EINVAL; 485 - } 486 - 487 445 static inline void get_brightness(struct backlight_device *bd) 488 446 { 489 447 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE ··· 447 543 return 0; 448 544 } 449 545 450 - /* return the current mode to the dpst module */ 451 - static int psb_dpst_ioctl(struct drm_device *dev, void *data, 452 - struct drm_file *file_priv) 453 - { 454 - struct drm_psb_private *dev_priv = psb_priv(dev); 455 - uint32_t *arg = data; 456 - uint32_t x; 457 - uint32_t y; 458 - uint32_t reg; 459 - 460 - if (!gma_power_begin(dev, 0)) 461 - return -EIO; 462 - 463 - reg = PSB_RVDC32(PIPEASRC); 464 - 465 - gma_power_end(dev); 466 - 467 - /* horizontal is the left 16 bits */ 468 - x = reg >> 16; 469 - /* vertical is the right 16 bits */ 470 - y = reg & 0x0000ffff; 471 - 472 - /* the values are the image size minus one */ 473 - x++; 474 - y++; 475 - 476 - *arg = (x << 16) | y; 477 - 478 - return 0; 479 - } 480 546 static int psb_gamma_ioctl(struct drm_device *dev, void *data, 481 547 struct drm_file *file_priv) 482 548 { ··· 487 613 struct drm_psb_mode_operation_arg *arg; 488 614 struct drm_mode_object *obj; 489 615 struct drm_connector *connector; 490 - struct drm_framebuffer *drm_fb; 491 - struct psb_framebuffer *psb_fb; 492 616 struct drm_connector_helper_funcs *connector_funcs; 493 617 int ret = 0; 494 618 int resp = MODE_OK; 495 - struct drm_psb_private *dev_priv = psb_priv(dev); 496 619 497 620 arg = (struct drm_psb_mode_operation_arg *)data; 498 621 obj_id = arg->obj_id; 499 622 op = arg->operation; 500 623 501 624 switch (op) { 502 - case PSB_MODE_OPERATION_SET_DC_BASE: 503 - obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB); 504 - if (!obj) { 505 - dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id); 506 - return -EINVAL; 507 - } 508 - 509 - drm_fb = obj_to_fb(obj); 510 - psb_fb = to_psb_fb(drm_fb); 511 - 512 - if (gma_power_begin(dev, 0)) { 513 - REG_WRITE(DSPASURF, psb_fb->gtt->offset); 514 - REG_READ(DSPASURF); 515 - gma_power_end(dev); 516 - } else { 517 - dev_priv->saveDSPASURF = psb_fb->gtt->offset; 518 - } 519 - 520 - return 0; 521 625 case PSB_MODE_OPERATION_MODE_VALID: 522 626 umode = &arg->mode; 523 627 ··· 541 689 542 690 if (connector_funcs->mode_valid) { 543 691 resp = connector_funcs->mode_valid(connector, mode); 544 - arg->data = (void *)resp; 692 + arg->data = resp; 545 693 } 546 694 547 695 /*do some clean up work*/ ··· 567 715 568 716 arg->base = dev_priv->stolen_base; 569 717 arg->size = dev_priv->vram_stolen_size; 570 - 571 - return 0; 572 - } 573 - 574 - /* FIXME: needs Medfield changes */ 575 - static int psb_register_rw_ioctl(struct drm_device *dev, void *data, 576 - struct drm_file *file_priv) 577 - { 578 - struct drm_psb_private *dev_priv = psb_priv(dev); 579 - struct drm_psb_register_rw_arg *arg = data; 580 - bool usage = arg->b_force_hw_on ? true : false; 581 - 582 - if (arg->display_write_mask != 0) { 583 - if (gma_power_begin(dev, usage)) { 584 - if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS) 585 - PSB_WVDC32(arg->display.pfit_controls, 586 - PFIT_CONTROL); 587 - if (arg->display_write_mask & 588 - REGRWBITS_PFIT_AUTOSCALE_RATIOS) 589 - PSB_WVDC32(arg->display.pfit_autoscale_ratios, 590 - PFIT_AUTO_RATIOS); 591 - if (arg->display_write_mask & 592 - REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS) 593 - PSB_WVDC32( 594 - arg->display.pfit_programmed_scale_ratios, 595 - PFIT_PGM_RATIOS); 596 - if (arg->display_write_mask & REGRWBITS_PIPEASRC) 597 - PSB_WVDC32(arg->display.pipeasrc, 598 - PIPEASRC); 599 - if (arg->display_write_mask & REGRWBITS_PIPEBSRC) 600 - PSB_WVDC32(arg->display.pipebsrc, 601 - PIPEBSRC); 602 - if (arg->display_write_mask & REGRWBITS_VTOTAL_A) 603 - PSB_WVDC32(arg->display.vtotal_a, 604 - VTOTAL_A); 605 - if (arg->display_write_mask & REGRWBITS_VTOTAL_B) 606 - PSB_WVDC32(arg->display.vtotal_b, 607 - VTOTAL_B); 608 - gma_power_end(dev); 609 - } else { 610 - if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS) 611 - dev_priv->savePFIT_CONTROL = 612 - arg->display.pfit_controls; 613 - if (arg->display_write_mask & 614 - REGRWBITS_PFIT_AUTOSCALE_RATIOS) 615 - dev_priv->savePFIT_AUTO_RATIOS = 616 - arg->display.pfit_autoscale_ratios; 617 - if (arg->display_write_mask & 618 - REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS) 619 - dev_priv->savePFIT_PGM_RATIOS = 620 - arg->display.pfit_programmed_scale_ratios; 621 - if (arg->display_write_mask & REGRWBITS_PIPEASRC) 622 - dev_priv->savePIPEASRC = arg->display.pipeasrc; 623 - if (arg->display_write_mask & REGRWBITS_PIPEBSRC) 624 - dev_priv->savePIPEBSRC = arg->display.pipebsrc; 625 - if (arg->display_write_mask & REGRWBITS_VTOTAL_A) 626 - dev_priv->saveVTOTAL_A = arg->display.vtotal_a; 627 - if (arg->display_write_mask & REGRWBITS_VTOTAL_B) 628 - dev_priv->saveVTOTAL_B = arg->display.vtotal_b; 629 - } 630 - } 631 - 632 - if (arg->display_read_mask != 0) { 633 - if (gma_power_begin(dev, usage)) { 634 - if (arg->display_read_mask & 635 - REGRWBITS_PFIT_CONTROLS) 636 - arg->display.pfit_controls = 637 - PSB_RVDC32(PFIT_CONTROL); 638 - if (arg->display_read_mask & 639 - REGRWBITS_PFIT_AUTOSCALE_RATIOS) 640 - arg->display.pfit_autoscale_ratios = 641 - PSB_RVDC32(PFIT_AUTO_RATIOS); 642 - if (arg->display_read_mask & 643 - REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS) 644 - arg->display.pfit_programmed_scale_ratios = 645 - PSB_RVDC32(PFIT_PGM_RATIOS); 646 - if (arg->display_read_mask & REGRWBITS_PIPEASRC) 647 - arg->display.pipeasrc = PSB_RVDC32(PIPEASRC); 648 - if (arg->display_read_mask & REGRWBITS_PIPEBSRC) 649 - arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC); 650 - if (arg->display_read_mask & REGRWBITS_VTOTAL_A) 651 - arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A); 652 - if (arg->display_read_mask & REGRWBITS_VTOTAL_B) 653 - arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B); 654 - gma_power_end(dev); 655 - } else { 656 - if (arg->display_read_mask & 657 - REGRWBITS_PFIT_CONTROLS) 658 - arg->display.pfit_controls = 659 - dev_priv->savePFIT_CONTROL; 660 - if (arg->display_read_mask & 661 - REGRWBITS_PFIT_AUTOSCALE_RATIOS) 662 - arg->display.pfit_autoscale_ratios = 663 - dev_priv->savePFIT_AUTO_RATIOS; 664 - if (arg->display_read_mask & 665 - REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS) 666 - arg->display.pfit_programmed_scale_ratios = 667 - dev_priv->savePFIT_PGM_RATIOS; 668 - if (arg->display_read_mask & REGRWBITS_PIPEASRC) 669 - arg->display.pipeasrc = dev_priv->savePIPEASRC; 670 - if (arg->display_read_mask & REGRWBITS_PIPEBSRC) 671 - arg->display.pipebsrc = dev_priv->savePIPEBSRC; 672 - if (arg->display_read_mask & REGRWBITS_VTOTAL_A) 673 - arg->display.vtotal_a = dev_priv->saveVTOTAL_A; 674 - if (arg->display_read_mask & REGRWBITS_VTOTAL_B) 675 - arg->display.vtotal_b = dev_priv->saveVTOTAL_B; 676 - } 677 - } 678 - 679 - if (arg->overlay_write_mask != 0) { 680 - if (gma_power_begin(dev, usage)) { 681 - if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) { 682 - PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5); 683 - PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4); 684 - PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3); 685 - PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2); 686 - PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1); 687 - PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0); 688 - } 689 - if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) { 690 - PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5); 691 - PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4); 692 - PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3); 693 - PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2); 694 - PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1); 695 - PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0); 696 - } 697 - 698 - if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) { 699 - PSB_WVDC32(arg->overlay.OVADD, OV_OVADD); 700 - 701 - if (arg->overlay.b_wait_vblank) { 702 - /* Wait for 20ms.*/ 703 - unsigned long vblank_timeout = jiffies 704 - + HZ/50; 705 - uint32_t temp; 706 - while (time_before_eq(jiffies, 707 - vblank_timeout)) { 708 - temp = PSB_RVDC32(OV_DOVASTA); 709 - if ((temp & (0x1 << 31)) != 0) 710 - break; 711 - cpu_relax(); 712 - } 713 - } 714 - } 715 - if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) { 716 - PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD); 717 - if (arg->overlay.b_wait_vblank) { 718 - /* Wait for 20ms.*/ 719 - unsigned long vblank_timeout = 720 - jiffies + HZ/50; 721 - uint32_t temp; 722 - while (time_before_eq(jiffies, 723 - vblank_timeout)) { 724 - temp = PSB_RVDC32(OVC_DOVCSTA); 725 - if ((temp & (0x1 << 31)) != 0) 726 - break; 727 - cpu_relax(); 728 - } 729 - } 730 - } 731 - gma_power_end(dev); 732 - } else { 733 - if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) { 734 - dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5; 735 - dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4; 736 - dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3; 737 - dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2; 738 - dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1; 739 - dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0; 740 - } 741 - if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) { 742 - dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5; 743 - dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4; 744 - dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3; 745 - dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2; 746 - dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1; 747 - dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0; 748 - } 749 - if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) 750 - dev_priv->saveOV_OVADD = arg->overlay.OVADD; 751 - if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) 752 - dev_priv->saveOVC_OVADD = arg->overlay.OVADD; 753 - } 754 - } 755 - 756 - if (arg->overlay_read_mask != 0) { 757 - if (gma_power_begin(dev, usage)) { 758 - if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) { 759 - arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5); 760 - arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4); 761 - arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3); 762 - arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2); 763 - arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1); 764 - arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0); 765 - } 766 - if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) { 767 - arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5); 768 - arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4); 769 - arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3); 770 - arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2); 771 - arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1); 772 - arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0); 773 - } 774 - if (arg->overlay_read_mask & OV_REGRWBITS_OVADD) 775 - arg->overlay.OVADD = PSB_RVDC32(OV_OVADD); 776 - if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD) 777 - arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD); 778 - gma_power_end(dev); 779 - } else { 780 - if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) { 781 - arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5; 782 - arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4; 783 - arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3; 784 - arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2; 785 - arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1; 786 - arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0; 787 - } 788 - if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) { 789 - arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5; 790 - arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4; 791 - arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3; 792 - arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2; 793 - arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1; 794 - arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0; 795 - } 796 - if (arg->overlay_read_mask & OV_REGRWBITS_OVADD) 797 - arg->overlay.OVADD = dev_priv->saveOV_OVADD; 798 - if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD) 799 - arg->overlay.OVADD = dev_priv->saveOVC_OVADD; 800 - } 801 - } 802 - 803 - if (arg->sprite_enable_mask != 0) { 804 - if (gma_power_begin(dev, usage)) { 805 - PSB_WVDC32(0x1F3E, DSPARB); 806 - PSB_WVDC32(arg->sprite.dspa_control 807 - | PSB_RVDC32(DSPACNTR), DSPACNTR); 808 - PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL); 809 - PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK); 810 - PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF); 811 - PSB_RVDC32(DSPASURF); 812 - PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR); 813 - PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE); 814 - PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS); 815 - PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF); 816 - PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE); 817 - PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF); 818 - PSB_RVDC32(DSPCSURF); 819 - gma_power_end(dev); 820 - } 821 - } 822 - 823 - if (arg->sprite_disable_mask != 0) { 824 - if (gma_power_begin(dev, usage)) { 825 - PSB_WVDC32(0x3F3E, DSPARB); 826 - PSB_WVDC32(0x0, DSPCCNTR); 827 - PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF); 828 - PSB_RVDC32(DSPCSURF); 829 - gma_power_end(dev); 830 - } 831 - } 832 - 833 - if (arg->subpicture_enable_mask != 0) { 834 - if (gma_power_begin(dev, usage)) { 835 - uint32_t temp; 836 - if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) { 837 - temp = PSB_RVDC32(DSPACNTR); 838 - temp &= ~DISPPLANE_PIXFORMAT_MASK; 839 - temp &= ~DISPPLANE_BOTTOM; 840 - temp |= DISPPLANE_32BPP; 841 - PSB_WVDC32(temp, DSPACNTR); 842 - 843 - temp = PSB_RVDC32(DSPABASE); 844 - PSB_WVDC32(temp, DSPABASE); 845 - PSB_RVDC32(DSPABASE); 846 - temp = PSB_RVDC32(DSPASURF); 847 - PSB_WVDC32(temp, DSPASURF); 848 - PSB_RVDC32(DSPASURF); 849 - } 850 - if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) { 851 - temp = PSB_RVDC32(DSPBCNTR); 852 - temp &= ~DISPPLANE_PIXFORMAT_MASK; 853 - temp &= ~DISPPLANE_BOTTOM; 854 - temp |= DISPPLANE_32BPP; 855 - PSB_WVDC32(temp, DSPBCNTR); 856 - 857 - temp = PSB_RVDC32(DSPBBASE); 858 - PSB_WVDC32(temp, DSPBBASE); 859 - PSB_RVDC32(DSPBBASE); 860 - temp = PSB_RVDC32(DSPBSURF); 861 - PSB_WVDC32(temp, DSPBSURF); 862 - PSB_RVDC32(DSPBSURF); 863 - } 864 - if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) { 865 - temp = PSB_RVDC32(DSPCCNTR); 866 - temp &= ~DISPPLANE_PIXFORMAT_MASK; 867 - temp &= ~DISPPLANE_BOTTOM; 868 - temp |= DISPPLANE_32BPP; 869 - PSB_WVDC32(temp, DSPCCNTR); 870 - 871 - temp = PSB_RVDC32(DSPCBASE); 872 - PSB_WVDC32(temp, DSPCBASE); 873 - PSB_RVDC32(DSPCBASE); 874 - temp = PSB_RVDC32(DSPCSURF); 875 - PSB_WVDC32(temp, DSPCSURF); 876 - PSB_RVDC32(DSPCSURF); 877 - } 878 - gma_power_end(dev); 879 - } 880 - } 881 - 882 - if (arg->subpicture_disable_mask != 0) { 883 - if (gma_power_begin(dev, usage)) { 884 - uint32_t temp; 885 - if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) { 886 - temp = PSB_RVDC32(DSPACNTR); 887 - temp &= ~DISPPLANE_PIXFORMAT_MASK; 888 - temp |= DISPPLANE_32BPP_NO_ALPHA; 889 - PSB_WVDC32(temp, DSPACNTR); 890 - 891 - temp = PSB_RVDC32(DSPABASE); 892 - PSB_WVDC32(temp, DSPABASE); 893 - PSB_RVDC32(DSPABASE); 894 - temp = PSB_RVDC32(DSPASURF); 895 - PSB_WVDC32(temp, DSPASURF); 896 - PSB_RVDC32(DSPASURF); 897 - } 898 - if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) { 899 - temp = PSB_RVDC32(DSPBCNTR); 900 - temp &= ~DISPPLANE_PIXFORMAT_MASK; 901 - temp |= DISPPLANE_32BPP_NO_ALPHA; 902 - PSB_WVDC32(temp, DSPBCNTR); 903 - 904 - temp = PSB_RVDC32(DSPBBASE); 905 - PSB_WVDC32(temp, DSPBBASE); 906 - PSB_RVDC32(DSPBBASE); 907 - temp = PSB_RVDC32(DSPBSURF); 908 - PSB_WVDC32(temp, DSPBSURF); 909 - PSB_RVDC32(DSPBSURF); 910 - } 911 - if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) { 912 - temp = PSB_RVDC32(DSPCCNTR); 913 - temp &= ~DISPPLANE_PIXFORMAT_MASK; 914 - temp |= DISPPLANE_32BPP_NO_ALPHA; 915 - PSB_WVDC32(temp, DSPCCNTR); 916 - 917 - temp = PSB_RVDC32(DSPCBASE); 918 - PSB_WVDC32(temp, DSPCBASE); 919 - PSB_RVDC32(DSPCBASE); 920 - temp = PSB_RVDC32(DSPCSURF); 921 - PSB_WVDC32(temp, DSPCSURF); 922 - PSB_RVDC32(DSPCSURF); 923 - } 924 - gma_power_end(dev); 925 - } 926 - } 927 718 928 719 return 0; 929 720 }
-2
drivers/gpu/drm/gma500/psb_drv.h
··· 324 324 * Sizes info 325 325 */ 326 326 327 - struct drm_psb_sizes_arg sizes; 328 - 329 327 u32 fuse_reg_value; 330 328 u32 video_device_fuse; 331 329