tjh.dev / kernel
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staging: rtl8723bs: clean driver from unused RF paths

rtl8723bs support only two rf paths (A and B), remove all
the others (C, D, BC, ...) as they are unused. Keep
just one enum selecting rf path, remove unused macro
indicating max rf path number, add an item in rf_path
enum for this pourpose.

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Link: https://lore.kernel.org/r/23060c85ab9aa468c9c021378f0dc8a8f887a578.1628329348.git.fabioaiuto83@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Fabio Aiuto and committed by
Greg Kroah-Hartman 61b919fe e3678dc1

+185 -214
+26 -26
drivers/staging/rtl8723bs/hal/HalPhyRf.c
··· 30 30 pDM_Odm->BbSwingIdxCck = pDM_Odm->DefaultCckIndex; 31 31 pDM_Odm->RFCalibrateInfo.CCK_index = 0; 32 32 33 - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { 33 + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { 34 34 pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex; 35 35 pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->DefaultOfdmIndex; 36 36 pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex; ··· 93 93 pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; 94 94 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = true; 95 95 96 - ThermalValue = (u8)PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ 96 + ThermalValue = (u8)PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, c.ThermalRegAddr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ 97 97 if ( 98 98 !pDM_Odm->RFCalibrateInfo.TxPowerTrackControl || 99 99 pHalData->EEPROMThermalMeter == 0 || ··· 154 154 155 155 /* 4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset */ 156 156 if (ThermalValue > pHalData->EEPROMThermalMeter) { 157 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = 158 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A]; 159 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = 157 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[RF_PATH_A] = 158 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_A]; 159 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_A] = 160 160 deltaSwingTableIdx_TUP_A[delta]; 161 161 162 162 /* Record delta swing for mix mode power tracking */ 163 - pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = 163 + pDM_Odm->Absolute_OFDMSwingIdx[RF_PATH_A] = 164 164 deltaSwingTableIdx_TUP_A[delta]; 165 165 166 166 if (c.RfPathCount > 1) { 167 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = 168 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B]; 169 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = 167 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[RF_PATH_B] = 168 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_B]; 169 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_B] = 170 170 deltaSwingTableIdx_TUP_B[delta]; 171 171 172 172 /* Record delta swing for mix mode power tracking */ 173 - pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = 173 + pDM_Odm->Absolute_OFDMSwingIdx[RF_PATH_B] = 174 174 deltaSwingTableIdx_TUP_B[delta]; 175 175 } 176 176 177 177 } else { 178 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = 179 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A]; 180 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = 178 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[RF_PATH_A] = 179 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_A]; 180 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_A] = 181 181 -1 * deltaSwingTableIdx_TDOWN_A[delta]; 182 182 183 183 /* Record delta swing for mix mode power tracking */ 184 - pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = 184 + pDM_Odm->Absolute_OFDMSwingIdx[RF_PATH_A] = 185 185 -1 * deltaSwingTableIdx_TDOWN_A[delta]; 186 186 187 187 if (c.RfPathCount > 1) { 188 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = 189 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B]; 190 - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = 188 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[RF_PATH_B] = 189 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_B]; 190 + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[RF_PATH_B] = 191 191 -1 * deltaSwingTableIdx_TDOWN_B[delta]; 192 192 193 193 /* Record delta swing for mix mode power tracking */ 194 - pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = 194 + pDM_Odm->Absolute_OFDMSwingIdx[RF_PATH_B] = 195 195 -1 * deltaSwingTableIdx_TDOWN_B[delta]; 196 196 } 197 197 } 198 198 199 - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { 199 + for (p = RF_PATH_A; p < c.RfPathCount; p++) { 200 200 if ( 201 201 pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] == 202 202 pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] ··· 230 230 /* else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) */ 231 231 /* pDM_Odm->RFCalibrateInfo.CCK_index = 0; */ 232 232 } else { 233 - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) 233 + for (p = RF_PATH_A; p < c.RfPathCount; p++) 234 234 pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0; 235 235 } 236 236 237 237 /* Print Swing base & current */ 238 - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { 238 + for (p = RF_PATH_A; p < c.RfPathCount; p++) { 239 239 } 240 240 241 241 if ( 242 - (pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A] != 0 || 243 - pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0) && 242 + (pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RF_PATH_A] != 0 || 243 + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RF_PATH_B] != 0) && 244 244 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl 245 245 ) { 246 246 /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ ··· 253 253 /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ 254 254 255 255 if (ThermalValue > pHalData->EEPROMThermalMeter) { 256 - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) 256 + for (p = RF_PATH_A; p < c.RfPathCount; p++) 257 257 (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); 258 258 } else { 259 - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) 259 + for (p = RF_PATH_A; p < c.RfPathCount; p++) 260 260 (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); 261 261 } 262 262 263 263 /* Record last time Power Tracking result as base. */ 264 264 pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck; 265 - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) 265 + for (p = RF_PATH_A; p < c.RfPathCount; p++) 266 266 pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->BbSwingIdxOfdm[p]; 267 267 268 268 /* Record last Power Tracking Thermal Value */
+82 -82
drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
··· 67 67 IqkResult_Y = IqkResult_Y | 0xFFFFFC00; 68 68 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; 69 69 70 - /* if (RFPath == ODM_RF_PATH_A) */ 70 + /* if (RFPath == RF_PATH_A) */ 71 71 switch (RFPath) { 72 - case ODM_RF_PATH_A: 72 + case RF_PATH_A: 73 73 /* write new elements A, C, D to regC80 and regC94, 74 74 * element B is always 0 75 75 */ ··· 82 82 value32 = ((IqkResult_X * ele_D)>>7)&0x01; 83 83 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32); 84 84 break; 85 - case ODM_RF_PATH_B: 85 + case RF_PATH_B: 86 86 /* write new elements A, C, D to regC88 and regC9C, 87 87 * element B is always 0 88 88 */ ··· 101 101 } 102 102 } else { 103 103 switch (RFPath) { 104 - case ODM_RF_PATH_A: 104 + case RF_PATH_A: 105 105 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); 106 106 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); 107 107 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00); 108 108 break; 109 109 110 - case ODM_RF_PATH_B: 110 + case RF_PATH_B: 111 111 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); 112 112 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); 113 113 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); ··· 380 380 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 381 381 382 382 /* enable path A PA in TXIQK mode */ 383 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 384 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 385 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); 386 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); 383 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 384 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 385 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); 386 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); 387 387 /* disable path B PA in TXIQK mode */ 388 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */ 389 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */ 388 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */ 389 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */ 390 390 391 391 /* 1 Tx IQK */ 392 392 /* IQK setting */ ··· 480 480 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 481 481 /* 1 Get TXIMR setting */ 482 482 /* modify RXIQK mode table */ 483 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 484 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 485 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 483 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 484 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 485 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 486 486 /* LNA2 off, PA on for Dcut */ 487 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 488 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 487 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 488 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 489 489 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 490 490 491 491 /* IQK setting */ ··· 564 564 565 565 /* modify RXIQK mode table */ 566 566 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 567 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 568 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 569 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 567 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 568 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 569 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 570 570 /* LAN2 on, PA off for Dcut */ 571 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 572 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 571 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 572 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 573 573 574 574 /* PA, PAD setting */ 575 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); 576 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); 575 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); 576 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); 577 577 578 578 579 579 /* IQK setting */ ··· 631 631 /* PA/PAD controlled by 0x0 */ 632 632 /* leave IQK mode */ 633 633 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 634 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); 634 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); 635 635 636 636 /* Allen 20131125 */ 637 637 tmp = (regEAC & 0x03FF0000)>>16; ··· 666 666 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 667 667 668 668 /* in TXIQK mode */ 669 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ 670 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */ 671 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */ 672 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */ 669 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ 670 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */ 671 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */ 672 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */ 673 673 /* enable path B PA in TXIQK mode */ 674 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 675 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1); 674 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); 675 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1); 676 676 677 677 678 678 ··· 700 700 701 701 /* switch to path B */ 702 702 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 703 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 703 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 704 704 705 705 /* GNT_BT = 0 */ 706 706 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); ··· 760 760 /* switch to path B */ 761 761 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 762 762 /* modify RXIQK mode table */ 763 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 764 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 765 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 766 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 763 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 764 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 765 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 766 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 767 767 /* open PA S1 & SMIXER */ 768 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 769 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd); 768 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); 769 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd); 770 770 771 771 772 772 /* IQK setting */ ··· 794 794 795 795 /* switch to path B */ 796 796 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 797 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 797 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 798 798 799 799 /* GNT_BT = 0 */ 800 800 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); ··· 844 844 /* modify RXIQK mode table */ 845 845 /* 20121009, Kordan> RF Mode = 3 */ 846 846 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 847 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 848 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 849 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 850 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 851 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 847 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 848 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 849 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 850 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 851 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 852 852 853 853 /* open PA S1 & close SMIXER */ 854 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 855 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd); 854 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); 855 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd); 856 856 857 857 /* PA, PAD setting */ 858 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */ 859 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */ 858 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */ 859 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */ 860 860 861 861 /* IQK setting */ 862 862 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); ··· 881 881 882 882 /* switch to path B */ 883 883 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 884 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 884 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 885 885 886 886 /* GNT_BT = 0 */ 887 887 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); ··· 909 909 /* PA/PAD controlled by 0x0 */ 910 910 /* leave IQK mode */ 911 911 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */ 912 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */ 912 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */ 913 913 914 914 915 915 ··· 1384 1384 1385 1385 /* save RF path for 8723B */ 1386 1386 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ 1387 - /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */ 1387 + /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */ 1388 1388 1389 1389 /* MAC settings */ 1390 1390 _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ··· 1406 1406 /* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */ 1407 1407 1408 1408 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1409 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1410 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); 1411 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1412 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 1413 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 1414 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); 1409 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1410 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); 1411 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1412 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 1413 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); 1414 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); 1415 1415 1416 1416 /* path A TX IQK */ 1417 1417 for (i = 0 ; i < retryCount ; i++) { ··· 1420 1420 if (PathAOK == 0x01) { 1421 1421 /* Path A Tx IQK Success */ 1422 1422 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1423 - pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); 1423 + pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x8, bRFRegOffsetMask); 1424 1424 1425 1425 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1426 1426 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ··· 1452 1452 if (PathBOK == 0x01) { 1453 1453 /* Path B Tx IQK Success */ 1454 1454 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1455 - pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); 1455 + pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_B, 0x8, bRFRegOffsetMask); 1456 1456 1457 1457 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1458 1458 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ··· 1489 1489 1490 1490 /* Reload RF path */ 1491 1491 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ 1492 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1492 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1493 1493 1494 1494 /* Allen initial gain 0xc50 */ 1495 1495 /* Restore RX initial gain */ ··· 1526 1526 if ((tmpReg&0x70) != 0) { 1527 1527 /* 1. Read original RF mode */ 1528 1528 /* Path-A */ 1529 - RF_Amode = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); 1529 + RF_Amode = PHY_QueryRFReg(padapter, RF_PATH_A, RF_AC, bMask12Bits); 1530 1530 1531 1531 /* Path-B */ 1532 1532 if (is2T) 1533 - RF_Bmode = PHY_QueryRFReg(padapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); 1533 + RF_Bmode = PHY_QueryRFReg(padapter, RF_PATH_B, RF_AC, bMask12Bits); 1534 1534 1535 1535 /* 2. Set RF mode = standby mode */ 1536 1536 /* Path-A */ 1537 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); 1537 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); 1538 1538 1539 1539 /* Path-B */ 1540 1540 if (is2T) 1541 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); 1541 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); 1542 1542 } 1543 1543 1544 1544 /* 3. Read RF reg18 */ 1545 - LC_Cal = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); 1545 + LC_Cal = PHY_QueryRFReg(padapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); 1546 1546 1547 1547 /* 4. Set LC calibration begin bit15 */ 1548 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */ 1549 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); 1548 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */ 1549 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); 1550 1550 1551 1551 mdelay(100); 1552 1552 1553 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */ 1553 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */ 1554 1554 1555 1555 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */ 1556 1556 if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) { 1557 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); 1557 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); 1558 1558 } 1559 1559 1560 1560 /* Restore original situation */ 1561 1561 if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */ 1562 1562 /* Path-A */ 1563 1563 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg); 1564 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); 1564 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); 1565 1565 1566 1566 /* Path-B */ 1567 1567 if (is2T) 1568 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); 1568 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); 1569 1569 } else /* Deal with Packet TX case */ 1570 1570 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00); 1571 1571 } ··· 1625 1625 u8 path, bResult = SUCCESS; 1626 1626 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo; 1627 1627 1628 - path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? ODM_RF_PATH_A : ODM_RF_PATH_B; 1628 + path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? RF_PATH_A : RF_PATH_B; 1629 1629 1630 1630 /* Restore TX IQK */ 1631 1631 for (i = 0; i < 3; ++i) { ··· 1649 1649 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); 1650 1650 } 1651 1651 1652 - if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) { 1652 + if (pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] == 0) { 1653 1653 bResult = FAIL; 1654 1654 } else { 1655 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); 1656 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); 1655 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A]); 1656 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B]); 1657 1657 } 1658 1658 1659 1659 if (bResult == SUCCESS) ··· 1669 1669 GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord); 1670 1670 /* Save RF Path */ 1671 1671 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ 1672 - /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */ 1672 + /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */ 1673 1673 1674 1674 /* set GNT_BT = 0, pause BT traffic */ 1675 1675 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ ··· 1770 1770 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default); 1771 1771 /* Restore RF Path */ 1772 1772 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ 1773 - /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1773 + /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1774 1774 1775 1775 /* Resotr RX mode table parameter */ 1776 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1777 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 1778 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1779 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177); 1780 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 1781 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); 1776 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1777 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 1778 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1779 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177); 1780 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); 1781 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); 1782 1782 1783 1783 /* set GNT_BT = HW control */ 1784 1784 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
+11 -11
drivers/staging/rtl8723bs/hal/hal_com_phycfg.c
··· 16 16 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 17 17 u8 value = 0; 18 18 19 - if (RfPath > ODM_RF_PATH_D) 19 + if (RfPath >= RF_PATH_MAX) 20 20 return 0; 21 21 22 22 switch (RateSection) { ··· 47 47 { 48 48 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 49 49 50 - if (RfPath > ODM_RF_PATH_D) 50 + if (RfPath >= RF_PATH_MAX) 51 51 return; 52 52 53 53 switch (RateSection) { ··· 72 72 { 73 73 u8 path, base; 74 74 75 - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_B; ++path) { 75 + for (path = RF_PATH_A; path <= RF_PATH_B; ++path) { 76 76 base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_11M); 77 77 phy_SetTxPowerByRateBase(padapter, path, CCK, RF_1TX, base); 78 78 ··· 347 347 348 348 PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum); 349 349 350 - if (RfPath > ODM_RF_PATH_D) 350 + if (RfPath >= RF_PATH_MAX) 351 351 return; 352 352 353 353 if (TxNum > RF_MAX_TX_NUM) ··· 418 418 u8 mcs0_7Rates[8] = { 419 419 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7 420 420 }; 421 - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { 421 + for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) { 422 422 for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) { 423 423 /* CCK */ 424 424 base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_11M); ··· 619 619 padapter->registrypriv.RegEnableTxPowerByRate == 0) 620 620 return 0; 621 621 622 - if (RFPath > ODM_RF_PATH_D) 622 + if (RFPath >= RF_PATH_MAX) 623 623 return value; 624 624 625 625 if (TxNum >= RF_MAX_TX_NUM) ··· 643 643 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 644 644 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); 645 645 646 - if (RFPath > ODM_RF_PATH_D) 646 + if (RFPath >= RF_PATH_MAX) 647 647 return; 648 648 649 649 if (TxNum >= RF_MAX_TX_NUM) ··· 809 809 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { 810 810 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) { 811 811 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) { 812 - tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A]; 812 + tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A]; 813 813 814 - for (rfPath = ODM_RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) { 814 + for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) { 815 815 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) { 816 816 if (rateSection == 2) /* HT 1T */ 817 817 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, HT_MCS0_MCS7); ··· 904 904 if (channelIndex == -1) 905 905 return; 906 906 907 - prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]; 907 + prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; 908 908 909 909 if (powerLimit < prevPowerLimit) 910 - pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit; 910 + pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; 911 911 } 912 912 913 913 void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan)
+2 -2
drivers/staging/rtl8723bs/hal/odm.c
··· 718 718 pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex; 719 719 pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->DefaultCckIndex; 720 720 721 - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { 721 + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { 722 722 pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex; 723 723 pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex; 724 724 pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0; ··· 736 736 return; 737 737 738 738 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 739 - PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03); 739 + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03); 740 740 741 741 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 742 742 return;
-20
drivers/staging/rtl8723bs/hal/odm.h
··· 998 998 #endif 999 999 }; 1000 1000 1001 - #define ODM_RF_PATH_MAX 2 1002 - 1003 - enum odm_rf_radio_path_e { 1004 - ODM_RF_PATH_A = 0, /* Radio Path A */ 1005 - ODM_RF_PATH_B = 1, /* Radio Path B */ 1006 - ODM_RF_PATH_C = 2, /* Radio Path C */ 1007 - ODM_RF_PATH_D = 3, /* Radio Path D */ 1008 - ODM_RF_PATH_AB, 1009 - ODM_RF_PATH_AC, 1010 - ODM_RF_PATH_AD, 1011 - ODM_RF_PATH_BC, 1012 - ODM_RF_PATH_BD, 1013 - ODM_RF_PATH_CD, 1014 - ODM_RF_PATH_ABC, 1015 - ODM_RF_PATH_ACD, 1016 - ODM_RF_PATH_BCD, 1017 - ODM_RF_PATH_ABCD, 1018 - /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1019 - }; 1020 - 1021 1001 enum odm_rf_content { 1022 1002 odm_radioa_txt = 0x1000, 1023 1003 odm_radiob_txt = 0x1001,
+1 -1
drivers/staging/rtl8723bs/hal/odm_CfoTracking.c
··· 203 203 * 3 Update CFO report for path-A & path-B 204 204 * Only paht-A and path-B have CFO tail and short CFO 205 205 */ 206 - for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) 206 + for (i = RF_PATH_A; i <= RF_PATH_B; i++) 207 207 cfo_track->CFO_tail[i] = (int)cfotail[i]; 208 208 209 209 /* 3 Update packet counter */
+18 -18
drivers/staging/rtl8723bs/hal/odm_HWConfig.c
··· 113 113 struct phy_status_rpt_8192cd_t *phy_sta_rpt = (struct phy_status_rpt_8192cd_t *)phy_status; 114 114 115 115 is_cck_rate = pkt_info->data_rate <= DESC_RATE11M; 116 - phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; 117 - phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; 116 + phy_info->rx_mimo_signal_quality[RF_PATH_A] = -1; 117 + phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1; 118 118 119 119 120 120 if (is_cck_rate) { ··· 166 166 } 167 167 168 168 phy_info->signal_quality = sq; 169 - phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = sq; 170 - phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; 169 + phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq; 170 + phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1; 171 171 } 172 172 } else { /* is OFDM rate */ 173 173 dm_odm->PhyDbgInfo.NumQryPhyStatusOFDM++; ··· 176 176 * (1)Get RSSI for HT rate 177 177 */ 178 178 179 - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { 179 + for (i = RF_PATH_A; i < RF_PATH_MAX; i++) { 180 180 /* 2008/01/30 MH we will judge RF RX path now. */ 181 181 if (dm_odm->RFPathRxEnable & BIT(i)) 182 182 rf_rx_num++; ··· 227 227 /* Fill value in RFD, Get the first spatial stream only */ 228 228 phy_info->signal_quality = (u8)(evm & 0xff); 229 229 230 - phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = (u8)(evm & 0xff); 230 + phy_info->rx_mimo_signal_quality[RF_PATH_A] = (u8)(evm & 0xff); 231 231 232 232 odm_parsing_cfo(dm_odm, pkt_info, phy_sta_rpt->path_cfotail); 233 233 } ··· 290 290 if (pPktinfo->to_self || pPktinfo->is_beacon) { 291 291 292 292 if (!isCCKrate) { /* ofdm rate */ 293 - if (pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) { 294 - RSSI_Ave = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_A]; 295 - pDM_Odm->RSSI_A = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_A]; 293 + if (pPhyInfo->rx_mimo_signal_strength[RF_PATH_B] == 0) { 294 + RSSI_Ave = pPhyInfo->rx_mimo_signal_strength[RF_PATH_A]; 295 + pDM_Odm->RSSI_A = pPhyInfo->rx_mimo_signal_strength[RF_PATH_A]; 296 296 pDM_Odm->RSSI_B = 0; 297 297 } else { 298 - pDM_Odm->RSSI_A = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_A]; 299 - pDM_Odm->RSSI_B = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_B]; 298 + pDM_Odm->RSSI_A = pPhyInfo->rx_mimo_signal_strength[RF_PATH_A]; 299 + pDM_Odm->RSSI_B = pPhyInfo->rx_mimo_signal_strength[RF_PATH_B]; 300 300 301 301 if ( 302 - pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_A] > 303 - pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_B] 302 + pPhyInfo->rx_mimo_signal_strength[RF_PATH_A] > 303 + pPhyInfo->rx_mimo_signal_strength[RF_PATH_B] 304 304 ) { 305 - RSSI_max = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_A]; 306 - RSSI_min = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_B]; 305 + RSSI_max = pPhyInfo->rx_mimo_signal_strength[RF_PATH_A]; 306 + RSSI_min = pPhyInfo->rx_mimo_signal_strength[RF_PATH_B]; 307 307 } else { 308 - RSSI_max = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_B]; 309 - RSSI_min = pPhyInfo->rx_mimo_signal_strength[ODM_RF_PATH_A]; 308 + RSSI_max = pPhyInfo->rx_mimo_signal_strength[RF_PATH_B]; 309 + RSSI_min = pPhyInfo->rx_mimo_signal_strength[RF_PATH_A]; 310 310 } 311 311 312 312 if ((RSSI_max-RSSI_min) < 3) ··· 411 411 enum hal_status ODM_ConfigRFWithHeaderFile( 412 412 struct dm_odm_t *pDM_Odm, 413 413 enum ODM_RF_Config_Type ConfigType, 414 - enum odm_rf_radio_path_e eRFPath 414 + enum rf_path eRFPath 415 415 ) 416 416 { 417 417 if (ConfigType == CONFIG_RF_RADIO)
+1 -1
drivers/staging/rtl8723bs/hal/odm_HWConfig.h
··· 84 84 enum hal_status ODM_ConfigRFWithHeaderFile( 85 85 struct dm_odm_t *pDM_Odm, 86 86 enum ODM_RF_Config_Type ConfigType, 87 - enum odm_rf_radio_path_e eRFPath 87 + enum rf_path eRFPath 88 88 ); 89 89 90 90 enum hal_status ODM_ConfigBBWithHeaderFile(
+9 -9
drivers/staging/rtl8723bs/hal/odm_NoiseMonitor.c
··· 70 70 /* update idle time pwer report per 5us */ 71 71 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0); 72 72 73 - noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b&0xff); 74 - noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b&0xff00)>>8); 73 + noise_data.value[RF_PATH_A] = (u8)(tmp4b&0xff); 74 + noise_data.value[RF_PATH_B] = (u8)((tmp4b&0xff00)>>8); 75 75 76 - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { 76 + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { 77 77 noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; 78 78 noise_data.sval[rf_path] /= 2; 79 79 } 80 80 /* mdelay(10); */ 81 81 /* msleep(10); */ 82 82 83 - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { 83 + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { 84 84 if ((noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) { 85 85 noise_data.valid_cnt[rf_path]++; 86 86 noise_data.sum[rf_path] += noise_data.sval[rf_path]; ··· 94 94 95 95 /* printk("####### valid_done:%d #############\n", valid_done); */ 96 96 if ((valid_done == max_rf_path) || (jiffies_to_msecs(jiffies - start) > max_time)) { 97 - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { 97 + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { 98 98 /* printk("%s PATH_%d - sum = %d, valid_cnt = %d\n", __func__, rf_path, noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */ 99 99 if (noise_data.valid_cnt[rf_path]) 100 100 noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; ··· 106 106 } 107 107 reg_c50 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0); 108 108 reg_c50 &= ~BIT7; 109 - pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]; 110 - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; 109 + pDM_Odm->noise_level.noise[RF_PATH_A] = -110 + reg_c50 + noise_data.sum[RF_PATH_A]; 110 + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[RF_PATH_A]; 111 111 112 112 if (max_rf_path == 2) { 113 113 reg_c58 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0); 114 114 reg_c58 &= ~BIT7; 115 - pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]; 116 - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; 115 + pDM_Odm->noise_level.noise[RF_PATH_B] = -110 + reg_c58 + noise_data.sum[RF_PATH_B]; 116 + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[RF_PATH_B]; 117 117 } 118 118 pDM_Odm->noise_level.noise_all /= max_rf_path; 119 119
+2 -2
drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c
··· 11 11 struct dm_odm_t *pDM_Odm, 12 12 u32 Addr, 13 13 u32 Data, 14 - enum odm_rf_radio_path_e RF_PATH, 14 + enum rf_path RF_PATH, 15 15 u32 RegAddr 16 16 ) 17 17 { ··· 93 93 pDM_Odm, 94 94 Addr, 95 95 Data, 96 - ODM_RF_PATH_A, 96 + RF_PATH_A, 97 97 Addr|maskforPhySet 98 98 ); 99 99 }
+1 -1
drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.h
··· 10 10 void odm_ConfigRFReg_8723B(struct dm_odm_t *pDM_Odm, 11 11 u32 Addr, 12 12 u32 Data, 13 - enum odm_rf_radio_path_e RF_PATH, 13 + enum rf_path RF_PATH, 14 14 u32 RegAddr 15 15 ); 16 16
+6 -6
drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c
··· 2280 2280 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B]; 2281 2281 if (tempval != 0xFF) { 2282 2282 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0); 2283 - /* EFUSE_0xC3[6] == 0, S1(Main)-ODM_RF_PATH_A; */ 2284 - /* EFUSE_0xC3[6] == 1, S0(Aux)-ODM_RF_PATH_B */ 2285 - pHalData->ant_path = (tempval & BIT(6))?ODM_RF_PATH_B:ODM_RF_PATH_A; 2283 + /* EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A; */ 2284 + /* EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B */ 2285 + pHalData->ant_path = (tempval & BIT(6))? RF_PATH_B : RF_PATH_A; 2286 2286 } else { 2287 2287 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2288 2288 if (pHalData->PackageType == PACKAGE_QFN68) 2289 - pHalData->ant_path = ODM_RF_PATH_B; 2289 + pHalData->ant_path = RF_PATH_B; 2290 2290 else 2291 - pHalData->ant_path = ODM_RF_PATH_A; 2291 + pHalData->ant_path = RF_PATH_A; 2292 2292 } 2293 2293 } else { 2294 2294 pHalData->EEPROMBluetoothCoexist = false; 2295 2295 pHalData->EEPROMBluetoothType = BT_RTL8723B; 2296 2296 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2297 - pHalData->ant_path = ODM_RF_PATH_A; 2297 + pHalData->ant_path = RF_PATH_A; 2298 2298 } 2299 2299 2300 2300 if (padapter->registrypriv.ant_num > 0) {
+21 -21
drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
··· 308 308 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 309 309 310 310 /* RF Interface Sowrtware Control */ 311 - pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ 312 - pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 311 + pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ 312 + pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 313 313 314 314 /* RF Interface Output (and Enable) */ 315 - pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ 316 - pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ 315 + pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ 316 + pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ 317 317 318 318 /* RF Interface (Output and) Enable */ 319 - pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 320 - pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 319 + pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 320 + pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 321 321 322 - pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ 323 - pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 322 + pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ 323 + pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 324 324 325 - pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ 326 - pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */ 325 + pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ 326 + pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */ 327 327 328 328 /* Tranceiver Readback LSSI/HSPI mode */ 329 - pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 330 - pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 331 - pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; 332 - pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; 329 + pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 330 + pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 331 + pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; 332 + pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; 333 333 334 334 } 335 335 ··· 399 399 400 400 msleep(1); 401 401 402 - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780); 402 + PHY_SetRFReg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780); 403 403 404 404 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB); 405 405 ··· 453 453 u8 Rate 454 454 ) 455 455 { 456 - if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) { 456 + if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) { 457 457 switch (Rate) { 458 458 case MGN_1M: 459 459 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex); ··· 538 538 s8 txPower = 0, powerDiffByRate = 0, limit = 0; 539 539 540 540 txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel); 541 - powerDiffByRate = PHY_GetTxPowerByRate(padapter, ODM_RF_PATH_A, RF_1TX, Rate); 541 + powerDiffByRate = PHY_GetTxPowerByRate(padapter, RF_PATH_A, RF_1TX, Rate); 542 542 543 543 limit = phy_get_tx_pwr_lmt( 544 544 padapter, ··· 565 565 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 566 566 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 567 567 struct fat_t *pDM_FatTable = &pDM_Odm->DM_FatTable; 568 - u8 RFPath = ODM_RF_PATH_A; 568 + u8 RFPath = RF_PATH_A; 569 569 570 570 if (pHalData->AntDivCfg) {/* antenna diversity Enable */ 571 - RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B); 571 + RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? RF_PATH_A : RF_PATH_B); 572 572 } else { /* antenna diversity disable */ 573 573 RFPath = pHalData->ant_path; 574 574 } ··· 672 672 if (pHalData->rf_chip == RF_PSEUDO_11N) 673 673 return; 674 674 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW); 675 - PHY_SetRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); 676 - PHY_SetRFReg(padapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); 675 + PHY_SetRFReg(padapter, RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); 676 + PHY_SetRFReg(padapter, RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); 677 677 } 678 678 679 679 static void phy_SwChnlAndSetBwMode8723B(struct adapter *Adapter)
+4 -12
drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c
··· 63 63 switch (Bandwidth) { 64 64 case CHANNEL_WIDTH_20: 65 65 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); 66 - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 67 - PHY_SetRFReg(Adapter, ODM_RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 66 + PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 67 + PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 68 68 break; 69 69 70 70 case CHANNEL_WIDTH_40: 71 71 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10); 72 - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 73 - PHY_SetRFReg(Adapter, ODM_RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 72 + PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 73 + PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 74 74 break; 75 75 76 76 default: ··· 97 97 /*----Store original RFENV control type----*/ 98 98 switch (eRFPath) { 99 99 case RF_PATH_A: 100 - case RF_PATH_C: 101 100 u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); 102 101 break; 103 102 case RF_PATH_B: 104 - case RF_PATH_D: 105 103 u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16); 106 104 break; 107 105 } ··· 126 128 ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, 127 129 CONFIG_RF_RADIO, eRFPath); 128 130 break; 129 - case RF_PATH_C: 130 - case RF_PATH_D: 131 - break; 132 131 } 133 132 134 133 /*----Restore RFENV control type----*/ 135 134 switch (eRFPath) { 136 135 case RF_PATH_A: 137 - case RF_PATH_C: 138 136 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); 139 137 break; 140 138 case RF_PATH_B: 141 - case RF_PATH_D: 142 139 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue); 143 140 break; 144 141 } ··· 156 163 /* */ 157 164 /* Initialize general global value */ 158 165 /* */ 159 - /* TODO: Extend RF_PATH_C and RF_PATH_D in the future */ 160 166 if (pHalData->rf_type == RF_1T1R) 161 167 pHalData->NumTotalRFPath = 1; 162 168 else
+1 -2
drivers/staging/rtl8723bs/include/hal_phy.h
··· 30 30 enum rf_path { 31 31 RF_PATH_A = 0, 32 32 RF_PATH_B, 33 - RF_PATH_C, 34 - RF_PATH_D 33 + RF_PATH_MAX 35 34 }; 36 35 37 36 #define TX_1S 0