Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

media: iris: Allocate and queue internal buffers for encoder video device

Add support for allocating and queuing internal buffers required by the
encoder. The sizes of these buffers are derived from hardware
specifications and are essential to meet the encoder's functional and
performance requirements.

These buffers are not exposed to userspace; they are allocated and
managed internally to ensure correct and efficient hardware operation.

Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # X1E80100
Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # x1e80100-crd
[bod: added sm8750 enc_op_int_buf_tbl enumeration during merge]
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

authored by

Dikshita Agarwal and committed by
Hans Verkuil
61528e86 d22037f3

+1081 -58
+83 -31
drivers/media/platform/qcom/iris/iris_buffer.c
··· 294 294 const u32 *internal_buf_type; 295 295 u32 internal_buffer_count, i; 296 296 297 - if (V4L2_TYPE_IS_OUTPUT(plane)) { 298 - internal_buf_type = platform_data->dec_ip_int_buf_tbl; 299 - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 300 - for (i = 0; i < internal_buffer_count; i++) 301 - iris_fill_internal_buf_info(inst, internal_buf_type[i]); 297 + if (inst->domain == DECODER) { 298 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 299 + internal_buf_type = platform_data->dec_ip_int_buf_tbl; 300 + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 301 + for (i = 0; i < internal_buffer_count; i++) 302 + iris_fill_internal_buf_info(inst, internal_buf_type[i]); 303 + } else { 304 + internal_buf_type = platform_data->dec_op_int_buf_tbl; 305 + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; 306 + for (i = 0; i < internal_buffer_count; i++) 307 + iris_fill_internal_buf_info(inst, internal_buf_type[i]); 308 + } 302 309 } else { 303 - internal_buf_type = platform_data->dec_op_int_buf_tbl; 304 - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; 305 - for (i = 0; i < internal_buffer_count; i++) 306 - iris_fill_internal_buf_info(inst, internal_buf_type[i]); 310 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 311 + internal_buf_type = platform_data->enc_ip_int_buf_tbl; 312 + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; 313 + for (i = 0; i < internal_buffer_count; i++) 314 + iris_fill_internal_buf_info(inst, internal_buf_type[i]); 315 + } else { 316 + internal_buf_type = platform_data->enc_op_int_buf_tbl; 317 + internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; 318 + for (i = 0; i < internal_buffer_count; i++) 319 + iris_fill_internal_buf_info(inst, internal_buf_type[i]); 320 + } 307 321 } 308 322 } 309 323 ··· 358 344 const u32 *internal_buf_type; 359 345 int ret; 360 346 361 - if (V4L2_TYPE_IS_OUTPUT(plane)) { 362 - internal_buf_type = platform_data->dec_ip_int_buf_tbl; 363 - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 347 + if (inst->domain == DECODER) { 348 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 349 + internal_buf_type = platform_data->dec_ip_int_buf_tbl; 350 + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 351 + } else { 352 + internal_buf_type = platform_data->dec_op_int_buf_tbl; 353 + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; 354 + } 364 355 } else { 365 - internal_buf_type = platform_data->dec_op_int_buf_tbl; 366 - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; 356 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 357 + internal_buf_type = platform_data->enc_ip_int_buf_tbl; 358 + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; 359 + } else { 360 + internal_buf_type = platform_data->enc_op_int_buf_tbl; 361 + internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; 362 + } 367 363 } 368 364 369 365 for (i = 0; i < internal_buffer_count; i++) { ··· 435 411 u32 internal_buffer_count, i; 436 412 int ret; 437 413 438 - if (V4L2_TYPE_IS_OUTPUT(plane)) { 439 - internal_buf_type = platform_data->dec_ip_int_buf_tbl; 440 - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 414 + if (inst->domain == DECODER) { 415 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 416 + internal_buf_type = platform_data->dec_ip_int_buf_tbl; 417 + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 418 + } else { 419 + internal_buf_type = platform_data->dec_op_int_buf_tbl; 420 + internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; 421 + } 441 422 } else { 442 - internal_buf_type = platform_data->dec_op_int_buf_tbl; 443 - internal_buffer_count = platform_data->dec_op_int_buf_tbl_size; 423 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 424 + internal_buf_type = platform_data->enc_ip_int_buf_tbl; 425 + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; 426 + } else { 427 + internal_buf_type = platform_data->enc_op_int_buf_tbl; 428 + internal_buffer_count = platform_data->enc_op_int_buf_tbl_size; 429 + } 444 430 } 445 431 446 432 for (i = 0; i < internal_buffer_count; i++) { ··· 494 460 u32 i, len; 495 461 int ret; 496 462 497 - if (V4L2_TYPE_IS_OUTPUT(plane)) { 498 - internal_buf_type = platform_data->dec_ip_int_buf_tbl; 499 - len = platform_data->dec_ip_int_buf_tbl_size; 463 + if (inst->domain == DECODER) { 464 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 465 + internal_buf_type = platform_data->dec_ip_int_buf_tbl; 466 + len = platform_data->dec_ip_int_buf_tbl_size; 467 + } else { 468 + internal_buf_type = platform_data->dec_op_int_buf_tbl; 469 + len = platform_data->dec_op_int_buf_tbl_size; 470 + } 500 471 } else { 501 - internal_buf_type = platform_data->dec_op_int_buf_tbl; 502 - len = platform_data->dec_op_int_buf_tbl_size; 472 + if (V4L2_TYPE_IS_OUTPUT(plane)) { 473 + internal_buf_type = platform_data->enc_ip_int_buf_tbl; 474 + len = platform_data->enc_ip_int_buf_tbl_size; 475 + } else { 476 + internal_buf_type = platform_data->enc_op_int_buf_tbl; 477 + len = platform_data->enc_op_int_buf_tbl_size; 478 + } 503 479 } 504 480 505 481 for (i = 0; i < len; i++) { ··· 530 486 } 531 487 532 488 if (force) { 533 - buffers = &inst->buffers[BUF_PERSIST]; 489 + if (inst->domain == DECODER) 490 + buffers = &inst->buffers[BUF_PERSIST]; 491 + else 492 + buffers = &inst->buffers[BUF_ARP]; 534 493 535 494 list_for_each_entry_safe(buf, next, &buffers->list, list) { 536 495 ret = iris_destroy_internal_buffer(inst, buf); ··· 584 537 u32 internal_buffer_count, i; 585 538 int ret; 586 539 587 - internal_buf_type = platform_data->dec_ip_int_buf_tbl; 588 - internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 540 + if (inst->domain == DECODER) { 541 + internal_buf_type = platform_data->dec_ip_int_buf_tbl; 542 + internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size; 543 + } else { 544 + internal_buf_type = platform_data->enc_ip_int_buf_tbl; 545 + internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size; 546 + } 589 547 590 548 for (i = 0; i < internal_buffer_count; i++) { 591 549 ret = iris_release_internal_buffers(inst, internal_buf_type[i]); ··· 601 549 return 0; 602 550 } 603 551 604 - int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst) 552 + int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst, enum iris_buffer_type buffer_type) 605 553 { 606 - struct iris_buffers *buffers = &inst->buffers[BUF_PERSIST]; 554 + struct iris_buffers *buffers = &inst->buffers[buffer_type]; 607 555 struct iris_buffer *buffer, *next; 608 556 int ret; 609 557 u32 i; ··· 611 559 if (!list_empty(&buffers->list)) 612 560 return 0; 613 561 614 - iris_fill_internal_buf_info(inst, BUF_PERSIST); 562 + iris_fill_internal_buf_info(inst, buffer_type); 615 563 616 564 for (i = 0; i < buffers->min_count; i++) { 617 - ret = iris_create_internal_buffer(inst, BUF_PERSIST, i); 565 + ret = iris_create_internal_buffer(inst, buffer_type, i); 618 566 if (ret) 619 567 return ret; 620 568 }
+5 -1
drivers/media/platform/qcom/iris/iris_buffer.h
··· 25 25 * @BUF_DPB: buffer to store display picture buffers for reference 26 26 * @BUF_PERSIST: buffer to store session context data 27 27 * @BUF_SCRATCH_1: buffer to store decoding/encoding context data for HW 28 + * @BUF_SCRATCH_2: buffer to store encoding context data for HW 29 + * @BUF_VPSS: buffer to store VPSS context data for HW 28 30 * @BUF_TYPE_MAX: max buffer types 29 31 */ 30 32 enum iris_buffer_type { ··· 40 38 BUF_DPB, 41 39 BUF_PERSIST, 42 40 BUF_SCRATCH_1, 41 + BUF_SCRATCH_2, 42 + BUF_VPSS, 43 43 BUF_TYPE_MAX, 44 44 }; 45 45 ··· 113 109 int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer); 114 110 int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane); 115 111 int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane); 116 - int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst); 112 + int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst, enum iris_buffer_type buf_type); 117 113 int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst); 118 114 int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf); 119 115 int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buf_type);
+6
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
··· 21 21 return HFI_BUFFER_INTERNAL_SCRATCH; 22 22 case BUF_SCRATCH_1: 23 23 return HFI_BUFFER_INTERNAL_SCRATCH_1; 24 + case BUF_SCRATCH_2: 25 + return HFI_BUFFER_INTERNAL_SCRATCH_2; 26 + case BUF_ARP: 27 + return HFI_BUFFER_INTERNAL_PERSIST; 24 28 default: 25 29 return -EINVAL; 26 30 } ··· 362 358 case BUF_PERSIST: 363 359 case BUF_BIN: 364 360 case BUF_SCRATCH_1: 361 + case BUF_SCRATCH_2: 362 + case BUF_ARP: 365 363 return iris_hfi_gen1_queue_internal_buffer(inst, buf); 366 364 default: 367 365 return -EINVAL;
+2
drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h
··· 74 74 #define HFI_BUFFER_INPUT 0x1 75 75 #define HFI_BUFFER_OUTPUT 0x2 76 76 #define HFI_BUFFER_OUTPUT2 0x3 77 + #define HFI_BUFFER_INTERNAL_PERSIST 0x4 77 78 #define HFI_BUFFER_INTERNAL_PERSIST_1 0x5 78 79 #define HFI_BUFFER_INTERNAL_SCRATCH 0x6 79 80 #define HFI_BUFFER_INTERNAL_SCRATCH_1 0x7 81 + #define HFI_BUFFER_INTERNAL_SCRATCH_2 0x8 80 82 81 83 #define HFI_PROPERTY_SYS_CODEC_POWER_PLANE_CTRL 0x5 82 84 #define HFI_PROPERTY_SYS_IMAGE_VERSION 0x6
+40 -16
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
··· 111 111 } 112 112 } 113 113 114 - static u32 iris_hfi_gen2_get_port_from_buf_type(enum iris_buffer_type buffer_type) 114 + static u32 iris_hfi_gen2_get_port_from_buf_type(struct iris_inst *inst, 115 + enum iris_buffer_type buffer_type) 115 116 { 116 - switch (buffer_type) { 117 - case BUF_INPUT: 118 - case BUF_BIN: 119 - case BUF_COMV: 120 - case BUF_NON_COMV: 121 - case BUF_LINE: 122 - return HFI_PORT_BITSTREAM; 123 - case BUF_OUTPUT: 124 - case BUF_DPB: 125 - return HFI_PORT_RAW; 126 - case BUF_PERSIST: 127 - default: 128 - return HFI_PORT_NONE; 117 + if (inst->domain == DECODER) { 118 + switch (buffer_type) { 119 + case BUF_INPUT: 120 + case BUF_BIN: 121 + case BUF_COMV: 122 + case BUF_NON_COMV: 123 + case BUF_LINE: 124 + return HFI_PORT_BITSTREAM; 125 + case BUF_OUTPUT: 126 + case BUF_DPB: 127 + return HFI_PORT_RAW; 128 + case BUF_PERSIST: 129 + default: 130 + return HFI_PORT_NONE; 131 + } 132 + } else { 133 + switch (buffer_type) { 134 + case BUF_INPUT: 135 + case BUF_VPSS: 136 + return HFI_PORT_RAW; 137 + case BUF_OUTPUT: 138 + case BUF_BIN: 139 + case BUF_COMV: 140 + case BUF_NON_COMV: 141 + case BUF_LINE: 142 + case BUF_SCRATCH_2: 143 + return HFI_PORT_BITSTREAM; 144 + case BUF_ARP: 145 + default: 146 + return HFI_PORT_NONE; 147 + } 129 148 } 130 149 } 131 150 ··· 1061 1042 case BUF_LINE: 1062 1043 return HFI_BUFFER_LINE; 1063 1044 case BUF_DPB: 1045 + case BUF_SCRATCH_2: 1064 1046 return HFI_BUFFER_DPB; 1065 1047 case BUF_PERSIST: 1066 1048 return HFI_BUFFER_PERSIST; 1049 + case BUF_ARP: 1050 + return HFI_BUFFER_ARP; 1051 + case BUF_VPSS: 1052 + return HFI_BUFFER_VPSS; 1067 1053 default: 1068 1054 return 0; 1069 1055 } ··· 1124 1100 return ret; 1125 1101 } 1126 1102 1127 - port = iris_hfi_gen2_get_port_from_buf_type(buffer->type); 1103 + port = iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type); 1128 1104 iris_hfi_gen2_packet_session_command(inst, 1129 1105 HFI_CMD_BUFFER, 1130 1106 HFI_HOST_FLAGS_INTR_REQUIRED, ··· 1146 1122 1147 1123 iris_hfi_gen2_get_buffer(buffer, &hfi_buffer); 1148 1124 hfi_buffer.flags |= HFI_BUF_HOST_FLAG_RELEASE; 1149 - port = iris_hfi_gen2_get_port_from_buf_type(buffer->type); 1125 + port = iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type); 1150 1126 1151 1127 iris_hfi_gen2_packet_session_command(inst, 1152 1128 HFI_CMD_BUFFER,
+7 -3
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
··· 29 29 int (*handle)(struct iris_inst *inst, struct iris_hfi_packet *pkt); 30 30 }; 31 31 32 - static u32 iris_hfi_gen2_buf_type_to_driver(enum hfi_buffer_type buf_type) 32 + static u32 iris_hfi_gen2_buf_type_to_driver(struct iris_inst *inst, 33 + enum hfi_buffer_type buf_type) 33 34 { 34 35 switch (buf_type) { 35 36 case HFI_BUFFER_BITSTREAM: ··· 48 47 case HFI_BUFFER_LINE: 49 48 return BUF_LINE; 50 49 case HFI_BUFFER_DPB: 51 - return BUF_DPB; 50 + if (inst->domain == DECODER) 51 + return BUF_DPB; 52 + else 53 + return BUF_SCRATCH_2; 52 54 case HFI_BUFFER_PERSIST: 53 55 return BUF_PERSIST; 54 56 default: ··· 425 421 static int iris_hfi_gen2_handle_release_internal_buffer(struct iris_inst *inst, 426 422 struct iris_hfi_buffer *buffer) 427 423 { 428 - u32 buf_type = iris_hfi_gen2_buf_type_to_driver(buffer->type); 424 + u32 buf_type = iris_hfi_gen2_buf_type_to_driver(inst, buffer->type); 429 425 struct iris_buffers *buffers = &inst->buffers[buf_type]; 430 426 struct iris_buffer *buf, *iter; 431 427 bool found = false;
+4
drivers/media/platform/qcom/iris/iris_platform_common.h
··· 251 251 unsigned int dec_ip_int_buf_tbl_size; 252 252 const u32 *dec_op_int_buf_tbl; 253 253 unsigned int dec_op_int_buf_tbl_size; 254 + const u32 *enc_ip_int_buf_tbl; 255 + unsigned int enc_ip_int_buf_tbl_size; 256 + const u32 *enc_op_int_buf_tbl; 257 + unsigned int enc_op_int_buf_tbl_size; 254 258 }; 255 259 256 260 #endif
+20
drivers/media/platform/qcom/iris/iris_platform_gen2.c
··· 728 728 BUF_DPB, 729 729 }; 730 730 731 + static const u32 sm8550_enc_op_int_buf_tbl[] = { 732 + BUF_BIN, 733 + BUF_COMV, 734 + BUF_NON_COMV, 735 + BUF_LINE, 736 + BUF_SCRATCH_2, 737 + }; 738 + 731 739 struct iris_platform_data sm8550_data = { 732 740 .get_instance = iris_hfi_gen2_get_instance, 733 741 .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, ··· 813 805 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), 814 806 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, 815 807 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), 808 + 809 + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, 810 + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), 816 811 }; 817 812 818 813 /* ··· 904 893 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), 905 894 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, 906 895 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), 896 + 897 + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, 898 + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), 907 899 }; 908 900 909 901 struct iris_platform_data sm8750_data = { ··· 985 971 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), 986 972 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, 987 973 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), 974 + 975 + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, 976 + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), 988 977 }; 989 978 990 979 /* ··· 1072 1055 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), 1073 1056 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, 1074 1057 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), 1058 + 1059 + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, 1060 + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), 1075 1061 };
+9
drivers/media/platform/qcom/iris/iris_platform_sm8250.c
··· 307 307 BUF_DPB, 308 308 }; 309 309 310 + static const u32 sm8250_enc_ip_int_buf_tbl[] = { 311 + BUF_BIN, 312 + BUF_SCRATCH_1, 313 + BUF_SCRATCH_2, 314 + }; 315 + 310 316 struct iris_platform_data sm8250_data = { 311 317 .get_instance = iris_hfi_gen1_get_instance, 312 318 .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, ··· 358 352 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), 359 353 .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, 360 354 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), 355 + 356 + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, 357 + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), 361 358 };
+1 -1
drivers/media/platform/qcom/iris/iris_vdec.c
··· 321 321 if (ret) 322 322 return ret; 323 323 324 - ret = iris_alloc_and_queue_persist_bufs(inst); 324 + ret = iris_alloc_and_queue_persist_bufs(inst, BUF_PERSIST); 325 325 if (ret) 326 326 return ret; 327 327
+36
drivers/media/platform/qcom/iris/iris_venc.c
··· 435 435 if (ret) 436 436 return ret; 437 437 438 + ret = iris_alloc_and_queue_persist_bufs(inst, BUF_ARP); 439 + if (ret) 440 + return ret; 441 + 442 + iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 443 + 444 + ret = iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 445 + if (ret) 446 + return ret; 447 + 448 + ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 449 + if (ret) 450 + return ret; 451 + 452 + ret = iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 453 + if (ret) 454 + return ret; 455 + 438 456 return iris_process_streamon_input(inst); 439 457 } 440 458 ··· 461 443 int ret; 462 444 463 445 ret = iris_set_properties(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 446 + if (ret) 447 + goto error; 448 + 449 + ret = iris_alloc_and_queue_persist_bufs(inst, BUF_ARP); 450 + if (ret) 451 + return ret; 452 + 453 + iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 454 + 455 + ret = iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 456 + if (ret) 457 + goto error; 458 + 459 + ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 460 + if (ret) 461 + goto error; 462 + 463 + ret = iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 464 464 if (ret) 465 465 goto error; 466 466
+8 -2
drivers/media/platform/qcom/iris/iris_vidc.c
··· 176 176 INIT_LIST_HEAD(&inst->buffers[BUF_DPB].list); 177 177 INIT_LIST_HEAD(&inst->buffers[BUF_PERSIST].list); 178 178 INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_1].list); 179 + INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_2].list); 180 + INIT_LIST_HEAD(&inst->buffers[BUF_VPSS].list); 179 181 init_completion(&inst->completion); 180 182 init_completion(&inst->flush_completion); 181 183 ··· 267 265 count, internal_buf_type[i]); 268 266 } 269 267 270 - buffers = &inst->buffers[BUF_PERSIST]; 268 + if (inst->domain == DECODER) 269 + buffers = &inst->buffers[BUF_PERSIST]; 270 + else 271 + buffers = &inst->buffers[BUF_ARP]; 271 272 272 273 count = 0; 273 274 list_for_each_entry_safe(buf, next, &buffers->list, list) 274 275 count++; 275 276 if (count) 276 - dev_err(inst->core->dev, "%d buffer of type BUF_PERSIST not released", count); 277 + dev_err(inst->core->dev, "%d buffer of type %d not released", 278 + count, inst->domain == DECODER ? BUF_PERSIST : BUF_ARP); 277 279 } 278 280 279 281 int iris_close(struct file *filp)
+839 -4
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
··· 5 5 6 6 #include "iris_instance.h" 7 7 #include "iris_vpu_buffer.h" 8 + #include "iris_hfi_gen1_defines.h" 9 + #include "iris_hfi_gen2_defines.h" 10 + 11 + #define HFI_MAX_COL_FRAME 6 12 + 13 + #ifndef SYSTEM_LAL_TILE10 14 + #define SYSTEM_LAL_TILE10 192 15 + #endif 8 16 9 17 static u32 size_h264d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 10 18 { ··· 556 548 iris_vpu_dec_line_size(inst); 557 549 } 558 550 551 + static inline 552 + u32 size_enc_single_pipe(u32 rc_type, u32 bitbin_size, u32 num_vpp_pipes, 553 + u32 frame_width, u32 frame_height, u32 lcu_size) 554 + { 555 + u32 size_aligned_height = ALIGN((frame_height), lcu_size); 556 + u32 size_aligned_width = ALIGN((frame_width), lcu_size); 557 + u32 size_single_pipe_eval = 0, sao_bin_buffer_size = 0; 558 + u32 padded_bin_sz; 559 + 560 + if ((size_aligned_width * size_aligned_height) > (3840 * 2160)) 561 + size_single_pipe_eval = (bitbin_size / num_vpp_pipes); 562 + else if (num_vpp_pipes > 2) 563 + size_single_pipe_eval = bitbin_size / 2; 564 + else 565 + size_single_pipe_eval = bitbin_size; 566 + 567 + sao_bin_buffer_size = (64 * ((((frame_width) + 32) * ((frame_height) + 32)) >> 10)) + 384; 568 + padded_bin_sz = ALIGN(size_single_pipe_eval, 256); 569 + size_single_pipe_eval = sao_bin_buffer_size + padded_bin_sz; 570 + 571 + return ALIGN(size_single_pipe_eval, 256); 572 + } 573 + 574 + static inline u32 size_bin_bitstream_enc(u32 width, u32 height, 575 + u32 rc_type) 576 + { 577 + u32 aligned_height = ALIGN(height, 32); 578 + u32 aligned_width = ALIGN(width, 32); 579 + u32 frame_size = width * height * 3; 580 + u32 mbs_per_frame; 581 + 582 + /* 583 + * Encoder output size calculation: 32 Align width/height 584 + * For resolution < 720p : YUVsize * 4 585 + * For resolution > 720p & <= 4K : YUVsize / 2 586 + * For resolution > 4k : YUVsize / 4 587 + * Initially frame_size = YUVsize * 2; 588 + */ 589 + 590 + mbs_per_frame = (ALIGN(aligned_height, 16) * ALIGN(aligned_width, 16)) / 256; 591 + 592 + if (mbs_per_frame < NUM_MBS_720P) 593 + frame_size = frame_size << 1; 594 + else if (mbs_per_frame <= NUM_MBS_4K) 595 + frame_size = frame_size >> 2; 596 + else 597 + frame_size = frame_size >> 3; 598 + 599 + if (rc_type == HFI_RATE_CONTROL_OFF || rc_type == HFI_RATE_CONTROL_CQ || 600 + rc_type == HFI_RC_OFF || rc_type == HFI_RC_CQ) 601 + frame_size = frame_size << 1; 602 + 603 + /* 604 + * In case of opaque color format bitdepth will be known 605 + * with first ETB, buffers allocated already with 8 bit 606 + * won't be sufficient for 10 bit 607 + * calculate size considering 10-bit by default 608 + * For 10-bit cases size = size * 1.25 609 + */ 610 + frame_size *= 5; 611 + frame_size /= 4; 612 + 613 + return ALIGN(frame_size, SZ_4K); 614 + } 615 + 616 + static inline u32 hfi_buffer_bin_enc(u32 width, u32 height, 617 + u32 work_mode, u32 lcu_size, 618 + u32 num_vpp_pipes, u32 rc_type) 619 + { 620 + u32 sao_bin_buffer_size, padded_bin_size, bitstream_size; 621 + u32 total_bitbin_buffers, size_single_pipe, bitbin_size; 622 + u32 aligned_height = ALIGN(height, lcu_size); 623 + u32 aligned_width = ALIGN(width, lcu_size); 624 + 625 + bitstream_size = size_bin_bitstream_enc(width, height, rc_type); 626 + bitstream_size = ALIGN(bitstream_size, 256); 627 + 628 + if (work_mode == STAGE_2) { 629 + total_bitbin_buffers = 3; 630 + bitbin_size = bitstream_size * 17 / 10; 631 + bitbin_size = ALIGN(bitbin_size, 256); 632 + } else { 633 + total_bitbin_buffers = 1; 634 + bitstream_size = aligned_width * aligned_height * 3; 635 + bitbin_size = ALIGN(bitstream_size, 256); 636 + } 637 + 638 + if (num_vpp_pipes > 2) 639 + size_single_pipe = bitbin_size / 2; 640 + else 641 + size_single_pipe = bitbin_size; 642 + 643 + size_single_pipe = ALIGN(size_single_pipe, 256); 644 + sao_bin_buffer_size = (64 * (((width + 32) * (height + 32)) >> 10)) + 384; 645 + padded_bin_size = ALIGN(size_single_pipe, 256); 646 + size_single_pipe = sao_bin_buffer_size + padded_bin_size; 647 + size_single_pipe = ALIGN(size_single_pipe, 256); 648 + bitbin_size = size_single_pipe * num_vpp_pipes; 649 + 650 + return ALIGN(bitbin_size, 256) * total_bitbin_buffers + 512; 651 + } 652 + 653 + static u32 iris_vpu_enc_bin_size(struct iris_inst *inst) 654 + { 655 + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 656 + u32 stage = inst->fw_caps[STAGE].value; 657 + struct v4l2_format *f = inst->fmt_dst; 658 + u32 height = f->fmt.pix_mp.height; 659 + u32 width = f->fmt.pix_mp.width; 660 + u32 lcu_size; 661 + 662 + if (inst->codec == V4L2_PIX_FMT_HEVC) 663 + lcu_size = 32; 664 + else 665 + lcu_size = 16; 666 + 667 + return hfi_buffer_bin_enc(width, height, stage, lcu_size, 668 + num_vpp_pipes, inst->hfi_rc_type); 669 + } 670 + 671 + static inline 672 + u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_height, u32 lcu_size, 673 + u32 num_recon, u32 standard) 674 + { 675 + u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 676 + u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 677 + u32 num_lcu_in_frame = width_in_lcus * height_in_lcus; 678 + u32 mb_height = ((frame_height) + 15) >> 4; 679 + u32 mb_width = ((frame_width) + 15) >> 4; 680 + u32 size_colloc_mv, size_colloc_rc; 681 + 682 + size_colloc_mv = (standard == HFI_CODEC_ENCODE_HEVC) ? 683 + (16 * ((num_lcu_in_frame << 2) + 32)) : 684 + (3 * 16 * (width_in_lcus * height_in_lcus + 32)); 685 + size_colloc_mv = ALIGN(size_colloc_mv, 256) * num_recon; 686 + size_colloc_rc = (((mb_width + 7) >> 3) * 16 * 2 * mb_height); 687 + size_colloc_rc = ALIGN(size_colloc_rc, 256) * HFI_MAX_COL_FRAME; 688 + 689 + return size_colloc_mv + size_colloc_rc; 690 + } 691 + 692 + static u32 iris_vpu_enc_comv_size(struct iris_inst *inst) 693 + { 694 + struct v4l2_format *f = inst->fmt_dst; 695 + u32 height = f->fmt.pix_mp.height; 696 + u32 width = f->fmt.pix_mp.width; 697 + u32 num_recon = 1; 698 + u32 lcu_size = 16; 699 + 700 + if (inst->codec == V4L2_PIX_FMT_HEVC) { 701 + lcu_size = 32; 702 + return hfi_buffer_comv_enc(width, height, lcu_size, 703 + num_recon + 1, HFI_CODEC_ENCODE_HEVC); 704 + } 705 + 706 + return hfi_buffer_comv_enc(width, height, lcu_size, 707 + num_recon + 1, HFI_CODEC_ENCODE_AVC); 708 + } 709 + 710 + static inline 711 + u32 size_frame_rc_buf_size(u32 standard, u32 frame_height_coded, 712 + u32 num_vpp_pipes_enc) 713 + { 714 + u32 size = 0; 715 + 716 + size = (standard == HFI_CODEC_ENCODE_HEVC) ? 717 + (256 + 16 * (14 + ((((frame_height_coded) >> 5) + 7) >> 3))) : 718 + (256 + 16 * (14 + ((((frame_height_coded) >> 4) + 7) >> 3))); 719 + size *= 11; 720 + 721 + if (num_vpp_pipes_enc > 1) 722 + size = ALIGN(size, 256) * num_vpp_pipes_enc; 723 + 724 + return ALIGN(size, 512) * HFI_MAX_COL_FRAME; 725 + } 726 + 727 + static inline 728 + u32 size_enc_slice_info_buf(u32 num_lcu_in_frame) 729 + { 730 + return ALIGN((256 + (num_lcu_in_frame << 4)), 256); 731 + } 732 + 733 + static inline u32 enc_bitcnt_buf_size(u32 num_lcu_in_frame) 734 + { 735 + return ALIGN((256 + (4 * (num_lcu_in_frame))), 256); 736 + } 737 + 738 + static inline u32 enc_bitmap_buf_size(u32 num_lcu_in_frame) 739 + { 740 + return ALIGN((256 + ((num_lcu_in_frame) >> 3)), 256); 741 + } 742 + 743 + static inline u32 size_override_buf(u32 num_lcumb) 744 + { 745 + return ALIGN(((16 * (((num_lcumb) + 7) >> 3))), 256) * 2; 746 + } 747 + 748 + static inline u32 size_ir_buf(u32 num_lcu_in_frame) 749 + { 750 + return ALIGN((((((num_lcu_in_frame) << 1) + 7) & (~7)) * 3), 256); 751 + } 752 + 753 + static inline 754 + u32 size_linebuff_data(bool is_ten_bit, u32 frame_width_coded) 755 + { 756 + return is_ten_bit ? 757 + (((((10 * (frame_width_coded) + 1024) + (256 - 1)) & 758 + (~(256 - 1))) * 1) + 759 + (((((10 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & 760 + (~(256 - 1))) * 2)) : 761 + (((((8 * (frame_width_coded) + 1024) + (256 - 1)) & 762 + (~(256 - 1))) * 1) + 763 + (((((8 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & 764 + (~(256 - 1))) * 2)); 765 + } 766 + 767 + static inline 768 + u32 size_left_linebuff_ctrl(u32 standard, u32 frame_height_coded, 769 + u32 num_vpp_pipes_enc) 770 + { 771 + u32 size = 0; 772 + 773 + size = standard == HFI_CODEC_ENCODE_HEVC ? 774 + (((frame_height_coded) + 775 + (32)) / 32 * 4 * 16) : 776 + (((frame_height_coded) + 15) / 16 * 5 * 16); 777 + 778 + if ((num_vpp_pipes_enc) > 1) { 779 + size += 512; 780 + size = ALIGN(size, 512) * 781 + num_vpp_pipes_enc; 782 + } 783 + 784 + return ALIGN(size, 256); 785 + } 786 + 787 + static inline 788 + u32 size_left_linebuff_recon_pix(bool is_ten_bit, u32 frame_height_coded, 789 + u32 num_vpp_pipes_enc) 790 + { 791 + return (((is_ten_bit + 1) * 2 * (frame_height_coded) + 256) + 792 + (256 << (num_vpp_pipes_enc - 1)) - 1) & 793 + (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1; 794 + } 795 + 796 + static inline 797 + u32 size_top_linebuff_ctrl_fe(u32 frame_width_coded, u32 standard) 798 + { 799 + return standard == HFI_CODEC_ENCODE_HEVC ? 800 + ALIGN((64 * ((frame_width_coded) >> 5)), 256) : 801 + ALIGN((256 + 16 * ((frame_width_coded) >> 4)), 256); 802 + } 803 + 804 + static inline 805 + u32 size_left_linebuff_ctrl_fe(u32 frame_height_coded, u32 num_vpp_pipes_enc) 806 + { 807 + return (((256 + 64 * ((frame_height_coded) >> 4)) + 808 + (256 << (num_vpp_pipes_enc - 1)) - 1) & 809 + (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1) * 810 + num_vpp_pipes_enc; 811 + } 812 + 813 + static inline 814 + u32 size_left_linebuff_metadata_recon_y(u32 frame_height_coded, 815 + bool is_ten_bit, 816 + u32 num_vpp_pipes_enc) 817 + { 818 + return ALIGN(((256 + 64 * ((frame_height_coded) / 819 + (8 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; 820 + } 821 + 822 + static inline 823 + u32 size_left_linebuff_metadata_recon_uv(u32 frame_height_coded, 824 + bool is_ten_bit, 825 + u32 num_vpp_pipes_enc) 826 + { 827 + return ALIGN(((256 + 64 * ((frame_height_coded) / 828 + (4 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; 829 + } 830 + 831 + static inline 832 + u32 size_linebuff_recon_pix(bool is_ten_bit, u32 frame_width_coded) 833 + { 834 + return ALIGN(((is_ten_bit ? 3 : 2) * (frame_width_coded)), 256); 835 + } 836 + 837 + static inline 838 + u32 size_line_buf_ctrl(u32 frame_width_coded) 839 + { 840 + return ALIGN(frame_width_coded, 256); 841 + } 842 + 843 + static inline 844 + u32 size_line_buf_ctrl_id2(u32 frame_width_coded) 845 + { 846 + return ALIGN(frame_width_coded, 256); 847 + } 848 + 849 + static inline u32 size_line_buf_sde(u32 frame_width_coded) 850 + { 851 + return ALIGN((256 + (16 * ((frame_width_coded) >> 4))), 256); 852 + } 853 + 854 + static inline 855 + u32 size_vpss_line_buf(u32 num_vpp_pipes_enc, u32 frame_height_coded, 856 + u32 frame_width_coded) 857 + { 858 + return ALIGN(((((((8192) >> 2) << 5) * (num_vpp_pipes_enc)) + 64) + 859 + (((((max_t(u32, (frame_width_coded), 860 + (frame_height_coded)) + 3) >> 2) << 5) + 256) * 16)), 256); 861 + } 862 + 863 + static inline 864 + u32 size_top_line_buf_first_stg_sao(u32 frame_width_coded) 865 + { 866 + return ALIGN((16 * ((frame_width_coded) >> 5)), 256); 867 + } 868 + 869 + static inline 870 + u32 size_enc_ref_buffer(u32 frame_width, u32 frame_height) 871 + { 872 + u32 u_chroma_buffer_height = ALIGN(frame_height >> 1, 32); 873 + u32 u_buffer_height = ALIGN(frame_height, 32); 874 + u32 u_buffer_width = ALIGN(frame_width, 32); 875 + 876 + return (u_buffer_height + u_chroma_buffer_height) * u_buffer_width; 877 + } 878 + 879 + static inline 880 + u32 size_enc_ten_bit_ref_buffer(u32 frame_width, u32 frame_height) 881 + { 882 + u32 ref_luma_stride_in_bytes = ((frame_width + SYSTEM_LAL_TILE10 - 1) / SYSTEM_LAL_TILE10) * 883 + SYSTEM_LAL_TILE10; 884 + u32 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1)); 885 + u32 u_ref_stride, luma_size; 886 + u32 ref_chrm_height_in_bytes; 887 + u32 chroma_size; 888 + 889 + u_ref_stride = 4 * (ref_luma_stride_in_bytes / 3); 890 + u_ref_stride = (u_ref_stride + (128 - 1)) & (~(128 - 1)); 891 + luma_size = ref_buf_height * u_ref_stride; 892 + luma_size = (luma_size + (4096 - 1)) & (~(4096 - 1)); 893 + 894 + ref_chrm_height_in_bytes = (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); 895 + chroma_size = u_ref_stride * ref_chrm_height_in_bytes; 896 + chroma_size = (chroma_size + (4096 - 1)) & (~(4096 - 1)); 897 + 898 + return luma_size + chroma_size; 899 + } 900 + 901 + static inline 902 + u32 hfi_ubwc_calc_metadata_plane_stride(u32 frame_width, 903 + u32 metadata_stride_multiple, 904 + u32 tile_width_in_pels) 905 + { 906 + return ALIGN(((frame_width + (tile_width_in_pels - 1)) / tile_width_in_pels), 907 + metadata_stride_multiple); 908 + } 909 + 910 + static inline 911 + u32 hfi_ubwc_metadata_plane_bufheight(u32 frame_height, 912 + u32 metadata_height_multiple, 913 + u32 tile_height_in_pels) 914 + { 915 + return ALIGN(((frame_height + (tile_height_in_pels - 1)) / tile_height_in_pels), 916 + metadata_height_multiple); 917 + } 918 + 919 + static inline 920 + u32 hfi_ubwc_metadata_plane_buffer_size(u32 _metadata_tride, u32 _metadata_buf_height) 921 + { 922 + return ALIGN(_metadata_tride * _metadata_buf_height, 4096); 923 + } 924 + 925 + static inline 926 + u32 hfi_buffer_non_comv_enc(u32 frame_width, u32 frame_height, 927 + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 928 + { 929 + u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 930 + u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 931 + u32 num_lcu_in_frame = width_in_lcus * height_in_lcus; 932 + u32 frame_height_coded = height_in_lcus * (lcu_size); 933 + u32 frame_width_coded = width_in_lcus * (lcu_size); 934 + u32 num_lcumb, frame_rc_buf_size; 935 + 936 + num_lcumb = (frame_height_coded / lcu_size) * 937 + ((frame_width_coded + lcu_size * 8) / lcu_size); 938 + frame_rc_buf_size = size_frame_rc_buf_size(standard, frame_height_coded, 939 + num_vpp_pipes_enc); 940 + return size_enc_slice_info_buf(num_lcu_in_frame) + 941 + SIZE_SLICE_CMD_BUFFER + 942 + SIZE_SPS_PPS_SLICE_HDR + 943 + frame_rc_buf_size + 944 + enc_bitcnt_buf_size(num_lcu_in_frame) + 945 + enc_bitmap_buf_size(num_lcu_in_frame) + 946 + SIZE_BSE_SLICE_CMD_BUF + 947 + SIZE_LAMBDA_LUT + 948 + size_override_buf(num_lcumb) + 949 + size_ir_buf(num_lcu_in_frame); 950 + } 951 + 952 + static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst) 953 + { 954 + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 955 + struct v4l2_format *f = inst->fmt_dst; 956 + u32 height = f->fmt.pix_mp.height; 957 + u32 width = f->fmt.pix_mp.width; 958 + u32 lcu_size = 16; 959 + 960 + if (inst->codec == V4L2_PIX_FMT_HEVC) { 961 + lcu_size = 32; 962 + return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, 963 + lcu_size, HFI_CODEC_ENCODE_HEVC) + 964 + SIZE_ONE_SLICE_BUF; 965 + } 966 + 967 + return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, 968 + lcu_size, HFI_CODEC_ENCODE_AVC); 969 + } 970 + 971 + static inline 972 + u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit, 973 + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 974 + { 975 + u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 976 + u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 977 + u32 frame_height_coded = height_in_lcus * (lcu_size); 978 + u32 frame_width_coded = width_in_lcus * (lcu_size); 979 + u32 line_buff_data_size, left_line_buff_ctrl_size; 980 + u32 left_line_buff_metadata_recon__uv__size; 981 + u32 left_line_buff_metadata_recon__y__size; 982 + u32 left_line_buff_recon_pix_size; 983 + u32 top_line_buff_ctrl_fe_size; 984 + u32 line_buff_recon_pix_size; 985 + 986 + line_buff_data_size = size_linebuff_data(is_ten_bit, frame_width_coded); 987 + left_line_buff_ctrl_size = 988 + size_left_linebuff_ctrl(standard, frame_height_coded, num_vpp_pipes_enc); 989 + left_line_buff_recon_pix_size = 990 + size_left_linebuff_recon_pix(is_ten_bit, frame_height_coded, 991 + num_vpp_pipes_enc); 992 + top_line_buff_ctrl_fe_size = 993 + size_top_linebuff_ctrl_fe(frame_width_coded, standard); 994 + left_line_buff_metadata_recon__y__size = 995 + size_left_linebuff_metadata_recon_y(frame_height_coded, is_ten_bit, 996 + num_vpp_pipes_enc); 997 + left_line_buff_metadata_recon__uv__size = 998 + size_left_linebuff_metadata_recon_uv(frame_height_coded, is_ten_bit, 999 + num_vpp_pipes_enc); 1000 + line_buff_recon_pix_size = size_linebuff_recon_pix(is_ten_bit, frame_width_coded); 1001 + 1002 + return size_line_buf_ctrl(frame_width_coded) + 1003 + size_line_buf_ctrl_id2(frame_width_coded) + 1004 + line_buff_data_size + 1005 + left_line_buff_ctrl_size + 1006 + left_line_buff_recon_pix_size + 1007 + top_line_buff_ctrl_fe_size + 1008 + left_line_buff_metadata_recon__y__size + 1009 + left_line_buff_metadata_recon__uv__size + 1010 + line_buff_recon_pix_size + 1011 + size_left_linebuff_ctrl_fe(frame_height_coded, num_vpp_pipes_enc) + 1012 + size_line_buf_sde(frame_width_coded) + 1013 + size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_coded) + 1014 + size_top_line_buf_first_stg_sao(frame_width_coded); 1015 + } 1016 + 1017 + static u32 iris_vpu_enc_line_size(struct iris_inst *inst) 1018 + { 1019 + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1020 + struct v4l2_format *f = inst->fmt_dst; 1021 + u32 height = f->fmt.pix_mp.height; 1022 + u32 width = f->fmt.pix_mp.width; 1023 + u32 lcu_size = 16; 1024 + 1025 + if (inst->codec == V4L2_PIX_FMT_HEVC) { 1026 + lcu_size = 32; 1027 + return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, 1028 + lcu_size, HFI_CODEC_ENCODE_HEVC); 1029 + } 1030 + 1031 + return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, 1032 + lcu_size, HFI_CODEC_ENCODE_AVC); 1033 + } 1034 + 1035 + static inline 1036 + u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit) 1037 + { 1038 + u32 metadata_stride, metadata_buf_height, meta_size_y, meta_size_c; 1039 + u32 ten_bit_ref_buf_size = 0, ref_buf_size = 0; 1040 + u32 size; 1041 + 1042 + if (!is_ten_bit) { 1043 + ref_buf_size = size_enc_ref_buffer(frame_width, frame_height); 1044 + metadata_stride = 1045 + hfi_ubwc_calc_metadata_plane_stride(frame_width, 64, 1046 + HFI_COL_FMT_NV12C_Y_TILE_WIDTH); 1047 + metadata_buf_height = 1048 + hfi_ubwc_metadata_plane_bufheight(frame_height, 16, 1049 + HFI_COL_FMT_NV12C_Y_TILE_HEIGHT); 1050 + meta_size_y = 1051 + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1052 + meta_size_c = 1053 + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1054 + size = ref_buf_size + meta_size_y + meta_size_c; 1055 + } else { 1056 + ten_bit_ref_buf_size = size_enc_ten_bit_ref_buffer(frame_width, frame_height); 1057 + metadata_stride = 1058 + hfi_ubwc_calc_metadata_plane_stride(frame_width, 1059 + IRIS_METADATA_STRIDE_MULTIPLE, 1060 + HFI_COL_FMT_TP10C_Y_TILE_WIDTH); 1061 + metadata_buf_height = 1062 + hfi_ubwc_metadata_plane_bufheight(frame_height, 1063 + IRIS_METADATA_HEIGHT_MULTIPLE, 1064 + HFI_COL_FMT_TP10C_Y_TILE_HEIGHT); 1065 + meta_size_y = 1066 + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1067 + meta_size_c = 1068 + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1069 + size = ten_bit_ref_buf_size + meta_size_y + meta_size_c; 1070 + } 1071 + 1072 + return size; 1073 + } 1074 + 1075 + static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) 1076 + { 1077 + return HFI_BUFFER_ARP_ENC; 1078 + } 1079 + 1080 + inline bool is_scaling_enabled(struct iris_inst *inst) 1081 + { 1082 + return inst->crop.left != inst->compose.left || 1083 + inst->crop.top != inst->compose.top || 1084 + inst->crop.width != inst->compose.width || 1085 + inst->crop.height != inst->compose.height; 1086 + } 1087 + 1088 + static inline 1089 + u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable, 1090 + u32 blur, bool is_ten_bit) 1091 + { 1092 + if (ds_enable || blur) 1093 + return hfi_buffer_dpb_enc(dswidth, dsheight, is_ten_bit); 1094 + 1095 + return 0; 1096 + } 1097 + 1098 + static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_height, 1099 + u32 lcu_size, u32 num_ref, 1100 + bool ten_bit, u32 num_vpp_pipes, 1101 + bool is_h265) 1102 + { 1103 + u32 line_buf_ctrl_size, line_buf_data_size, leftline_buf_ctrl_size; 1104 + u32 line_buf_sde_size, sps_pps_slice_hdr, topline_buf_ctrl_size_FE; 1105 + u32 leftline_buf_ctrl_size_FE, line_buf_recon_pix_size; 1106 + u32 leftline_buf_recon_pix_size, lambda_lut_size, override_buffer_size; 1107 + u32 col_mv_buf_size, vpp_reg_buffer_size, ir_buffer_size; 1108 + u32 vpss_line_buf, leftline_buf_meta_recony, h265e_colrcbuf_size; 1109 + u32 h265e_framerc_bufsize, h265e_lcubitcnt_bufsize; 1110 + u32 h265e_lcubitmap_bufsize, se_stats_bufsize; 1111 + u32 bse_reg_buffer_size, bse_slice_cmd_buffer_size, slice_info_bufsize; 1112 + u32 line_buf_ctrl_size_buffid2, slice_cmd_buffer_size; 1113 + u32 width_lcu_num, height_lcu_num, width_coded, height_coded; 1114 + u32 frame_num_lcu, linebuf_meta_recon_uv, topline_bufsize_fe_1stg_sao; 1115 + u32 vpss_line_buffer_size_1; 1116 + u32 bit_depth, num_lcu_mb; 1117 + 1118 + width_lcu_num = (frame_width + lcu_size - 1) / lcu_size; 1119 + height_lcu_num = (frame_height + lcu_size - 1) / lcu_size; 1120 + frame_num_lcu = width_lcu_num * height_lcu_num; 1121 + width_coded = width_lcu_num * lcu_size; 1122 + height_coded = height_lcu_num * lcu_size; 1123 + num_lcu_mb = (height_coded / lcu_size) * 1124 + ((width_coded + lcu_size * 8) / lcu_size); 1125 + slice_info_bufsize = 256 + (frame_num_lcu << 4); 1126 + slice_info_bufsize = ALIGN(slice_info_bufsize, 256); 1127 + line_buf_ctrl_size = ALIGN(width_coded, 256); 1128 + line_buf_ctrl_size_buffid2 = ALIGN(width_coded, 256); 1129 + 1130 + bit_depth = ten_bit ? 10 : 8; 1131 + line_buf_data_size = 1132 + (((((bit_depth * width_coded + 1024) + (256 - 1)) & 1133 + (~(256 - 1))) * 1) + 1134 + (((((bit_depth * width_coded + 1024) >> 1) + (256 - 1)) & 1135 + (~(256 - 1))) * 2)); 1136 + 1137 + leftline_buf_ctrl_size = is_h265 ? ((height_coded + 32) / 32 * 4 * 16) : 1138 + ((height_coded + 15) / 16 * 5 * 16); 1139 + 1140 + if (num_vpp_pipes > 1) { 1141 + leftline_buf_ctrl_size += 512; 1142 + leftline_buf_ctrl_size = 1143 + ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes; 1144 + } 1145 + 1146 + leftline_buf_ctrl_size = ALIGN(leftline_buf_ctrl_size, 256); 1147 + leftline_buf_recon_pix_size = 1148 + (((ten_bit + 1) * 2 * (height_coded) + 256) + 1149 + (256 << (num_vpp_pipes - 1)) - 1) & 1150 + (~((256 << (num_vpp_pipes - 1)) - 1)) * 1; 1151 + 1152 + topline_buf_ctrl_size_FE = is_h265 ? (64 * (width_coded >> 5)) : 1153 + (256 + 16 * (width_coded >> 4)); 1154 + topline_buf_ctrl_size_FE = ALIGN(topline_buf_ctrl_size_FE, 256); 1155 + leftline_buf_ctrl_size_FE = 1156 + (((256 + 64 * (height_coded >> 4)) + 1157 + (256 << (num_vpp_pipes - 1)) - 1) & 1158 + (~((256 << (num_vpp_pipes - 1)) - 1)) * 1) * 1159 + num_vpp_pipes; 1160 + leftline_buf_meta_recony = 1161 + (256 + 64 * ((height_coded) / (8 * (ten_bit ? 4 : 8)))); 1162 + leftline_buf_meta_recony = ALIGN(leftline_buf_meta_recony, 256); 1163 + leftline_buf_meta_recony = leftline_buf_meta_recony * num_vpp_pipes; 1164 + linebuf_meta_recon_uv = 1165 + (256 + 64 * ((height_coded) / (4 * (ten_bit ? 4 : 8)))); 1166 + linebuf_meta_recon_uv = ALIGN(linebuf_meta_recon_uv, 256); 1167 + linebuf_meta_recon_uv = linebuf_meta_recon_uv * num_vpp_pipes; 1168 + line_buf_recon_pix_size = ((ten_bit ? 3 : 2) * width_coded); 1169 + line_buf_recon_pix_size = ALIGN(line_buf_recon_pix_size, 256); 1170 + slice_cmd_buffer_size = ALIGN(20480, 256); 1171 + sps_pps_slice_hdr = 2048 + 4096; 1172 + col_mv_buf_size = 1173 + is_h265 ? (16 * ((frame_num_lcu << 2) + 32)) : 1174 + (3 * 16 * (width_lcu_num * height_lcu_num + 32)); 1175 + col_mv_buf_size = ALIGN(col_mv_buf_size, 256) * (num_ref + 1); 1176 + h265e_colrcbuf_size = 1177 + (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); 1178 + if (num_vpp_pipes > 1) 1179 + h265e_colrcbuf_size = 1180 + ALIGN(h265e_colrcbuf_size, 256) * num_vpp_pipes; 1181 + 1182 + h265e_colrcbuf_size = 1183 + ALIGN(h265e_colrcbuf_size, 256) * HFI_MAX_COL_FRAME; 1184 + h265e_framerc_bufsize = 1185 + (is_h265) ? 1186 + (256 + 16 * (14 + (((height_coded >> 5) + 7) >> 3))) : 1187 + (256 + 16 * (14 + (((height_coded >> 4) + 7) >> 3))); 1188 + h265e_framerc_bufsize *= 6; 1189 + if (num_vpp_pipes > 1) 1190 + h265e_framerc_bufsize = 1191 + ALIGN(h265e_framerc_bufsize, 256) * num_vpp_pipes; 1192 + 1193 + h265e_framerc_bufsize = 1194 + ALIGN(h265e_framerc_bufsize, 512) * HFI_MAX_COL_FRAME; 1195 + h265e_lcubitcnt_bufsize = 256 + 4 * frame_num_lcu; 1196 + h265e_lcubitcnt_bufsize = ALIGN(h265e_lcubitcnt_bufsize, 256); 1197 + h265e_lcubitmap_bufsize = 256 + (frame_num_lcu >> 3); 1198 + h265e_lcubitmap_bufsize = ALIGN(h265e_lcubitmap_bufsize, 256); 1199 + line_buf_sde_size = 256 + 16 * (width_coded >> 4); 1200 + line_buf_sde_size = ALIGN(line_buf_sde_size, 256); 1201 + if ((width_coded * height_coded) > (4096 * 2160)) 1202 + se_stats_bufsize = 0; 1203 + else if ((width_coded * height_coded) > (1920 * 1088)) 1204 + se_stats_bufsize = (40 * 4 * frame_num_lcu + 256 + 256); 1205 + else 1206 + se_stats_bufsize = (1024 * frame_num_lcu + 256 + 256); 1207 + 1208 + se_stats_bufsize = ALIGN(se_stats_bufsize, 256) * 2; 1209 + bse_slice_cmd_buffer_size = (((8192 << 2) + 7) & (~7)) * 6; 1210 + bse_reg_buffer_size = (((512 << 3) + 7) & (~7)) * 4; 1211 + vpp_reg_buffer_size = (((2048 << 3) + 31) & (~31)) * 10; 1212 + lambda_lut_size = 256 * 11; 1213 + override_buffer_size = 16 * ((num_lcu_mb + 7) >> 3); 1214 + override_buffer_size = ALIGN(override_buffer_size, 256) * 2; 1215 + ir_buffer_size = (((frame_num_lcu << 1) + 7) & (~7)) * 3; 1216 + vpss_line_buffer_size_1 = (((8192 >> 2) << 5) * num_vpp_pipes) + 64; 1217 + vpss_line_buf = 1218 + (((((max(width_coded, height_coded) + 3) >> 2) << 5) + 256) * 1219 + 16) + 1220 + vpss_line_buffer_size_1; 1221 + topline_bufsize_fe_1stg_sao = 16 * (width_coded >> 5); 1222 + topline_bufsize_fe_1stg_sao = ALIGN(topline_bufsize_fe_1stg_sao, 256); 1223 + 1224 + return line_buf_ctrl_size + line_buf_data_size + 1225 + line_buf_ctrl_size_buffid2 + leftline_buf_ctrl_size + 1226 + vpss_line_buf + col_mv_buf_size + topline_buf_ctrl_size_FE + 1227 + leftline_buf_ctrl_size_FE + line_buf_recon_pix_size + 1228 + leftline_buf_recon_pix_size + leftline_buf_meta_recony + 1229 + linebuf_meta_recon_uv + h265e_colrcbuf_size + 1230 + h265e_framerc_bufsize + h265e_lcubitcnt_bufsize + 1231 + h265e_lcubitmap_bufsize + line_buf_sde_size + 1232 + topline_bufsize_fe_1stg_sao + override_buffer_size + 1233 + bse_reg_buffer_size + vpp_reg_buffer_size + sps_pps_slice_hdr + 1234 + slice_cmd_buffer_size + bse_slice_cmd_buffer_size + 1235 + ir_buffer_size + slice_info_bufsize + lambda_lut_size + 1236 + se_stats_bufsize + 1024; 1237 + } 1238 + 1239 + static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst) 1240 + { 1241 + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1242 + struct v4l2_format *f = inst->fmt_dst; 1243 + u32 frame_height = f->fmt.pix_mp.height; 1244 + u32 frame_width = f->fmt.pix_mp.width; 1245 + u32 num_ref = 1; 1246 + u32 lcu_size; 1247 + bool is_h265; 1248 + 1249 + if (inst->codec == V4L2_PIX_FMT_H264) { 1250 + lcu_size = 16; 1251 + is_h265 = false; 1252 + } else if (inst->codec == V4L2_PIX_FMT_HEVC) { 1253 + lcu_size = 32; 1254 + is_h265 = true; 1255 + } else { 1256 + return 0; 1257 + } 1258 + 1259 + return hfi_buffer_scratch1_enc(frame_width, frame_height, lcu_size, 1260 + num_ref, false, num_vpp_pipes, is_h265); 1261 + } 1262 + 1263 + static inline u32 ubwc_metadata_plane_stride(u32 width, 1264 + u32 metadata_stride_multi, 1265 + u32 tile_width_pels) 1266 + { 1267 + return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels), 1268 + metadata_stride_multi); 1269 + } 1270 + 1271 + static inline u32 ubwc_metadata_plane_bufheight(u32 height, 1272 + u32 metadata_height_multi, 1273 + u32 tile_height_pels) 1274 + { 1275 + return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels), 1276 + metadata_height_multi); 1277 + } 1278 + 1279 + static inline u32 ubwc_metadata_plane_buffer_size(u32 metadata_stride, 1280 + u32 metadata_buf_height) 1281 + { 1282 + return ALIGN(metadata_stride * metadata_buf_height, SZ_4K); 1283 + } 1284 + 1285 + static inline u32 hfi_buffer_scratch2_enc(u32 frame_width, u32 frame_height, 1286 + u32 num_ref, bool ten_bit) 1287 + { 1288 + u32 aligned_width, aligned_height, chroma_height, ref_buf_height; 1289 + u32 metadata_stride, meta_buf_height, meta_size_y, meta_size_c; 1290 + u32 ref_luma_stride_bytes, ref_chroma_height_bytes; 1291 + u32 ref_buf_size, ref_stride; 1292 + u32 luma_size, chroma_size; 1293 + u32 size; 1294 + 1295 + if (!ten_bit) { 1296 + aligned_height = ALIGN(frame_height, 32); 1297 + chroma_height = frame_height >> 1; 1298 + chroma_height = ALIGN(chroma_height, 32); 1299 + aligned_width = ALIGN(frame_width, 128); 1300 + metadata_stride = 1301 + ubwc_metadata_plane_stride(frame_width, 64, 32); 1302 + meta_buf_height = 1303 + ubwc_metadata_plane_bufheight(frame_height, 16, 8); 1304 + meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, 1305 + meta_buf_height); 1306 + meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, 1307 + meta_buf_height); 1308 + size = (aligned_height + chroma_height) * aligned_width + 1309 + meta_size_y + meta_size_c; 1310 + size = (size * (num_ref + 3)) + 4096; 1311 + } else { 1312 + ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1)); 1313 + ref_luma_stride_bytes = ((frame_width + 192 - 1) / 192) * 192; 1314 + ref_stride = 4 * (ref_luma_stride_bytes / 3); 1315 + ref_stride = (ref_stride + (128 - 1)) & (~(128 - 1)); 1316 + luma_size = ref_buf_height * ref_stride; 1317 + ref_chroma_height_bytes = 1318 + (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); 1319 + chroma_size = ref_stride * ref_chroma_height_bytes; 1320 + luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); 1321 + chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); 1322 + ref_buf_size = luma_size + chroma_size; 1323 + metadata_stride = 1324 + ubwc_metadata_plane_stride(frame_width, 64, 48); 1325 + meta_buf_height = 1326 + ubwc_metadata_plane_bufheight(frame_height, 16, 4); 1327 + meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, 1328 + meta_buf_height); 1329 + meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, 1330 + meta_buf_height); 1331 + size = ref_buf_size + meta_size_y + meta_size_c; 1332 + size = (size * (num_ref + 3)) + 4096; 1333 + } 1334 + 1335 + return size; 1336 + } 1337 + 1338 + static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst) 1339 + { 1340 + struct v4l2_format *f = inst->fmt_dst; 1341 + u32 frame_width = f->fmt.pix_mp.width; 1342 + u32 frame_height = f->fmt.pix_mp.height; 1343 + u32 num_ref = 1; 1344 + 1345 + return hfi_buffer_scratch2_enc(frame_width, frame_height, num_ref, 1346 + false); 1347 + } 1348 + 1349 + static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst) 1350 + { 1351 + u32 ds_enable = is_scaling_enabled(inst); 1352 + struct v4l2_format *f = inst->fmt_dst; 1353 + u32 height = f->fmt.pix_mp.height; 1354 + u32 width = f->fmt.pix_mp.width; 1355 + 1356 + return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); 1357 + } 1358 + 559 1359 static int output_min_count(struct iris_inst *inst) 560 1360 { 561 1361 int output_min_count = 4; ··· 1389 573 1390 574 int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) 1391 575 { 1392 - const struct iris_vpu_buf_type_handle *buf_type_handle_arr; 1393 - u32 size = 0, buf_type_handle_size, i; 576 + const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL; 577 + u32 size = 0, buf_type_handle_size = 0, i; 1394 578 1395 579 static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = { 1396 580 {BUF_BIN, iris_vpu_dec_bin_size }, ··· 1402 586 {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, 1403 587 }; 1404 588 1405 - buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle); 1406 - buf_type_handle_arr = dec_internal_buf_type_handle; 589 + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = { 590 + {BUF_BIN, iris_vpu_enc_bin_size }, 591 + {BUF_COMV, iris_vpu_enc_comv_size }, 592 + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, 593 + {BUF_LINE, iris_vpu_enc_line_size }, 594 + {BUF_ARP, iris_vpu_enc_arp_size }, 595 + {BUF_VPSS, iris_vpu_enc_vpss_size }, 596 + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, 597 + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, 598 + }; 599 + 600 + if (inst->domain == DECODER) { 601 + buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle); 602 + buf_type_handle_arr = dec_internal_buf_type_handle; 603 + } else if (inst->domain == ENCODER) { 604 + buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle); 605 + buf_type_handle_arr = enc_internal_buf_type_handle; 606 + } 1407 607 1408 608 for (i = 0; i < buf_type_handle_size; i++) { 1409 609 if (buf_type_handle_arr[i].type == buffer_type) { ··· 1471 639 case BUF_PERSIST: 1472 640 return internal_buffer_count(inst, buffer_type); 1473 641 case BUF_SCRATCH_1: 642 + case BUF_SCRATCH_2: 643 + case BUF_VPSS: 644 + case BUF_ARP: 1474 645 return 1; /* internal buffer count needed by firmware is 1 */ 1475 646 case BUF_DPB: 1476 647 return iris_vpu_dpb_count(inst);
+21
drivers/media/platform/qcom/iris/iris_vpu_buffer.h
··· 41 41 #define SIZE_SLIST_BUF_H265 (BIT(10)) 42 42 #define H265_DISPLAY_BUF_SIZE (3072) 43 43 #define H265_NUM_FRM_INFO (48) 44 + #define SIZE_ONE_SLICE_BUF 256 44 45 45 46 #define VP9_NUM_FRAME_INFO_BUF 32 46 47 #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) ··· 80 79 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 81 80 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 82 81 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 82 + 83 + #define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256)) 84 + #define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096) 85 + #define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3) 86 + #define SIZE_LAMBDA_LUT (256 * 11) 87 + 88 + #define HFI_COL_FMT_NV12C_Y_TILE_HEIGHT (8) 89 + #define HFI_COL_FMT_NV12C_Y_TILE_WIDTH (32) 90 + #define HFI_COL_FMT_TP10C_Y_TILE_HEIGHT (4) 91 + #define HFI_COL_FMT_TP10C_Y_TILE_WIDTH (48) 92 + 93 + #define IRIS_METADATA_STRIDE_MULTIPLE 64 94 + #define IRIS_METADATA_HEIGHT_MULTIPLE 16 95 + 96 + #define HFI_BUFFER_ARP_ENC 204800 97 + 98 + #define MAX_WIDTH 4096 99 + #define MAX_HEIGHT 2304 100 + #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16)) 101 + #define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4)) 83 102 84 103 static inline u32 size_h264d_lb_fe_top_data(u32 frame_width) 85 104 {