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linux
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)
Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10. This patch fixes the offset relative
to the GC block on gfx10.
(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Tom St Denis
and committed by
Alex Deucher
614c5611
9fb10671
+4
-4
+2
-2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+2
-2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
···
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#ifndef _gc_10_1_0_OFFSET_HEADER
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#define _gc_10_1_0_OFFSET_HEADER
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-
#define mmSQ_DEBUG_STS_GLOBAL 0x0309
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+
#define mmSQ_DEBUG_STS_GLOBAL 0x10A9
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#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
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-
#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
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+
#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0
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#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
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// addressBlock: gc_sdma0_sdma0dec
+2
-2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+2
-2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
···
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#ifndef _gc_10_3_0_OFFSET_HEADER
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#define _gc_10_3_0_OFFSET_HEADER
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-
#define mmSQ_DEBUG_STS_GLOBAL 0x0309
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+
#define mmSQ_DEBUG_STS_GLOBAL 0x10A9
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#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
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-
#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
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+
#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0
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#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
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// addressBlock: gc_sdma0_sdma0dec