tjh.dev / kernel
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bindings: PCI: artpec: correct pci binding example

- Increase config size. When using a PCIe switch,
the previous config size only had room for one device.
- Add bus range. Inherited optional property.
- Map downstream I/O to PCI address 0. We can map it to any
address, but let's be consistent with other drivers.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Niklas Cassel and committed by
Rob Herring 610e1283 58397832

+4 -3
+4 -3
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
··· 24 24 compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 25 25 reg = <0xf8050000 0x2000 26 26 0xf8040000 0x1000 27 - 0xc0000000 0x1000>; 27 + 0xc0000000 0x2000>; 28 28 reg-names = "dbi", "phy", "config"; 29 29 #address-cells = <3>; 30 30 #size-cells = <2>; 31 31 device_type = "pci"; 32 32 /* downstream I/O */ 33 - ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000 33 + ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 34 34 /* non-prefetchable memory */ 35 - 0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>; 35 + 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; 36 36 num-lanes = <2>; 37 + bus-range = <0x00 0xff>; 37 38 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 38 39 interrupt-names = "msi"; 39 40 #interrupt-cells = <1>;