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ARM: dts: Alpine platform binding documentation

This patch introduces documentation for alpine devicetree bindings.

Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

Tsahee Zidenberg and committed by
Arnd Bergmann
60f9e37a e9e06f28

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Documentation/devicetree/bindings/arm/al,alpine.txt
··· 1 + Annapurna Labs Alpine Platform Device Tree Bindings 2 + --------------------------------------------------------------- 3 + 4 + Boards in the Alpine family shall have the following properties: 5 + 6 + * Required root node properties: 7 + compatible: must contain "al,alpine" 8 + 9 + * Example: 10 + 11 + / { 12 + model = "Annapurna Labs Alpine Dev Board"; 13 + compatible = "al,alpine"; 14 + 15 + ... 16 + } 17 + 18 + * CPU node: 19 + 20 + The Alpine platform includes cortex-a15 cores. 21 + enable-method: must be "al,alpine-smp" to allow smp [1] 22 + 23 + Example: 24 + 25 + cpus { 26 + #address-cells = <1>; 27 + #size-cells = <0>; 28 + enable-method = "al,alpine-smp"; 29 + 30 + cpu@0 { 31 + compatible = "arm,cortex-a15"; 32 + device_type = "cpu"; 33 + reg = <0>; 34 + }; 35 + 36 + cpu@1 { 37 + compatible = "arm,cortex-a15"; 38 + device_type = "cpu"; 39 + reg = <1>; 40 + }; 41 + 42 + cpu@2 { 43 + compatible = "arm,cortex-a15"; 44 + device_type = "cpu"; 45 + reg = <2>; 46 + }; 47 + 48 + cpu@3 { 49 + compatible = "arm,cortex-a15"; 50 + device_type = "cpu"; 51 + reg = <3>; 52 + }; 53 + }; 54 + 55 + 56 + * Alpine CPU resume registers 57 + 58 + The CPU resume register are used to define required resume address after 59 + reset. 60 + 61 + Properties: 62 + - compatible : Should contain "al,alpine-cpu-resume". 63 + - reg : Offset and length of the register set for the device 64 + 65 + Example: 66 + 67 + cpu_resume { 68 + compatible = "al,alpine-cpu-resume"; 69 + reg = <0xfbff5ed0 0x30>; 70 + }; 71 + 72 + * Alpine System-Fabric Service Registers 73 + 74 + The System-Fabric Service Registers allow various operation on CPU and 75 + system fabric, like powering CPUs off. 76 + 77 + Properties: 78 + - compatible : Should contain "al,alpine-sysfabric-service" and "syscon". 79 + - reg : Offset and length of the register set for the device 80 + 81 + Example: 82 + 83 + nb_service { 84 + compatible = "al,alpine-sysfabric-service", "syscon"; 85 + reg = <0xfb070000 0x10000>; 86 + }; 87 + 88 + [1] arm/cpu-enable-method/al,alpine-smp
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Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp
··· 1 + ======================================================== 2 + Secondary CPU enable-method "al,alpine-smp" binding 3 + ======================================================== 4 + 5 + This document describes the "al,alpine-smp" method for 6 + enabling secondary CPUs. To apply to all CPUs, a single 7 + "al,alpine-smp" enable method should be defined in the 8 + "cpus" node. 9 + 10 + Enable method name: "al,alpine-smp" 11 + Compatible machines: "al,alpine" 12 + Compatible CPUs: "arm,cortex-a15" 13 + Related properties: (none) 14 + 15 + Note: 16 + This enable method requires valid nodes compatible with 17 + "al,alpine-cpu-resume" and "al,alpine-nb-service"[1]. 18 + 19 + Example: 20 + 21 + cpus { 22 + #address-cells = <1>; 23 + #size-cells = <0>; 24 + enable-method = "al,alpine-smp"; 25 + 26 + cpu@0 { 27 + compatible = "arm,cortex-a15"; 28 + device_type = "cpu"; 29 + reg = <0>; 30 + }; 31 + 32 + cpu@1 { 33 + compatible = "arm,cortex-a15"; 34 + device_type = "cpu"; 35 + reg = <1>; 36 + }; 37 + 38 + cpu@2 { 39 + compatible = "arm,cortex-a15"; 40 + device_type = "cpu"; 41 + reg = <2>; 42 + }; 43 + 44 + cpu@3 { 45 + compatible = "arm,cortex-a15"; 46 + device_type = "cpu"; 47 + reg = <3>; 48 + }; 49 + }; 50 + 51 + -- 52 + [1] arm/al,alpine.txt
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Documentation/devicetree/bindings/vendor-prefixes.txt
··· 11 11 adh AD Holdings Plc. 12 12 adi Analog Devices, Inc. 13 13 aeroflexgaisler Aeroflex Gaisler AB 14 + al Annapurna Labs 14 15 allwinner Allwinner Technology Co., Ltd. 15 16 alphascale AlphaScale Integrated Circuits Systems, Inc. 16 17 altr Altera Corp.