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kernel
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linux
drm/amdgpu/vcn: add common vcn sofware ring decode
Add common vcn sofware ring decode.
v2: fixed compiling error
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian Koenig <Christian.Koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
James Zhu
and committed by
Alex Deucher
60a2e9ee
e02fe3bc
+130
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+85
drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c
+85
drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c
···
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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u64 seq, uint32_t flags)
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{
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
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amdgpu_ring_write(ring, addr);
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
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}
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void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
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}
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void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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struct amdgpu_ib *ib, uint32_t flags)
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{
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uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
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amdgpu_ring_write(ring, vmid);
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amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, ib->length_dw);
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}
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void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask)
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{
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
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amdgpu_ring_write(ring, reg << 2);
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amdgpu_ring_write(ring, mask);
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amdgpu_ring_write(ring, val);
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}
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void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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uint32_t vmid, uint64_t pd_addr)
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t data0, data1, mask;
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pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
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/* wait for register write */
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data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
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data1 = lower_32_bits(pd_addr);
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mask = 0xffffffff;
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vcn_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
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}
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void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val)
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{
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
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amdgpu_ring_write(ring, reg << 2);
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amdgpu_ring_write(ring, val);
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}
+44
drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.h
+44
drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.h
···
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
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+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
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+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __VCN_SW_RING_H__
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#define __VCN_SW_RING_H__
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#define VCN_SW_RING_EMIT_FRAME_SIZE \
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(4 + /* vcn_dec_sw_ring_emit_vm_flush */ \
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5 + 5 + /* vcn_dec_sw_ring_emit_fence x2 vm fence */ \
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1) /* vcn_dec_sw_ring_insert_end */
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void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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u64 seq, uint32_t flags);
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void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring);
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void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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struct amdgpu_ib *ib, uint32_t flags);
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void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask);
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void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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uint32_t vmid, uint64_t pd_addr);
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void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val);
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#endif /* __VCN_SW_RING_H__ */