···11+Xilinx plb/axi GPIO controller22+33+Dual channel GPIO controller with configurable number of pins44+(from 1 to 32 per channel). Every pin can be configured as55+input/output/tristate. Both channels share the same global IRQ but66+local interrupts can be enabled on channel basis.77+88+Required properties:99+- compatible : Should be "xlnx,xps-gpio-1.00.a"1010+- reg : Address and length of the register set for the device1111+- #gpio-cells : Should be two. The first cell is the pin number and the1212+ second cell is used to specify optional parameters (currently unused).1313+- gpio-controller : Marks the device node as a GPIO controller.1414+1515+Optional properties:1616+- interrupts : Interrupt mapping for GPIO IRQ.1717+- interrupt-parent : Phandle for the interrupt controller that1818+ services interrupts for this device.1919+- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input2020+- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 12121+- xlnx,gpio-width : gpio width2222+- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode2323+- xlnx,is-dual : if 1, controller also uses the second channel2424+- xlnx,all-inputs-2 : as above but for the second channel2525+- xlnx,dout-default-2 : as above but the second channel2626+- xlnx,gpio2-width : as above but for the second channel2727+- xlnx,tri-default-2 : as above but for the second channel2828+2929+3030+Example:3131+gpio: gpio@40000000 {3232+ #gpio-cells = <2>;3333+ compatible = "xlnx,xps-gpio-1.00.a";3434+ gpio-controller ;3535+ interrupt-parent = <µblaze_0_intc>;3636+ interrupts = < 6 2 >;3737+ reg = < 0x40000000 0x10000 >;3838+ xlnx,all-inputs = <0x0>;3939+ xlnx,all-inputs-2 = <0x0>;4040+ xlnx,dout-default = <0x0>;4141+ xlnx,dout-default-2 = <0x0>;4242+ xlnx,gpio-width = <0x2>;4343+ xlnx,gpio2-width = <0x2>;4444+ xlnx,interrupt-present = <0x1>;4545+ xlnx,is-dual = <0x1>;4646+ xlnx,tri-default = <0xffffffff>;4747+ xlnx,tri-default-2 = <0xffffffff>;4848+} ;