tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'renesas-clock-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Merge "Renesas ARM Based SoC Clock Updates for v3.15" from Simon Horman:

* r7s72100 SoC (RZ/A1H)
- Add clock for SH Ethernet
- Add RSPI clocks

* r8a7791 (R-Car M2)
- Add QSPI and SDHI clocks

* r8a7790 (R-Car H2)
- Add audio clock
- Remove legacy DT clocks
- Correct SYS DMAC clock defines

* tag 'renesas-clock-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Remove legacy r8a7790 DT clocks
ARM: shmobile: Add r8a7791 legacy SDHI clocks
ARM: shmobile: r8a7790: Correct SYS DMAC clock defines
ARM: shmobile: r7s72100: Add clock for r7s72100-ether
ARM: shmobile: r8a7791 clock: add QSPI clocks
ARM: shmobile: r7s72100 clock: Add RSPI clocks for DT
ARM: shmobile: r7s72100 clock: Add RSPI clocks
ARM: shmobile: r8a7790: add audio clock
ARM: shmobile: r8a7778: add audio clock in new style

Signed-off-by: Olof Johansson <olof@lixom.net>

Olof Johansson 6020dd9b 63261d76

+136 -18
+23
arch/arm/boot/dts/r8a7790.dtsi
··· 313 313 clock-output-names = "extal"; 314 314 }; 315 315 316 + /* 317 + * The external audio clocks are configured as 0 Hz fixed frequency clocks by 318 + * default. Boards that provide audio clocks should override them. 319 + */ 320 + audio_clk_a: audio_clk_a { 321 + compatible = "fixed-clock"; 322 + #clock-cells = <0>; 323 + clock-frequency = <0>; 324 + clock-output-names = "audio_clk_a"; 325 + }; 326 + audio_clk_b: audio_clk_b { 327 + compatible = "fixed-clock"; 328 + #clock-cells = <0>; 329 + clock-frequency = <0>; 330 + clock-output-names = "audio_clk_b"; 331 + }; 332 + audio_clk_c: audio_clk_c { 333 + compatible = "fixed-clock"; 334 + #clock-cells = <0>; 335 + clock-frequency = <0>; 336 + clock-output-names = "audio_clk_c"; 337 + }; 338 + 316 339 /* Special CPG clocks */ 317 340 cpg_clocks: cpg_clocks@e6150000 { 318 341 compatible = "renesas,r8a7790-cpg-clocks",
+27 -3
arch/arm/mach-shmobile/clock-r7s72100.c
··· 22 22 #include <mach/common.h> 23 23 #include <mach/r7s72100.h> 24 24 25 - /* registers */ 25 + /* Frequency Control Registers */ 26 26 #define FRQCR 0xfcfe0010 27 27 #define FRQCR2 0xfcfe0014 28 + /* Standby Control Registers */ 28 29 #define STBCR3 0xfcfe0420 29 30 #define STBCR4 0xfcfe0424 31 + #define STBCR7 0xfcfe0430 30 32 #define STBCR9 0xfcfe0438 33 + #define STBCR10 0xfcfe043c 31 34 32 35 #define PLL_RATE 30 33 36 ··· 148 145 | CLK_ENABLE_ON_INIT), 149 146 }; 150 147 151 - enum { MSTP97, MSTP96, MSTP95, MSTP94, 148 + enum { 149 + MSTP107, MSTP106, MSTP105, MSTP104, MSTP103, 150 + MSTP97, MSTP96, MSTP95, MSTP94, 151 + MSTP74, 152 152 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, 153 - MSTP33, MSTP_NR }; 153 + MSTP33, MSTP_NR 154 + }; 154 155 155 156 static struct clk mstp_clks[MSTP_NR] = { 157 + [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */ 158 + [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */ 159 + [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */ 160 + [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */ 161 + [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */ 156 162 [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */ 157 163 [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */ 158 164 [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */ 159 165 [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */ 166 + [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */ 160 167 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ 161 168 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ 162 169 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ ··· 189 176 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 190 177 191 178 /* MSTP clocks */ 179 + CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]), 180 + CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]), 181 + CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]), 182 + CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]), 183 + CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]), 184 + CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]), 185 + CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]), 186 + CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]), 187 + CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]), 188 + CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]), 192 189 CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]), 193 190 CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]), 194 191 CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]), 195 192 CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]), 193 + CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]), 196 194 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]), 197 195 198 196 /* ICK */
+4
arch/arm/mach-shmobile/clock-r8a7778.c
··· 221 221 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ 222 222 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ 223 223 224 + CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a), 225 + CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b), 226 + CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c), 227 + CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk), 224 228 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), 225 229 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]), 226 230 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
+20 -11
arch/arm/mach-shmobile/clock-r8a7790.c
··· 91 91 .ops = &followparent_clk_ops, 92 92 }; 93 93 94 + static struct clk audio_clk_a = { 95 + }; 96 + 97 + static struct clk audio_clk_b = { 98 + }; 99 + 100 + static struct clk audio_clk_c = { 101 + }; 102 + 94 103 /* 95 104 * clock ratio of these clock will be updated 96 105 * on r8a7790_clock_init() ··· 133 124 SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); 134 125 135 126 static struct clk *main_clks[] = { 127 + &audio_clk_a, 128 + &audio_clk_b, 129 + &audio_clk_c, 136 130 &extal_clk, 137 131 &extal_div2_clk, 138 132 &main_clk, ··· 279 267 static struct clk_lookup lookups[] = { 280 268 281 269 /* main clocks */ 270 + CLKDEV_CON_ID("audio_clk_a", &audio_clk_a), 271 + CLKDEV_CON_ID("audio_clk_b", &audio_clk_b), 272 + CLKDEV_CON_ID("audio_clk_c", &audio_clk_c), 273 + CLKDEV_CON_ID("audio_clk_internal", &m2_clk), 282 274 CLKDEV_CON_ID("extal", &extal_clk), 283 275 CLKDEV_CON_ID("extal_div2", &extal_div2_clk), 284 276 CLKDEV_CON_ID("main", &main_clk), ··· 328 312 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), 329 313 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), 330 314 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), 331 - CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), 332 315 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]), 333 - CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), 334 316 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]), 335 - CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), 336 317 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]), 337 - CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), 338 318 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]), 339 319 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), 340 320 CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]), 341 321 CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]), 342 322 CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]), 343 323 CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]), 344 - CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 345 324 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 346 325 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]), 347 326 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]), 348 - CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), 349 327 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 350 - CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), 351 328 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 352 - CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), 353 329 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), 354 - CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]), 355 330 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), 356 - CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]), 357 331 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), 358 - CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]), 359 332 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 360 333 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 361 334 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), ··· 362 357 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), 363 358 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), 364 359 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), 360 + CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a), 361 + CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b), 362 + CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c), 363 + CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk), 365 364 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]), 366 365 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]), 367 366 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
+60 -2
arch/arm/mach-shmobile/clock-r8a7791.c
··· 61 61 62 62 #define MSTPSR1 IOMEM(0xe6150038) 63 63 #define MSTPSR2 IOMEM(0xe6150040) 64 + #define MSTPSR3 IOMEM(0xe6150048) 64 65 #define MSTPSR5 IOMEM(0xe615003c) 65 66 #define MSTPSR7 IOMEM(0xe61501c4) 66 67 #define MSTPSR8 IOMEM(0xe61509a0) ··· 70 69 71 70 #define MODEMR 0xE6160060 72 71 #define SDCKCR 0xE6150074 73 - #define SD2CKCR 0xE6150078 74 - #define SD3CKCR 0xE615007C 72 + #define SD1CKCR 0xE6150078 73 + #define SD2CKCR 0xE615026c 75 74 #define MMC0CKCR 0xE6150240 76 75 #define MMC1CKCR 0xE6150244 77 76 #define SSPCKCR 0xE6150248 ··· 102 101 */ 103 102 SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1); 104 103 SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1); 104 + SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1); 105 105 106 106 /* fixed ratio clock */ 107 107 SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2); ··· 126 124 &pll3_clk, 127 125 &hp_clk, 128 126 &p_clk, 127 + &qspi_clk, 129 128 &rclk_clk, 130 129 &mp_clk, 131 130 &cp_clk, ··· 135 132 &zs_clk, 136 133 }; 137 134 135 + /* SDHI (DIV4) clock */ 136 + static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 }; 137 + 138 + static struct clk_div_mult_table div4_div_mult_table = { 139 + .divisors = divisors, 140 + .nr_divisors = ARRAY_SIZE(divisors), 141 + }; 142 + 143 + static struct clk_div4_table div4_table = { 144 + .div_mult_table = &div4_div_mult_table, 145 + }; 146 + 147 + enum { 148 + DIV4_SDH, DIV4_SD0, 149 + DIV4_NR 150 + }; 151 + 152 + static struct clk div4_clks[DIV4_NR] = { 153 + [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 154 + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 155 + }; 156 + 157 + /* DIV6 clocks */ 158 + enum { 159 + DIV6_SD1, DIV6_SD2, 160 + DIV6_NR 161 + }; 162 + 163 + static struct clk div6_clks[DIV6_NR] = { 164 + [DIV6_SD1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0), 165 + [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), 166 + }; 167 + 138 168 /* MSTP */ 139 169 enum { 140 170 MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925, 171 + MSTP917, 141 172 MSTP815, MSTP814, 142 173 MSTP813, 143 174 MSTP811, MSTP810, MSTP809, 144 175 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, 145 176 MSTP719, MSTP718, MSTP715, MSTP714, 146 177 MSTP522, 178 + MSTP314, MSTP312, MSTP311, 147 179 MSTP216, MSTP207, MSTP206, 148 180 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, 149 181 MSTP124, ··· 192 154 [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ 193 155 [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */ 194 156 [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */ 157 + [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */ 195 158 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */ 196 159 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */ 197 160 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */ ··· 209 170 [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */ 210 171 [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */ 211 172 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */ 173 + [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */ 174 + [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */ 175 + [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */ 212 176 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */ 213 177 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */ 214 178 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */ ··· 237 195 CLKDEV_CON_ID("zs", &zs_clk), 238 196 CLKDEV_CON_ID("hp", &hp_clk), 239 197 CLKDEV_CON_ID("p", &p_clk), 198 + CLKDEV_CON_ID("qspi", &qspi_clk), 240 199 CLKDEV_CON_ID("rclk", &rclk_clk), 241 200 CLKDEV_CON_ID("mp", &mp_clk), 242 201 CLKDEV_CON_ID("cp", &cp_clk), ··· 262 219 CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */ 263 220 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ 264 221 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ 222 + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 223 + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]), 224 + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), 265 225 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 226 + CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), 266 227 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 267 228 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 268 229 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]), ··· 318 271 break; 319 272 } 320 273 274 + if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2)) 275 + SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); 276 + else 277 + SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); 278 + 321 279 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 322 280 ret = clk_register(main_clks[k]); 281 + 282 + if (!ret) 283 + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 284 + 285 + if (!ret) 286 + ret = sh_clk_div6_register(div6_clks, DIV6_NR); 323 287 324 288 if (!ret) 325 289 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+2 -2
include/dt-bindings/clock/r8a7790-clock.h
··· 46 46 #define R8A7790_CLK_MSIOF1 8 47 47 #define R8A7790_CLK_MSIOF3 15 48 48 #define R8A7790_CLK_SCIFB2 16 49 - #define R8A7790_CLK_SYS_DMAC0 18 50 - #define R8A7790_CLK_SYS_DMAC1 19 49 + #define R8A7790_CLK_SYS_DMAC1 18 50 + #define R8A7790_CLK_SYS_DMAC0 19 51 51 52 52 /* MSTP3 */ 53 53 #define R8A7790_CLK_TPU0 4