tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into clk-starfive
Pull Starfive clk driver updates from Conor Dooley:
- Initial JH7110 clk/reset support
A rake of patches, initially worked on by Emil & later picked up by Hal
that add support for the sys/aon clock & reset controllers on StarFive's
JH7110 SoC.
This SoC is largely similar to the existing JH7100, so a bunch of
refactoring is done to share as many bits as possible between the two.
What's here (plus the already applied pinctrl bits) should be sufficient
to boot a basic initramfs.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: generalise StarFive clk/reset entries
reset: starfive: Add StarFive JH7110 reset driver
clk: starfive: Add StarFive JH7110 always-on clock driver
clk: starfive: Add StarFive JH7110 system clock driver
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: starfive: Extract the common JH71X0 reset code
reset: starfive: Factor out common JH71X0 reset code
reset: Create subdirectory for StarFive drivers
reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
clk: starfive: Factor out common JH7100 and JH7110 code
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
+2297
-864
+107
Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
+107
Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: StarFive JH7110 Always-On Clock and Reset Generator
8
+
9
+
maintainers:
10
+
- Emil Renner Berthing <kernel@esmil.dk>
11
+
12
+
properties:
13
+
compatible:
14
+
const: starfive,jh7110-aoncrg
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
oneOf:
21
+
- items:
22
+
- description: Main Oscillator (24 MHz)
23
+
- description: GMAC0 RMII reference or GMAC0 RGMII RX
24
+
- description: STG AXI/AHB
25
+
- description: APB Bus
26
+
- description: GMAC0 GTX
27
+
28
+
- items:
29
+
- description: Main Oscillator (24 MHz)
30
+
- description: GMAC0 RMII reference or GMAC0 RGMII RX
31
+
- description: STG AXI/AHB or GMAC0 RGMII RX
32
+
- description: APB Bus or STG AXI/AHB
33
+
- description: GMAC0 GTX or APB Bus
34
+
- description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
35
+
36
+
- items:
37
+
- description: Main Oscillator (24 MHz)
38
+
- description: GMAC0 RMII reference
39
+
- description: GMAC0 RGMII RX
40
+
- description: STG AXI/AHB
41
+
- description: APB Bus
42
+
- description: GMAC0 GTX
43
+
- description: RTC Oscillator (32.768 kHz)
44
+
45
+
clock-names:
46
+
oneOf:
47
+
- minItems: 5
48
+
items:
49
+
- const: osc
50
+
- enum:
51
+
- gmac0_rmii_refin
52
+
- gmac0_rgmii_rxin
53
+
- const: stg_axiahb
54
+
- const: apb_bus
55
+
- const: gmac0_gtxclk
56
+
- const: rtc_osc
57
+
58
+
- minItems: 6
59
+
items:
60
+
- const: osc
61
+
- const: gmac0_rmii_refin
62
+
- const: gmac0_rgmii_rxin
63
+
- const: stg_axiahb
64
+
- const: apb_bus
65
+
- const: gmac0_gtxclk
66
+
- const: rtc_osc
67
+
68
+
'#clock-cells':
69
+
const: 1
70
+
description:
71
+
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
72
+
73
+
'#reset-cells':
74
+
const: 1
75
+
description:
76
+
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
77
+
78
+
required:
79
+
- compatible
80
+
- reg
81
+
- clocks
82
+
- clock-names
83
+
- '#clock-cells'
84
+
- '#reset-cells'
85
+
86
+
additionalProperties: false
87
+
88
+
examples:
89
+
- |
90
+
#include <dt-bindings/clock/starfive,jh7110-crg.h>
91
+
92
+
clock-controller@17000000 {
93
+
compatible = "starfive,jh7110-aoncrg";
94
+
reg = <0x17000000 0x10000>;
95
+
clocks = <&osc>, <&gmac0_rmii_refin>,
96
+
<&gmac0_rgmii_rxin>,
97
+
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
98
+
<&syscrg JH7110_SYSCLK_APB_BUS>,
99
+
<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
100
+
<&rtc_osc>;
101
+
clock-names = "osc", "gmac0_rmii_refin",
102
+
"gmac0_rgmii_rxin", "stg_axiahb",
103
+
"apb_bus", "gmac0_gtxclk",
104
+
"rtc_osc";
105
+
#clock-cells = <1>;
106
+
#reset-cells = <1>;
107
+
};
+104
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
+104
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: StarFive JH7110 System Clock and Reset Generator
8
+
9
+
maintainers:
10
+
- Emil Renner Berthing <kernel@esmil.dk>
11
+
12
+
properties:
13
+
compatible:
14
+
const: starfive,jh7110-syscrg
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
oneOf:
21
+
- items:
22
+
- description: Main Oscillator (24 MHz)
23
+
- description: GMAC1 RMII reference or GMAC1 RGMII RX
24
+
- description: External I2S TX bit clock
25
+
- description: External I2S TX left/right channel clock
26
+
- description: External I2S RX bit clock
27
+
- description: External I2S RX left/right channel clock
28
+
- description: External TDM clock
29
+
- description: External audio master clock
30
+
31
+
- items:
32
+
- description: Main Oscillator (24 MHz)
33
+
- description: GMAC1 RMII reference
34
+
- description: GMAC1 RGMII RX
35
+
- description: External I2S TX bit clock
36
+
- description: External I2S TX left/right channel clock
37
+
- description: External I2S RX bit clock
38
+
- description: External I2S RX left/right channel clock
39
+
- description: External TDM clock
40
+
- description: External audio master clock
41
+
42
+
clock-names:
43
+
oneOf:
44
+
- items:
45
+
- const: osc
46
+
- enum:
47
+
- gmac1_rmii_refin
48
+
- gmac1_rgmii_rxin
49
+
- const: i2stx_bclk_ext
50
+
- const: i2stx_lrck_ext
51
+
- const: i2srx_bclk_ext
52
+
- const: i2srx_lrck_ext
53
+
- const: tdm_ext
54
+
- const: mclk_ext
55
+
56
+
- items:
57
+
- const: osc
58
+
- const: gmac1_rmii_refin
59
+
- const: gmac1_rgmii_rxin
60
+
- const: i2stx_bclk_ext
61
+
- const: i2stx_lrck_ext
62
+
- const: i2srx_bclk_ext
63
+
- const: i2srx_lrck_ext
64
+
- const: tdm_ext
65
+
- const: mclk_ext
66
+
67
+
'#clock-cells':
68
+
const: 1
69
+
description:
70
+
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
71
+
72
+
'#reset-cells':
73
+
const: 1
74
+
description:
75
+
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
76
+
77
+
required:
78
+
- compatible
79
+
- reg
80
+
- clocks
81
+
- clock-names
82
+
- '#clock-cells'
83
+
- '#reset-cells'
84
+
85
+
additionalProperties: false
86
+
87
+
examples:
88
+
- |
89
+
clock-controller@13020000 {
90
+
compatible = "starfive,jh7110-syscrg";
91
+
reg = <0x13020000 0x10000>;
92
+
clocks = <&osc>, <&gmac1_rmii_refin>,
93
+
<&gmac1_rgmii_rxin>,
94
+
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
95
+
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
96
+
<&tdm_ext>, <&mclk_ext>;
97
+
clock-names = "osc", "gmac1_rmii_refin",
98
+
"gmac1_rgmii_rxin",
99
+
"i2stx_bclk_ext", "i2stx_lrck_ext",
100
+
"i2srx_bclk_ext", "i2srx_lrck_ext",
101
+
"tdm_ext", "mclk_ext";
102
+
#clock-cells = <1>;
103
+
#reset-cells = <1>;
104
+
};
+12
-10
MAINTAINERS
+12
-10
MAINTAINERS
···
19907
19907
S: Maintained
19908
19908
F: arch/riscv/boot/dts/starfive/
19909
19909
19910
-
STARFIVE JH7100 CLOCK DRIVERS
19911
-
M: Emil Renner Berthing <kernel@esmil.dk>
19912
-
S: Maintained
19913
-
F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
19914
-
F: drivers/clk/starfive/clk-starfive-jh7100*
19915
-
F: include/dt-bindings/clock/starfive-jh7100*.h
19916
-
19917
19910
STARFIVE JH7110 MMC/SD/SDIO DRIVER
19918
19911
M: William Qiu <william.qiu@starfivetech.com>
19919
19912
S: Supported
19920
19913
F: Documentation/devicetree/bindings/mmc/starfive*
19921
19914
F: drivers/mmc/host/dw_mmc-starfive.c
19915
+
19916
+
STARFIVE JH71X0 CLOCK DRIVERS
19917
+
M: Emil Renner Berthing <kernel@esmil.dk>
19918
+
M: Hal Feng <hal.feng@starfivetech.com>
19919
+
S: Maintained
19920
+
F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
19921
+
F: drivers/clk/starfive/clk-starfive-jh71*
19922
+
F: include/dt-bindings/clock/starfive?jh71*.h
19922
19923
19923
19924
STARFIVE JH71X0 PINCTRL DRIVERS
19924
19925
M: Emil Renner Berthing <kernel@esmil.dk>
···
19931
19930
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
19932
19931
F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
19933
19932
19934
-
STARFIVE JH7100 RESET CONTROLLER DRIVER
19933
+
STARFIVE JH71X0 RESET CONTROLLER DRIVERS
19935
19934
M: Emil Renner Berthing <kernel@esmil.dk>
19935
+
M: Hal Feng <hal.feng@starfivetech.com>
19936
19936
S: Maintained
19937
19937
F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
19938
-
F: drivers/reset/reset-starfive-jh7100.c
19939
-
F: include/dt-bindings/reset/starfive-jh7100.h
19938
+
F: drivers/reset/starfive/reset-starfive-jh71*
19939
+
F: include/dt-bindings/reset/starfive?jh71*.h
19940
19940
19941
19941
STARFIVE JH71XX PMU CONTROLLER DRIVER
19942
19942
M: Walker Chen <walker.chen@starfivetech.com>
+1
-1
drivers/clk/Makefile
+1
-1
drivers/clk/Makefile
+30
-3
drivers/clk/starfive/Kconfig
+30
-3
drivers/clk/starfive/Kconfig
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
3
+
config CLK_STARFIVE_JH71X0
4
+
bool
5
+
3
6
config CLK_STARFIVE_JH7100
4
7
bool "StarFive JH7100 clock support"
5
-
depends on SOC_STARFIVE || COMPILE_TEST
6
-
default SOC_STARFIVE
8
+
depends on ARCH_STARFIVE || COMPILE_TEST
9
+
select CLK_STARFIVE_JH71X0
10
+
default ARCH_STARFIVE
7
11
help
8
12
Say yes here to support the clock controller on the StarFive JH7100
9
13
SoC.
···
15
11
config CLK_STARFIVE_JH7100_AUDIO
16
12
tristate "StarFive JH7100 audio clock support"
17
13
depends on CLK_STARFIVE_JH7100
18
-
default m if SOC_STARFIVE
14
+
select CLK_STARFIVE_JH71X0
15
+
default m if ARCH_STARFIVE
19
16
help
20
17
Say Y or M here to support the audio clocks on the StarFive JH7100
21
18
SoC.
19
+
20
+
config CLK_STARFIVE_JH7110_SYS
21
+
bool "StarFive JH7110 system clock support"
22
+
depends on ARCH_STARFIVE || COMPILE_TEST
23
+
select AUXILIARY_BUS
24
+
select CLK_STARFIVE_JH71X0
25
+
select RESET_STARFIVE_JH7110
26
+
default ARCH_STARFIVE
27
+
help
28
+
Say yes here to support the system clock controller on the
29
+
StarFive JH7110 SoC.
30
+
31
+
config CLK_STARFIVE_JH7110_AON
32
+
tristate "StarFive JH7110 always-on clock support"
33
+
depends on CLK_STARFIVE_JH7110_SYS
34
+
select AUXILIARY_BUS
35
+
select CLK_STARFIVE_JH71X0
36
+
select RESET_STARFIVE_JH7110
37
+
default m if ARCH_STARFIVE
38
+
help
39
+
Say yes here to support the always-on clock controller on the
40
+
StarFive JH7110 SoC.
+5
-1
drivers/clk/starfive/Makefile
+5
-1
drivers/clk/starfive/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
-
# StarFive Clock
2
+
obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
3
+
3
4
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
4
5
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
6
+
7
+
obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
8
+
obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
+37
-37
drivers/clk/starfive/clk-starfive-jh7100-audio.c
+37
-37
drivers/clk/starfive/clk-starfive-jh7100-audio.c
···
16
16
17
17
#include <dt-bindings/clock/starfive-jh7100-audio.h>
18
18
19
-
#include "clk-starfive-jh7100.h"
19
+
#include "clk-starfive-jh71x0.h"
20
20
21
21
/* external clocks */
22
22
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
···
28
28
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
29
29
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
30
30
31
-
static const struct jh7100_clk_data jh7100_audclk_data[] = {
32
-
JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
31
+
static const struct jh71x0_clk_data jh7100_audclk_data[] = {
32
+
JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
33
33
JH7100_AUDCLK_AUDIO_SRC,
34
34
JH7100_AUDCLK_AUDIO_12288),
35
-
JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
35
+
JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
36
36
JH7100_AUDCLK_AUDIO_SRC,
37
37
JH7100_AUDCLK_AUDIO_12288),
38
-
JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
39
-
JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
38
+
JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
39
+
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
40
40
JH7100_AUDCLK_ADC_MCLK,
41
41
JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
42
-
JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
43
-
JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
42
+
JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
43
+
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
44
44
JH7100_AUDCLK_I2SADC_BCLK_N,
45
45
JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
46
46
JH7100_AUDCLK_I2SADC_BCLK),
47
-
JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
48
-
JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
47
+
JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
48
+
JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
49
49
JH7100_AUDCLK_AUDIO_SRC,
50
50
JH7100_AUDCLK_AUDIO_12288),
51
-
JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
52
-
JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
51
+
JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
52
+
JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
53
53
JH7100_AUDCLK_AUDIO_SRC,
54
54
JH7100_AUDCLK_AUDIO_12288),
55
-
JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
56
-
JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
57
-
JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
55
+
JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
56
+
JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
57
+
JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
58
58
JH7100_AUDCLK_AUDIO_SRC,
59
59
JH7100_AUDCLK_AUDIO_12288),
60
-
JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
61
-
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
60
+
JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
61
+
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
62
62
JH7100_AUDCLK_DAC_MCLK,
63
63
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
64
-
JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
65
-
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
64
+
JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
65
+
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
66
66
JH7100_AUDCLK_I2S1_MCLK,
67
67
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
68
-
JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
69
-
JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
68
+
JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
69
+
JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
70
70
JH7100_AUDCLK_I2S1_MCLK,
71
71
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
72
-
JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
73
-
JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
72
+
JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
73
+
JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
74
74
JH7100_AUDCLK_I2S1_BCLK_N,
75
75
JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
76
-
JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
77
-
JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
78
-
JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
79
-
JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
80
-
JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
81
-
JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
82
-
JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
83
-
JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
76
+
JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
77
+
JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
78
+
JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
79
+
JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
80
+
JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
81
+
JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
82
+
JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
83
+
JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
84
84
JH7100_AUDCLK_VAD_INTMEM,
85
85
JH7100_AUDCLK_AUDIO_12288),
86
86
};
87
87
88
88
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
89
89
{
90
-
struct jh7100_clk_priv *priv = data;
90
+
struct jh71x0_clk_priv *priv = data;
91
91
unsigned int idx = clkspec->args[0];
92
92
93
93
if (idx < JH7100_AUDCLK_END)
···
98
98
99
99
static int jh7100_audclk_probe(struct platform_device *pdev)
100
100
{
101
-
struct jh7100_clk_priv *priv;
101
+
struct jh71x0_clk_priv *priv;
102
102
unsigned int idx;
103
103
int ret;
104
104
···
117
117
struct clk_parent_data parents[4] = {};
118
118
struct clk_init_data init = {
119
119
.name = jh7100_audclk_data[idx].name,
120
-
.ops = starfive_jh7100_clk_ops(max),
120
+
.ops = starfive_jh71x0_clk_ops(max),
121
121
.parent_data = parents,
122
-
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
122
+
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
123
123
.flags = jh7100_audclk_data[idx].flags,
124
124
};
125
-
struct jh7100_clk *clk = &priv->reg[idx];
125
+
struct jh71x0_clk *clk = &priv->reg[idx];
126
126
unsigned int i;
127
127
128
128
for (i = 0; i < init.num_parents; i++) {
···
140
140
141
141
clk->hw.init = &init;
142
142
clk->idx = idx;
143
-
clk->max_div = max & JH7100_CLK_DIV_MASK;
143
+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
144
144
145
145
ret = devm_clk_hw_register(priv->dev, &clk->hw);
146
146
if (ret)
+197
-519
drivers/clk/starfive/clk-starfive-jh7100.c
+197
-519
drivers/clk/starfive/clk-starfive-jh7100.c
···
7
7
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
8
8
*/
9
9
10
-
#include <linux/bits.h>
11
10
#include <linux/clk-provider.h>
12
-
#include <linux/debugfs.h>
13
11
#include <linux/device.h>
14
12
#include <linux/init.h>
15
-
#include <linux/io.h>
16
-
#include <linux/kernel.h>
17
13
#include <linux/mod_devicetable.h>
18
-
#include <linux/module.h>
19
14
#include <linux/platform_device.h>
20
15
21
16
#include <dt-bindings/clock/starfive-jh7100.h>
22
17
23
-
#include "clk-starfive-jh7100.h"
18
+
#include "clk-starfive-jh71x0.h"
24
19
25
20
/* external clocks */
26
21
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
···
23
28
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
24
29
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
25
30
26
-
static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
27
-
JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
31
+
static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
32
+
JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
28
33
JH7100_CLK_OSC_SYS,
29
34
JH7100_CLK_PLL0_OUT,
30
35
JH7100_CLK_PLL1_OUT,
31
36
JH7100_CLK_PLL2_OUT),
32
-
JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
37
+
JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
33
38
JH7100_CLK_OSC_SYS,
34
39
JH7100_CLK_PLL1_OUT,
35
40
JH7100_CLK_PLL2_OUT),
36
-
JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
41
+
JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
37
42
JH7100_CLK_OSC_SYS,
38
43
JH7100_CLK_PLL0_OUT,
39
44
JH7100_CLK_PLL1_OUT,
40
45
JH7100_CLK_PLL2_OUT),
41
-
JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
46
+
JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
42
47
JH7100_CLK_OSC_SYS,
43
48
JH7100_CLK_PLL0_OUT,
44
49
JH7100_CLK_PLL2_OUT),
45
-
JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
50
+
JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
46
51
JH7100_CLK_OSC_SYS,
47
52
JH7100_CLK_PLL0_OUT),
48
-
JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
53
+
JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
49
54
JH7100_CLK_OSC_SYS,
50
55
JH7100_CLK_PLL2_OUT),
51
-
JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
56
+
JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
52
57
JH7100_CLK_OSC_SYS,
53
58
JH7100_CLK_PLL1_OUT,
54
59
JH7100_CLK_PLL2_OUT),
55
-
JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
60
+
JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
56
61
JH7100_CLK_OSC_AUD,
57
62
JH7100_CLK_PLL0_OUT,
58
63
JH7100_CLK_PLL2_OUT),
59
-
JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
60
-
JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
64
+
JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
65
+
JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
61
66
JH7100_CLK_OSC_SYS,
62
67
JH7100_CLK_PLL1_OUT,
63
68
JH7100_CLK_PLL2_OUT),
64
-
JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
69
+
JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
65
70
JH7100_CLK_OSC_SYS,
66
71
JH7100_CLK_PLL0_OUT,
67
72
JH7100_CLK_PLL1_OUT),
68
-
JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
73
+
JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
69
74
JH7100_CLK_OSC_AUD,
70
75
JH7100_CLK_PLL0_OUT,
71
76
JH7100_CLK_PLL2_OUT),
72
-
JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
73
-
JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
74
-
JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
75
-
JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
76
-
JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
77
-
JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
78
-
JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
79
-
JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
77
+
JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
78
+
JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
79
+
JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
80
+
JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
81
+
JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
82
+
JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
83
+
JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
84
+
JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
80
85
JH7100_CLK_OSC_SYS,
81
86
JH7100_CLK_OSC_AUD),
82
-
JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
83
-
JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
84
-
JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
85
-
JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
86
-
JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
87
-
JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
88
-
JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
89
-
JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
90
-
JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
91
-
JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
92
-
JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
93
-
JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
94
-
JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
95
-
JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
96
-
JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
97
-
JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
98
-
JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
99
-
JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
100
-
JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
101
-
JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
102
-
JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
103
-
JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
104
-
JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
105
-
JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
106
-
JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
107
-
JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
108
-
JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
109
-
JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
110
-
JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
111
-
JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
112
-
JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
113
-
JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
114
-
JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
115
-
JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
116
-
JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
117
-
JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
118
-
JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
119
-
JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
120
-
JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
121
-
JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
122
-
JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
123
-
JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
124
-
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
125
-
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
126
-
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
127
-
JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
128
-
JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
87
+
JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
88
+
JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
89
+
JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
90
+
JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
91
+
JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
92
+
JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
93
+
JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
94
+
JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
95
+
JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
96
+
JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
97
+
JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
98
+
JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
99
+
JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
100
+
JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
101
+
JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
102
+
JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
103
+
JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
104
+
JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
105
+
JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
106
+
JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
107
+
JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
108
+
JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
109
+
JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
110
+
JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
111
+
JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
112
+
JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
113
+
JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
114
+
JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
115
+
JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
116
+
JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
117
+
JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
118
+
JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
119
+
JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
120
+
JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
121
+
JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
122
+
JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
123
+
JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
124
+
JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
125
+
JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
126
+
JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
127
+
JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
128
+
JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
129
+
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
130
+
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
131
+
JH7100_CLK_DDRPLL_DIV2),
132
+
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
133
+
JH7100_CLK_DDRPLL_DIV4),
134
+
JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
135
+
JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
129
136
JH7100_CLK_DDROSC_DIV2,
130
137
JH7100_CLK_DDRPLL_DIV2,
131
138
JH7100_CLK_DDRPLL_DIV4,
132
139
JH7100_CLK_DDRPLL_DIV8),
133
-
JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
140
+
JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
134
141
JH7100_CLK_DDROSC_DIV2,
135
142
JH7100_CLK_DDRPLL_DIV2,
136
143
JH7100_CLK_DDRPLL_DIV4,
137
144
JH7100_CLK_DDRPLL_DIV8),
138
-
JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
139
-
JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
140
-
JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
141
-
JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
142
-
JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
143
-
JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
145
+
JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
146
+
JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
147
+
JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
148
+
JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
149
+
JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
150
+
JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
144
151
JH7100_CLK_CPU_AXI,
145
152
JH7100_CLK_NNEBUS_SRC1),
146
-
JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
147
-
JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
148
-
JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
149
-
JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
150
-
JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
151
-
JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
152
-
JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
153
-
JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
154
-
JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
155
-
JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
156
-
JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
157
-
JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
158
-
JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
159
-
JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
160
-
JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
161
-
JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
162
-
JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
163
-
JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
164
-
JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
165
-
JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
166
-
JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
153
+
JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
154
+
JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
155
+
JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
156
+
JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
157
+
JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
158
+
JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
159
+
JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
160
+
JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
161
+
JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
162
+
JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
163
+
JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
164
+
JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
165
+
JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
166
+
JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
167
+
JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
168
+
JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
169
+
JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
170
+
JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
171
+
JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
172
+
JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
173
+
JH7100_CLK_USBPHY_ROOTDIV),
174
+
JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
167
175
JH7100_CLK_OSC_SYS,
168
176
JH7100_CLK_USBPHY_PLLDIV25M),
169
-
JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
170
-
JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
171
-
JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
172
-
JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
173
-
JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
174
-
JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
175
-
JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
176
-
JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
177
-
JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
178
-
JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
179
-
JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
180
-
JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
181
-
JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
182
-
JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
183
-
JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
184
-
JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
185
-
JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
186
-
JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
187
-
JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
188
-
JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
189
-
JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
190
-
JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
191
-
JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
192
-
JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
193
-
JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
194
-
JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
195
-
JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
196
-
JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
197
-
JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
198
-
JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
199
-
JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
200
-
JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
177
+
JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
178
+
JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
179
+
JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
180
+
JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
181
+
JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
182
+
JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
183
+
JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
184
+
JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
185
+
JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
186
+
JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
187
+
JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
188
+
JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
189
+
JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
190
+
JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
191
+
JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
192
+
JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
193
+
JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
194
+
JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
195
+
JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
196
+
JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
197
+
JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
198
+
JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
199
+
JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
200
+
JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
201
+
JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
202
+
JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
203
+
JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
204
+
JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
205
+
JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
206
+
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
207
+
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
208
+
JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
201
209
JH7100_CLK_GMAC_GTX,
202
210
JH7100_CLK_GMAC_TX_INV,
203
211
JH7100_CLK_GMAC_RMII_TX),
204
-
JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
205
-
JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
212
+
JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
213
+
JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
206
214
JH7100_CLK_GMAC_GR_MII_RX,
207
215
JH7100_CLK_GMAC_RMII_RX),
208
-
JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
209
-
JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
210
-
JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
211
-
JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
212
-
JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
213
-
JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
214
-
JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
215
-
JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
216
-
JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
217
-
JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
218
-
JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
219
-
JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
220
-
JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
221
-
JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
222
-
JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
223
-
JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
224
-
JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
225
-
JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
226
-
JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
227
-
JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
228
-
JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
229
-
JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
230
-
JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
231
-
JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
232
-
JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
233
-
JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
234
-
JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
235
-
JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
236
-
JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
237
-
JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
238
-
JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
239
-
JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
240
-
JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
241
-
JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
242
-
JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
243
-
JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
244
-
JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
245
-
JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
246
-
JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
247
-
JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
248
-
JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
249
-
JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
250
-
JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
251
-
JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
252
-
JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
253
-
JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
254
-
JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
255
-
JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
256
-
JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
257
-
JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
258
-
JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
259
-
JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
260
-
JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
261
-
JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
262
-
JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
263
-
JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
264
-
JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
216
+
JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
217
+
JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
218
+
JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
219
+
JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
220
+
JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
221
+
JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
222
+
JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
223
+
JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
224
+
JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
225
+
JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
226
+
JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
227
+
JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
228
+
JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
229
+
JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
230
+
JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
231
+
JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
232
+
JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
233
+
JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
234
+
JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
235
+
JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
236
+
JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
237
+
JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
238
+
JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
239
+
JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
240
+
JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
241
+
JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
242
+
JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
243
+
JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
244
+
JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
245
+
JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
246
+
JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
247
+
JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
248
+
JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
249
+
JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
250
+
JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
251
+
JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
252
+
JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
253
+
JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
254
+
JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
255
+
JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
256
+
JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
257
+
JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
258
+
JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
259
+
JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
260
+
JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
261
+
JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
262
+
JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
263
+
JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
264
+
JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
265
+
JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
266
+
JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
267
+
JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
268
+
JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
269
+
JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
270
+
JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
271
+
JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
272
+
JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
265
273
};
266
-
267
-
static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
268
-
{
269
-
return container_of(hw, struct jh7100_clk, hw);
270
-
}
271
-
272
-
static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
273
-
{
274
-
return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
275
-
}
276
-
277
-
static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
278
-
{
279
-
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
280
-
void __iomem *reg = priv->base + 4 * clk->idx;
281
-
282
-
return readl_relaxed(reg);
283
-
}
284
-
285
-
static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
286
-
{
287
-
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
288
-
void __iomem *reg = priv->base + 4 * clk->idx;
289
-
unsigned long flags;
290
-
291
-
spin_lock_irqsave(&priv->rmw_lock, flags);
292
-
value |= readl_relaxed(reg) & ~mask;
293
-
writel_relaxed(value, reg);
294
-
spin_unlock_irqrestore(&priv->rmw_lock, flags);
295
-
}
296
-
297
-
static int jh7100_clk_enable(struct clk_hw *hw)
298
-
{
299
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
300
-
301
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
302
-
return 0;
303
-
}
304
-
305
-
static void jh7100_clk_disable(struct clk_hw *hw)
306
-
{
307
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
308
-
309
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
310
-
}
311
-
312
-
static int jh7100_clk_is_enabled(struct clk_hw *hw)
313
-
{
314
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
315
-
316
-
return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
317
-
}
318
-
319
-
static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
320
-
unsigned long parent_rate)
321
-
{
322
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
323
-
u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
324
-
325
-
return div ? parent_rate / div : 0;
326
-
}
327
-
328
-
static int jh7100_clk_determine_rate(struct clk_hw *hw,
329
-
struct clk_rate_request *req)
330
-
{
331
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
332
-
unsigned long parent = req->best_parent_rate;
333
-
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
334
-
unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
335
-
unsigned long result = parent / div;
336
-
337
-
/*
338
-
* we want the result clamped by min_rate and max_rate if possible:
339
-
* case 1: div hits the max divider value, which means it's less than
340
-
* parent / rate, so the result is greater than rate and min_rate in
341
-
* particular. we can't do anything about result > max_rate because the
342
-
* divider doesn't go any further.
343
-
* case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
344
-
* always lower or equal to rate and max_rate. however the result may
345
-
* turn out lower than min_rate, but then the next higher rate is fine:
346
-
* div - 1 = ceil(parent / rate) - 1 < parent / rate
347
-
* and thus
348
-
* min_rate <= rate < parent / (div - 1)
349
-
*/
350
-
if (result < req->min_rate && div > 1)
351
-
result = parent / (div - 1);
352
-
353
-
req->rate = result;
354
-
return 0;
355
-
}
356
-
357
-
static int jh7100_clk_set_rate(struct clk_hw *hw,
358
-
unsigned long rate,
359
-
unsigned long parent_rate)
360
-
{
361
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
362
-
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
363
-
1UL, (unsigned long)clk->max_div);
364
-
365
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
366
-
return 0;
367
-
}
368
-
369
-
static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
370
-
unsigned long parent_rate)
371
-
{
372
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
373
-
u32 reg = jh7100_clk_reg_get(clk);
374
-
unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
375
-
((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
376
-
377
-
return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
378
-
}
379
-
380
-
static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
381
-
struct clk_rate_request *req)
382
-
{
383
-
unsigned long parent100 = 100 * req->best_parent_rate;
384
-
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
385
-
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
386
-
JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
387
-
unsigned long result = parent100 / div100;
388
-
389
-
/* clamp the result as in jh7100_clk_determine_rate() above */
390
-
if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
391
-
result = parent100 / (div100 + 1);
392
-
if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
393
-
result = parent100 / (div100 - 1);
394
-
395
-
req->rate = result;
396
-
return 0;
397
-
}
398
-
399
-
static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
400
-
unsigned long rate,
401
-
unsigned long parent_rate)
402
-
{
403
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
404
-
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
405
-
JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
406
-
u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
407
-
408
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
409
-
return 0;
410
-
}
411
-
412
-
static u8 jh7100_clk_get_parent(struct clk_hw *hw)
413
-
{
414
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
415
-
u32 value = jh7100_clk_reg_get(clk);
416
-
417
-
return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
418
-
}
419
-
420
-
static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
421
-
{
422
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
423
-
u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
424
-
425
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
426
-
return 0;
427
-
}
428
-
429
-
static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
430
-
struct clk_rate_request *req)
431
-
{
432
-
return clk_mux_determine_rate_flags(hw, req, 0);
433
-
}
434
-
435
-
static int jh7100_clk_get_phase(struct clk_hw *hw)
436
-
{
437
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
438
-
u32 value = jh7100_clk_reg_get(clk);
439
-
440
-
return (value & JH7100_CLK_INVERT) ? 180 : 0;
441
-
}
442
-
443
-
static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
444
-
{
445
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
446
-
u32 value;
447
-
448
-
if (degrees == 0)
449
-
value = 0;
450
-
else if (degrees == 180)
451
-
value = JH7100_CLK_INVERT;
452
-
else
453
-
return -EINVAL;
454
-
455
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
456
-
return 0;
457
-
}
458
-
459
-
#ifdef CONFIG_DEBUG_FS
460
-
static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
461
-
{
462
-
static const struct debugfs_reg32 jh7100_clk_reg = {
463
-
.name = "CTRL",
464
-
.offset = 0,
465
-
};
466
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
467
-
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
468
-
struct debugfs_regset32 *regset;
469
-
470
-
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
471
-
if (!regset)
472
-
return;
473
-
474
-
regset->regs = &jh7100_clk_reg;
475
-
regset->nregs = 1;
476
-
regset->base = priv->base + 4 * clk->idx;
477
-
478
-
debugfs_create_regset32("registers", 0400, dentry, regset);
479
-
}
480
-
#else
481
-
#define jh7100_clk_debug_init NULL
482
-
#endif
483
-
484
-
static const struct clk_ops jh7100_clk_gate_ops = {
485
-
.enable = jh7100_clk_enable,
486
-
.disable = jh7100_clk_disable,
487
-
.is_enabled = jh7100_clk_is_enabled,
488
-
.debug_init = jh7100_clk_debug_init,
489
-
};
490
-
491
-
static const struct clk_ops jh7100_clk_div_ops = {
492
-
.recalc_rate = jh7100_clk_recalc_rate,
493
-
.determine_rate = jh7100_clk_determine_rate,
494
-
.set_rate = jh7100_clk_set_rate,
495
-
.debug_init = jh7100_clk_debug_init,
496
-
};
497
-
498
-
static const struct clk_ops jh7100_clk_fdiv_ops = {
499
-
.recalc_rate = jh7100_clk_frac_recalc_rate,
500
-
.determine_rate = jh7100_clk_frac_determine_rate,
501
-
.set_rate = jh7100_clk_frac_set_rate,
502
-
.debug_init = jh7100_clk_debug_init,
503
-
};
504
-
505
-
static const struct clk_ops jh7100_clk_gdiv_ops = {
506
-
.enable = jh7100_clk_enable,
507
-
.disable = jh7100_clk_disable,
508
-
.is_enabled = jh7100_clk_is_enabled,
509
-
.recalc_rate = jh7100_clk_recalc_rate,
510
-
.determine_rate = jh7100_clk_determine_rate,
511
-
.set_rate = jh7100_clk_set_rate,
512
-
.debug_init = jh7100_clk_debug_init,
513
-
};
514
-
515
-
static const struct clk_ops jh7100_clk_mux_ops = {
516
-
.determine_rate = jh7100_clk_mux_determine_rate,
517
-
.set_parent = jh7100_clk_set_parent,
518
-
.get_parent = jh7100_clk_get_parent,
519
-
.debug_init = jh7100_clk_debug_init,
520
-
};
521
-
522
-
static const struct clk_ops jh7100_clk_gmux_ops = {
523
-
.enable = jh7100_clk_enable,
524
-
.disable = jh7100_clk_disable,
525
-
.is_enabled = jh7100_clk_is_enabled,
526
-
.determine_rate = jh7100_clk_mux_determine_rate,
527
-
.set_parent = jh7100_clk_set_parent,
528
-
.get_parent = jh7100_clk_get_parent,
529
-
.debug_init = jh7100_clk_debug_init,
530
-
};
531
-
532
-
static const struct clk_ops jh7100_clk_mdiv_ops = {
533
-
.recalc_rate = jh7100_clk_recalc_rate,
534
-
.determine_rate = jh7100_clk_determine_rate,
535
-
.get_parent = jh7100_clk_get_parent,
536
-
.set_parent = jh7100_clk_set_parent,
537
-
.set_rate = jh7100_clk_set_rate,
538
-
.debug_init = jh7100_clk_debug_init,
539
-
};
540
-
541
-
static const struct clk_ops jh7100_clk_gmd_ops = {
542
-
.enable = jh7100_clk_enable,
543
-
.disable = jh7100_clk_disable,
544
-
.is_enabled = jh7100_clk_is_enabled,
545
-
.recalc_rate = jh7100_clk_recalc_rate,
546
-
.determine_rate = jh7100_clk_determine_rate,
547
-
.get_parent = jh7100_clk_get_parent,
548
-
.set_parent = jh7100_clk_set_parent,
549
-
.set_rate = jh7100_clk_set_rate,
550
-
.debug_init = jh7100_clk_debug_init,
551
-
};
552
-
553
-
static const struct clk_ops jh7100_clk_inv_ops = {
554
-
.get_phase = jh7100_clk_get_phase,
555
-
.set_phase = jh7100_clk_set_phase,
556
-
.debug_init = jh7100_clk_debug_init,
557
-
};
558
-
559
-
const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
560
-
{
561
-
if (max & JH7100_CLK_DIV_MASK) {
562
-
if (max & JH7100_CLK_MUX_MASK) {
563
-
if (max & JH7100_CLK_ENABLE)
564
-
return &jh7100_clk_gmd_ops;
565
-
return &jh7100_clk_mdiv_ops;
566
-
}
567
-
if (max & JH7100_CLK_ENABLE)
568
-
return &jh7100_clk_gdiv_ops;
569
-
if (max == JH7100_CLK_FRAC_MAX)
570
-
return &jh7100_clk_fdiv_ops;
571
-
return &jh7100_clk_div_ops;
572
-
}
573
-
574
-
if (max & JH7100_CLK_MUX_MASK) {
575
-
if (max & JH7100_CLK_ENABLE)
576
-
return &jh7100_clk_gmux_ops;
577
-
return &jh7100_clk_mux_ops;
578
-
}
579
-
580
-
if (max & JH7100_CLK_ENABLE)
581
-
return &jh7100_clk_gate_ops;
582
-
583
-
return &jh7100_clk_inv_ops;
584
-
}
585
-
EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
586
274
587
275
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
588
276
{
589
-
struct jh7100_clk_priv *priv = data;
277
+
struct jh71x0_clk_priv *priv = data;
590
278
unsigned int idx = clkspec->args[0];
591
279
592
280
if (idx < JH7100_CLK_PLL0_OUT)
···
283
605
284
606
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
285
607
{
286
-
struct jh7100_clk_priv *priv;
608
+
struct jh71x0_clk_priv *priv;
287
609
unsigned int idx;
288
610
int ret;
289
611
···
317
639
struct clk_parent_data parents[4] = {};
318
640
struct clk_init_data init = {
319
641
.name = jh7100_clk_data[idx].name,
320
-
.ops = starfive_jh7100_clk_ops(max),
642
+
.ops = starfive_jh71x0_clk_ops(max),
321
643
.parent_data = parents,
322
-
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
644
+
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
323
645
.flags = jh7100_clk_data[idx].flags,
324
646
};
325
-
struct jh7100_clk *clk = &priv->reg[idx];
647
+
struct jh71x0_clk *clk = &priv->reg[idx];
326
648
unsigned int i;
327
649
328
650
for (i = 0; i < init.num_parents; i++) {
···
344
666
345
667
clk->hw.init = &init;
346
668
clk->idx = idx;
347
-
clk->max_div = max & JH7100_CLK_DIV_MASK;
669
+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
348
670
349
671
ret = devm_clk_hw_register(priv->dev, &clk->hw);
350
672
if (ret)
-112
drivers/clk/starfive/clk-starfive-jh7100.h
-112
drivers/clk/starfive/clk-starfive-jh7100.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __CLK_STARFIVE_JH7100_H
3
-
#define __CLK_STARFIVE_JH7100_H
4
-
5
-
#include <linux/bits.h>
6
-
#include <linux/clk-provider.h>
7
-
8
-
/* register fields */
9
-
#define JH7100_CLK_ENABLE BIT(31)
10
-
#define JH7100_CLK_INVERT BIT(30)
11
-
#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
12
-
#define JH7100_CLK_MUX_SHIFT 24
13
-
#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
14
-
#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
15
-
#define JH7100_CLK_FRAC_SHIFT 8
16
-
#define JH7100_CLK_INT_MASK GENMASK(7, 0)
17
-
18
-
/* fractional divider min/max */
19
-
#define JH7100_CLK_FRAC_MIN 100UL
20
-
#define JH7100_CLK_FRAC_MAX 25599UL
21
-
22
-
/* clock data */
23
-
struct jh7100_clk_data {
24
-
const char *name;
25
-
unsigned long flags;
26
-
u32 max;
27
-
u8 parents[4];
28
-
};
29
-
30
-
#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
31
-
.name = _name, \
32
-
.flags = CLK_SET_RATE_PARENT | (_flags), \
33
-
.max = JH7100_CLK_ENABLE, \
34
-
.parents = { [0] = _parent }, \
35
-
}
36
-
37
-
#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
38
-
.name = _name, \
39
-
.flags = 0, \
40
-
.max = _max, \
41
-
.parents = { [0] = _parent }, \
42
-
}
43
-
44
-
#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
45
-
.name = _name, \
46
-
.flags = _flags, \
47
-
.max = JH7100_CLK_ENABLE | (_max), \
48
-
.parents = { [0] = _parent }, \
49
-
}
50
-
51
-
#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
52
-
.name = _name, \
53
-
.flags = 0, \
54
-
.max = JH7100_CLK_FRAC_MAX, \
55
-
.parents = { [0] = _parent }, \
56
-
}
57
-
58
-
#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
59
-
.name = _name, \
60
-
.flags = 0, \
61
-
.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
62
-
.parents = { __VA_ARGS__ }, \
63
-
}
64
-
65
-
#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
66
-
.name = _name, \
67
-
.flags = _flags, \
68
-
.max = JH7100_CLK_ENABLE | \
69
-
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
70
-
.parents = { __VA_ARGS__ }, \
71
-
}
72
-
73
-
#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
74
-
.name = _name, \
75
-
.flags = 0, \
76
-
.max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
77
-
.parents = { __VA_ARGS__ }, \
78
-
}
79
-
80
-
#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
81
-
.name = _name, \
82
-
.flags = _flags, \
83
-
.max = JH7100_CLK_ENABLE | \
84
-
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
85
-
.parents = { __VA_ARGS__ }, \
86
-
}
87
-
88
-
#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
89
-
.name = _name, \
90
-
.flags = CLK_SET_RATE_PARENT, \
91
-
.max = JH7100_CLK_INVERT, \
92
-
.parents = { [0] = _parent }, \
93
-
}
94
-
95
-
struct jh7100_clk {
96
-
struct clk_hw hw;
97
-
unsigned int idx;
98
-
unsigned int max_div;
99
-
};
100
-
101
-
struct jh7100_clk_priv {
102
-
/* protect clk enable and set rate/parent from happening at the same time */
103
-
spinlock_t rmw_lock;
104
-
struct device *dev;
105
-
void __iomem *base;
106
-
struct clk_hw *pll[3];
107
-
struct jh7100_clk reg[];
108
-
};
109
-
110
-
const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
111
-
112
-
#endif
+156
drivers/clk/starfive/clk-starfive-jh7110-aon.c
+156
drivers/clk/starfive/clk-starfive-jh7110-aon.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* StarFive JH7110 Always-On Clock Driver
4
+
*
5
+
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6
+
* Copyright (C) 2022 StarFive Technology Co., Ltd.
7
+
*/
8
+
9
+
#include <linux/clk-provider.h>
10
+
#include <linux/io.h>
11
+
#include <linux/platform_device.h>
12
+
13
+
#include <dt-bindings/clock/starfive,jh7110-crg.h>
14
+
15
+
#include "clk-starfive-jh7110.h"
16
+
17
+
/* external clocks */
18
+
#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
19
+
#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 1)
20
+
#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 2)
21
+
#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 3)
22
+
#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 4)
23
+
#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5)
24
+
#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6)
25
+
26
+
static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
27
+
/* source */
28
+
JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
29
+
JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
30
+
JH7110_AONCLK_OSC_DIV4,
31
+
JH7110_AONCLK_OSC),
32
+
/* gmac0 */
33
+
JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
34
+
JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
35
+
JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
36
+
JH7110_AONCLK_GMAC0_RMII_REFIN),
37
+
JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
38
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
39
+
JH7110_AONCLK_GMAC0_GTXCLK,
40
+
JH7110_AONCLK_GMAC0_RMII_RTX),
41
+
JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
42
+
JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
43
+
JH7110_AONCLK_GMAC0_RGMII_RXIN,
44
+
JH7110_AONCLK_GMAC0_RMII_RTX),
45
+
JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
46
+
/* otpc */
47
+
JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
48
+
/* rtc */
49
+
JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
50
+
JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
51
+
JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
52
+
JH7110_AONCLK_RTC_OSC,
53
+
JH7110_AONCLK_RTC_INTERNAL),
54
+
JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
55
+
};
56
+
57
+
static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
58
+
{
59
+
struct jh71x0_clk_priv *priv = data;
60
+
unsigned int idx = clkspec->args[0];
61
+
62
+
if (idx < JH7110_AONCLK_END)
63
+
return &priv->reg[idx].hw;
64
+
65
+
return ERR_PTR(-EINVAL);
66
+
}
67
+
68
+
static int jh7110_aoncrg_probe(struct platform_device *pdev)
69
+
{
70
+
struct jh71x0_clk_priv *priv;
71
+
unsigned int idx;
72
+
int ret;
73
+
74
+
priv = devm_kzalloc(&pdev->dev,
75
+
struct_size(priv, reg, JH7110_AONCLK_END),
76
+
GFP_KERNEL);
77
+
if (!priv)
78
+
return -ENOMEM;
79
+
80
+
spin_lock_init(&priv->rmw_lock);
81
+
priv->dev = &pdev->dev;
82
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
83
+
if (IS_ERR(priv->base))
84
+
return PTR_ERR(priv->base);
85
+
86
+
dev_set_drvdata(priv->dev, (void *)(&priv->base));
87
+
88
+
for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
89
+
u32 max = jh7110_aonclk_data[idx].max;
90
+
struct clk_parent_data parents[4] = {};
91
+
struct clk_init_data init = {
92
+
.name = jh7110_aonclk_data[idx].name,
93
+
.ops = starfive_jh71x0_clk_ops(max),
94
+
.parent_data = parents,
95
+
.num_parents =
96
+
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
97
+
.flags = jh7110_aonclk_data[idx].flags,
98
+
};
99
+
struct jh71x0_clk *clk = &priv->reg[idx];
100
+
unsigned int i;
101
+
102
+
for (i = 0; i < init.num_parents; i++) {
103
+
unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
104
+
105
+
if (pidx < JH7110_AONCLK_END)
106
+
parents[i].hw = &priv->reg[pidx].hw;
107
+
else if (pidx == JH7110_AONCLK_OSC)
108
+
parents[i].fw_name = "osc";
109
+
else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
110
+
parents[i].fw_name = "gmac0_rmii_refin";
111
+
else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
112
+
parents[i].fw_name = "gmac0_rgmii_rxin";
113
+
else if (pidx == JH7110_AONCLK_STG_AXIAHB)
114
+
parents[i].fw_name = "stg_axiahb";
115
+
else if (pidx == JH7110_AONCLK_APB_BUS)
116
+
parents[i].fw_name = "apb_bus";
117
+
else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
118
+
parents[i].fw_name = "gmac0_gtxclk";
119
+
else if (pidx == JH7110_AONCLK_RTC_OSC)
120
+
parents[i].fw_name = "rtc_osc";
121
+
}
122
+
123
+
clk->hw.init = &init;
124
+
clk->idx = idx;
125
+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
126
+
127
+
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
128
+
if (ret)
129
+
return ret;
130
+
}
131
+
132
+
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
133
+
if (ret)
134
+
return ret;
135
+
136
+
return jh7110_reset_controller_register(priv, "rst-aon", 1);
137
+
}
138
+
139
+
static const struct of_device_id jh7110_aoncrg_match[] = {
140
+
{ .compatible = "starfive,jh7110-aoncrg" },
141
+
{ /* sentinel */ }
142
+
};
143
+
MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
144
+
145
+
static struct platform_driver jh7110_aoncrg_driver = {
146
+
.probe = jh7110_aoncrg_probe,
147
+
.driver = {
148
+
.name = "clk-starfive-jh7110-aon",
149
+
.of_match_table = jh7110_aoncrg_match,
150
+
},
151
+
};
152
+
module_platform_driver(jh7110_aoncrg_driver);
153
+
154
+
MODULE_AUTHOR("Emil Renner Berthing");
155
+
MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
156
+
MODULE_LICENSE("GPL");
+490
drivers/clk/starfive/clk-starfive-jh7110-sys.c
+490
drivers/clk/starfive/clk-starfive-jh7110-sys.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* StarFive JH7110 System Clock Driver
4
+
*
5
+
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6
+
* Copyright (C) 2022 StarFive Technology Co., Ltd.
7
+
*/
8
+
9
+
#include <linux/auxiliary_bus.h>
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/init.h>
12
+
#include <linux/io.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include <dt-bindings/clock/starfive,jh7110-crg.h>
16
+
17
+
#include "clk-starfive-jh7110.h"
18
+
19
+
/* external clocks */
20
+
#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0)
21
+
#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1)
22
+
#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2)
23
+
#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3)
24
+
#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4)
25
+
#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5)
26
+
#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6)
27
+
#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7)
28
+
#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8)
29
+
#define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_END + 9)
30
+
#define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10)
31
+
#define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11)
32
+
33
+
static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
34
+
/* root */
35
+
JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
36
+
JH7110_SYSCLK_OSC,
37
+
JH7110_SYSCLK_PLL0_OUT),
38
+
JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
39
+
JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
40
+
JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
41
+
JH7110_SYSCLK_PLL2_OUT,
42
+
JH7110_SYSCLK_PLL1_OUT),
43
+
JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
44
+
JH7110_SYSCLK_PLL0_OUT,
45
+
JH7110_SYSCLK_PLL2_OUT),
46
+
JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
47
+
JH7110_SYSCLK_OSC,
48
+
JH7110_SYSCLK_PLL2_OUT),
49
+
JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
50
+
JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
51
+
JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
52
+
JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
53
+
JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
54
+
JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
55
+
JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
56
+
JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
57
+
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
58
+
JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
59
+
JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
60
+
JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
61
+
JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
62
+
JH7110_SYSCLK_MCLK_INNER,
63
+
JH7110_SYSCLK_MCLK_EXT),
64
+
JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
65
+
JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
66
+
JH7110_SYSCLK_PLL2_OUT,
67
+
JH7110_SYSCLK_PLL1_OUT),
68
+
JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
69
+
JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
70
+
JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
71
+
JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
72
+
/* cores */
73
+
JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
74
+
JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
75
+
JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
76
+
JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
77
+
JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
78
+
JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
79
+
JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
80
+
JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
81
+
JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
82
+
JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
83
+
JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
84
+
JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
85
+
JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
86
+
/* noc */
87
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
88
+
JH7110_SYSCLK_CPU_BUS),
89
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
90
+
JH7110_SYSCLK_AXI_CFG0),
91
+
/* ddr */
92
+
JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
93
+
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
94
+
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
95
+
JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
96
+
JH7110_SYSCLK_OSC_DIV2,
97
+
JH7110_SYSCLK_PLL1_DIV2,
98
+
JH7110_SYSCLK_PLL1_DIV4,
99
+
JH7110_SYSCLK_PLL1_DIV8),
100
+
JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
101
+
/* gpu */
102
+
JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
103
+
JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
104
+
JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
105
+
JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
106
+
JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
107
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
108
+
/* isp */
109
+
JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
110
+
JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
111
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
112
+
JH7110_SYSCLK_ISP_AXI),
113
+
/* hifi4 */
114
+
JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
115
+
JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
116
+
/* axi_cfg1 */
117
+
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
118
+
JH7110_SYSCLK_ISP_AXI),
119
+
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
120
+
JH7110_SYSCLK_AHB0),
121
+
/* vout */
122
+
JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
123
+
JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
124
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
125
+
JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
126
+
JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
127
+
JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
128
+
JH7110_SYSCLK_MCLK),
129
+
JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
130
+
JH7110_SYSCLK_OSC),
131
+
/* jpegc */
132
+
JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
133
+
JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
134
+
JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
135
+
JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
136
+
/* vdec */
137
+
JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
138
+
JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
139
+
JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
140
+
JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
141
+
JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
142
+
JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
143
+
JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
144
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
145
+
/* venc */
146
+
JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
147
+
JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
148
+
JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
149
+
JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
150
+
JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
151
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
152
+
/* axi_cfg0 */
153
+
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
154
+
JH7110_SYSCLK_AHB1),
155
+
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
156
+
JH7110_SYSCLK_AXI_CFG0),
157
+
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
158
+
JH7110_SYSCLK_HIFI4_AXI),
159
+
/* intmem */
160
+
JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
161
+
/* qspi */
162
+
JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
163
+
JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
164
+
JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
165
+
JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
166
+
JH7110_SYSCLK_OSC,
167
+
JH7110_SYSCLK_QSPI_REF_SRC),
168
+
/* sdio */
169
+
JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
170
+
JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
171
+
JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
172
+
JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
173
+
/* stg */
174
+
JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
175
+
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
176
+
JH7110_SYSCLK_NOCSTG_BUS),
177
+
/* gmac1 */
178
+
JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
179
+
JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
180
+
JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
181
+
JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
182
+
JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
183
+
JH7110_SYSCLK_GMAC1_RMII_REFIN),
184
+
JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
185
+
JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
186
+
JH7110_SYSCLK_GMAC1_RGMII_RXIN,
187
+
JH7110_SYSCLK_GMAC1_RMII_RTX),
188
+
JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
189
+
JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
190
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
191
+
JH7110_SYSCLK_GMAC1_GTXCLK,
192
+
JH7110_SYSCLK_GMAC1_RMII_RTX),
193
+
JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
194
+
JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
195
+
/* gmac0 */
196
+
JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
197
+
JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
198
+
JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
199
+
JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
200
+
/* apb misc */
201
+
JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
202
+
JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
203
+
JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
204
+
/* can0 */
205
+
JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
206
+
JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
207
+
JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
208
+
/* can1 */
209
+
JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
210
+
JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
211
+
JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
212
+
/* pwm */
213
+
JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
214
+
/* wdt */
215
+
JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
216
+
JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
217
+
/* timer */
218
+
JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
219
+
JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
220
+
JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
221
+
JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
222
+
JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
223
+
/* temp sensor */
224
+
JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
225
+
JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
226
+
/* spi */
227
+
JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
228
+
JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
229
+
JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
230
+
JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
231
+
JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
232
+
JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
233
+
JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
234
+
/* i2c */
235
+
JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
236
+
JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
237
+
JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
238
+
JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
239
+
JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
240
+
JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
241
+
JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
242
+
/* uart */
243
+
JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
244
+
JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
245
+
JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
246
+
JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
247
+
JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
248
+
JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
249
+
JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
250
+
JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
251
+
JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
252
+
JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
253
+
JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
254
+
JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
255
+
/* pwmdac */
256
+
JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
257
+
JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
258
+
/* spdif */
259
+
JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
260
+
JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
261
+
/* i2stx0 */
262
+
JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
263
+
JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
264
+
JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
265
+
JH7110_SYSCLK_I2STX0_BCLK_MST),
266
+
JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
267
+
JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
268
+
JH7110_SYSCLK_I2STX0_BCLK_MST),
269
+
JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
270
+
JH7110_SYSCLK_I2STX0_BCLK_MST,
271
+
JH7110_SYSCLK_I2STX_BCLK_EXT),
272
+
JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
273
+
JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
274
+
JH7110_SYSCLK_I2STX0_LRCK_MST,
275
+
JH7110_SYSCLK_I2STX_LRCK_EXT),
276
+
/* i2stx1 */
277
+
JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
278
+
JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
279
+
JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
280
+
JH7110_SYSCLK_I2STX1_BCLK_MST),
281
+
JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
282
+
JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
283
+
JH7110_SYSCLK_I2STX1_BCLK_MST),
284
+
JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
285
+
JH7110_SYSCLK_I2STX1_BCLK_MST,
286
+
JH7110_SYSCLK_I2STX_BCLK_EXT),
287
+
JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
288
+
JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
289
+
JH7110_SYSCLK_I2STX1_LRCK_MST,
290
+
JH7110_SYSCLK_I2STX_LRCK_EXT),
291
+
/* i2srx */
292
+
JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
293
+
JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
294
+
JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
295
+
JH7110_SYSCLK_I2SRX_BCLK_MST),
296
+
JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
297
+
JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
298
+
JH7110_SYSCLK_I2SRX_BCLK_MST),
299
+
JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
300
+
JH7110_SYSCLK_I2SRX_BCLK_MST,
301
+
JH7110_SYSCLK_I2SRX_BCLK_EXT),
302
+
JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
303
+
JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
304
+
JH7110_SYSCLK_I2SRX_LRCK_MST,
305
+
JH7110_SYSCLK_I2SRX_LRCK_EXT),
306
+
/* pdm */
307
+
JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
308
+
JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
309
+
/* tdm */
310
+
JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
311
+
JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
312
+
JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
313
+
JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
314
+
JH7110_SYSCLK_TDM_INTERNAL,
315
+
JH7110_SYSCLK_TDM_EXT),
316
+
JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
317
+
/* jtag */
318
+
JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
319
+
JH7110_SYSCLK_OSC),
320
+
};
321
+
322
+
static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
323
+
{
324
+
struct jh71x0_clk_priv *priv = data;
325
+
unsigned int idx = clkspec->args[0];
326
+
327
+
if (idx < JH7110_SYSCLK_END)
328
+
return &priv->reg[idx].hw;
329
+
330
+
return ERR_PTR(-EINVAL);
331
+
}
332
+
333
+
static void jh7110_reset_unregister_adev(void *_adev)
334
+
{
335
+
struct auxiliary_device *adev = _adev;
336
+
337
+
auxiliary_device_delete(adev);
338
+
}
339
+
340
+
static void jh7110_reset_adev_release(struct device *dev)
341
+
{
342
+
struct auxiliary_device *adev = to_auxiliary_dev(dev);
343
+
344
+
auxiliary_device_uninit(adev);
345
+
}
346
+
347
+
int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
348
+
const char *adev_name,
349
+
u32 adev_id)
350
+
{
351
+
struct auxiliary_device *adev;
352
+
int ret;
353
+
354
+
adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
355
+
if (!adev)
356
+
return -ENOMEM;
357
+
358
+
adev->name = adev_name;
359
+
adev->dev.parent = priv->dev;
360
+
adev->dev.release = jh7110_reset_adev_release;
361
+
adev->id = adev_id;
362
+
363
+
ret = auxiliary_device_init(adev);
364
+
if (ret)
365
+
return ret;
366
+
367
+
ret = auxiliary_device_add(adev);
368
+
if (ret) {
369
+
auxiliary_device_uninit(adev);
370
+
return ret;
371
+
}
372
+
373
+
return devm_add_action_or_reset(priv->dev,
374
+
jh7110_reset_unregister_adev, adev);
375
+
}
376
+
EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
377
+
378
+
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
379
+
{
380
+
struct jh71x0_clk_priv *priv;
381
+
unsigned int idx;
382
+
int ret;
383
+
384
+
priv = devm_kzalloc(&pdev->dev,
385
+
struct_size(priv, reg, JH7110_SYSCLK_END),
386
+
GFP_KERNEL);
387
+
if (!priv)
388
+
return -ENOMEM;
389
+
390
+
spin_lock_init(&priv->rmw_lock);
391
+
priv->dev = &pdev->dev;
392
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
393
+
if (IS_ERR(priv->base))
394
+
return PTR_ERR(priv->base);
395
+
396
+
dev_set_drvdata(priv->dev, (void *)(&priv->base));
397
+
398
+
/*
399
+
* These PLL clocks are not actually fixed factor clocks and can be
400
+
* controlled by the syscon registers of JH7110. They will be dropped
401
+
* and registered in the PLL clock driver instead.
402
+
*/
403
+
/* 24MHz -> 1000.0MHz */
404
+
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
405
+
"osc", 0, 125, 3);
406
+
if (IS_ERR(priv->pll[0]))
407
+
return PTR_ERR(priv->pll[0]);
408
+
409
+
/* 24MHz -> 1066.0MHz */
410
+
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
411
+
"osc", 0, 533, 12);
412
+
if (IS_ERR(priv->pll[1]))
413
+
return PTR_ERR(priv->pll[1]);
414
+
415
+
/* 24MHz -> 1188.0MHz */
416
+
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
417
+
"osc", 0, 99, 2);
418
+
if (IS_ERR(priv->pll[2]))
419
+
return PTR_ERR(priv->pll[2]);
420
+
421
+
for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
422
+
u32 max = jh7110_sysclk_data[idx].max;
423
+
struct clk_parent_data parents[4] = {};
424
+
struct clk_init_data init = {
425
+
.name = jh7110_sysclk_data[idx].name,
426
+
.ops = starfive_jh71x0_clk_ops(max),
427
+
.parent_data = parents,
428
+
.num_parents =
429
+
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
430
+
.flags = jh7110_sysclk_data[idx].flags,
431
+
};
432
+
struct jh71x0_clk *clk = &priv->reg[idx];
433
+
unsigned int i;
434
+
435
+
for (i = 0; i < init.num_parents; i++) {
436
+
unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
437
+
438
+
if (pidx < JH7110_SYSCLK_END)
439
+
parents[i].hw = &priv->reg[pidx].hw;
440
+
else if (pidx == JH7110_SYSCLK_OSC)
441
+
parents[i].fw_name = "osc";
442
+
else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
443
+
parents[i].fw_name = "gmac1_rmii_refin";
444
+
else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
445
+
parents[i].fw_name = "gmac1_rgmii_rxin";
446
+
else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
447
+
parents[i].fw_name = "i2stx_bclk_ext";
448
+
else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
449
+
parents[i].fw_name = "i2stx_lrck_ext";
450
+
else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
451
+
parents[i].fw_name = "i2srx_bclk_ext";
452
+
else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
453
+
parents[i].fw_name = "i2srx_lrck_ext";
454
+
else if (pidx == JH7110_SYSCLK_TDM_EXT)
455
+
parents[i].fw_name = "tdm_ext";
456
+
else if (pidx == JH7110_SYSCLK_MCLK_EXT)
457
+
parents[i].fw_name = "mclk_ext";
458
+
else
459
+
parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
460
+
}
461
+
462
+
clk->hw.init = &init;
463
+
clk->idx = idx;
464
+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
465
+
466
+
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
467
+
if (ret)
468
+
return ret;
469
+
}
470
+
471
+
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
472
+
if (ret)
473
+
return ret;
474
+
475
+
return jh7110_reset_controller_register(priv, "rst-sys", 0);
476
+
}
477
+
478
+
static const struct of_device_id jh7110_syscrg_match[] = {
479
+
{ .compatible = "starfive,jh7110-syscrg" },
480
+
{ /* sentinel */ }
481
+
};
482
+
483
+
static struct platform_driver jh7110_syscrg_driver = {
484
+
.driver = {
485
+
.name = "clk-starfive-jh7110-sys",
486
+
.of_match_table = jh7110_syscrg_match,
487
+
.suppress_bind_attrs = true,
488
+
},
489
+
};
490
+
builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
+11
drivers/clk/starfive/clk-starfive-jh7110.h
+11
drivers/clk/starfive/clk-starfive-jh7110.h
+333
drivers/clk/starfive/clk-starfive-jh71x0.c
+333
drivers/clk/starfive/clk-starfive-jh71x0.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* StarFive JH71X0 Clock Generator Driver
4
+
*
5
+
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/debugfs.h>
10
+
#include <linux/device.h>
11
+
#include <linux/io.h>
12
+
13
+
#include "clk-starfive-jh71x0.h"
14
+
15
+
static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
16
+
{
17
+
return container_of(hw, struct jh71x0_clk, hw);
18
+
}
19
+
20
+
static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
21
+
{
22
+
return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
23
+
}
24
+
25
+
static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
26
+
{
27
+
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
28
+
void __iomem *reg = priv->base + 4 * clk->idx;
29
+
30
+
return readl_relaxed(reg);
31
+
}
32
+
33
+
static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
34
+
{
35
+
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
36
+
void __iomem *reg = priv->base + 4 * clk->idx;
37
+
unsigned long flags;
38
+
39
+
spin_lock_irqsave(&priv->rmw_lock, flags);
40
+
value |= readl_relaxed(reg) & ~mask;
41
+
writel_relaxed(value, reg);
42
+
spin_unlock_irqrestore(&priv->rmw_lock, flags);
43
+
}
44
+
45
+
static int jh71x0_clk_enable(struct clk_hw *hw)
46
+
{
47
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
48
+
49
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
50
+
return 0;
51
+
}
52
+
53
+
static void jh71x0_clk_disable(struct clk_hw *hw)
54
+
{
55
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
56
+
57
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
58
+
}
59
+
60
+
static int jh71x0_clk_is_enabled(struct clk_hw *hw)
61
+
{
62
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
63
+
64
+
return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
65
+
}
66
+
67
+
static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
68
+
unsigned long parent_rate)
69
+
{
70
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
71
+
u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
72
+
73
+
return div ? parent_rate / div : 0;
74
+
}
75
+
76
+
static int jh71x0_clk_determine_rate(struct clk_hw *hw,
77
+
struct clk_rate_request *req)
78
+
{
79
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
80
+
unsigned long parent = req->best_parent_rate;
81
+
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
82
+
unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
83
+
unsigned long result = parent / div;
84
+
85
+
/*
86
+
* we want the result clamped by min_rate and max_rate if possible:
87
+
* case 1: div hits the max divider value, which means it's less than
88
+
* parent / rate, so the result is greater than rate and min_rate in
89
+
* particular. we can't do anything about result > max_rate because the
90
+
* divider doesn't go any further.
91
+
* case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
92
+
* always lower or equal to rate and max_rate. however the result may
93
+
* turn out lower than min_rate, but then the next higher rate is fine:
94
+
* div - 1 = ceil(parent / rate) - 1 < parent / rate
95
+
* and thus
96
+
* min_rate <= rate < parent / (div - 1)
97
+
*/
98
+
if (result < req->min_rate && div > 1)
99
+
result = parent / (div - 1);
100
+
101
+
req->rate = result;
102
+
return 0;
103
+
}
104
+
105
+
static int jh71x0_clk_set_rate(struct clk_hw *hw,
106
+
unsigned long rate,
107
+
unsigned long parent_rate)
108
+
{
109
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
110
+
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
111
+
1UL, (unsigned long)clk->max_div);
112
+
113
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
114
+
return 0;
115
+
}
116
+
117
+
static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
118
+
unsigned long parent_rate)
119
+
{
120
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
121
+
u32 reg = jh71x0_clk_reg_get(clk);
122
+
unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
123
+
((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
124
+
125
+
return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
126
+
}
127
+
128
+
static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
129
+
struct clk_rate_request *req)
130
+
{
131
+
unsigned long parent100 = 100 * req->best_parent_rate;
132
+
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
133
+
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
134
+
JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
135
+
unsigned long result = parent100 / div100;
136
+
137
+
/* clamp the result as in jh71x0_clk_determine_rate() above */
138
+
if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
139
+
result = parent100 / (div100 + 1);
140
+
if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
141
+
result = parent100 / (div100 - 1);
142
+
143
+
req->rate = result;
144
+
return 0;
145
+
}
146
+
147
+
static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
148
+
unsigned long rate,
149
+
unsigned long parent_rate)
150
+
{
151
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
152
+
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
153
+
JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
154
+
u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
155
+
156
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
157
+
return 0;
158
+
}
159
+
160
+
static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
161
+
{
162
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
163
+
u32 value = jh71x0_clk_reg_get(clk);
164
+
165
+
return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
166
+
}
167
+
168
+
static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
169
+
{
170
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
171
+
u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
172
+
173
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
174
+
return 0;
175
+
}
176
+
177
+
static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,
178
+
struct clk_rate_request *req)
179
+
{
180
+
return clk_mux_determine_rate_flags(hw, req, 0);
181
+
}
182
+
183
+
static int jh71x0_clk_get_phase(struct clk_hw *hw)
184
+
{
185
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
186
+
u32 value = jh71x0_clk_reg_get(clk);
187
+
188
+
return (value & JH71X0_CLK_INVERT) ? 180 : 0;
189
+
}
190
+
191
+
static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
192
+
{
193
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
194
+
u32 value;
195
+
196
+
if (degrees == 0)
197
+
value = 0;
198
+
else if (degrees == 180)
199
+
value = JH71X0_CLK_INVERT;
200
+
else
201
+
return -EINVAL;
202
+
203
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
204
+
return 0;
205
+
}
206
+
207
+
#ifdef CONFIG_DEBUG_FS
208
+
static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
209
+
{
210
+
static const struct debugfs_reg32 jh71x0_clk_reg = {
211
+
.name = "CTRL",
212
+
.offset = 0,
213
+
};
214
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
215
+
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
216
+
struct debugfs_regset32 *regset;
217
+
218
+
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
219
+
if (!regset)
220
+
return;
221
+
222
+
regset->regs = &jh71x0_clk_reg;
223
+
regset->nregs = 1;
224
+
regset->base = priv->base + 4 * clk->idx;
225
+
226
+
debugfs_create_regset32("registers", 0400, dentry, regset);
227
+
}
228
+
#else
229
+
#define jh71x0_clk_debug_init NULL
230
+
#endif
231
+
232
+
static const struct clk_ops jh71x0_clk_gate_ops = {
233
+
.enable = jh71x0_clk_enable,
234
+
.disable = jh71x0_clk_disable,
235
+
.is_enabled = jh71x0_clk_is_enabled,
236
+
.debug_init = jh71x0_clk_debug_init,
237
+
};
238
+
239
+
static const struct clk_ops jh71x0_clk_div_ops = {
240
+
.recalc_rate = jh71x0_clk_recalc_rate,
241
+
.determine_rate = jh71x0_clk_determine_rate,
242
+
.set_rate = jh71x0_clk_set_rate,
243
+
.debug_init = jh71x0_clk_debug_init,
244
+
};
245
+
246
+
static const struct clk_ops jh71x0_clk_fdiv_ops = {
247
+
.recalc_rate = jh71x0_clk_frac_recalc_rate,
248
+
.determine_rate = jh71x0_clk_frac_determine_rate,
249
+
.set_rate = jh71x0_clk_frac_set_rate,
250
+
.debug_init = jh71x0_clk_debug_init,
251
+
};
252
+
253
+
static const struct clk_ops jh71x0_clk_gdiv_ops = {
254
+
.enable = jh71x0_clk_enable,
255
+
.disable = jh71x0_clk_disable,
256
+
.is_enabled = jh71x0_clk_is_enabled,
257
+
.recalc_rate = jh71x0_clk_recalc_rate,
258
+
.determine_rate = jh71x0_clk_determine_rate,
259
+
.set_rate = jh71x0_clk_set_rate,
260
+
.debug_init = jh71x0_clk_debug_init,
261
+
};
262
+
263
+
static const struct clk_ops jh71x0_clk_mux_ops = {
264
+
.determine_rate = jh71x0_clk_mux_determine_rate,
265
+
.set_parent = jh71x0_clk_set_parent,
266
+
.get_parent = jh71x0_clk_get_parent,
267
+
.debug_init = jh71x0_clk_debug_init,
268
+
};
269
+
270
+
static const struct clk_ops jh71x0_clk_gmux_ops = {
271
+
.enable = jh71x0_clk_enable,
272
+
.disable = jh71x0_clk_disable,
273
+
.is_enabled = jh71x0_clk_is_enabled,
274
+
.determine_rate = jh71x0_clk_mux_determine_rate,
275
+
.set_parent = jh71x0_clk_set_parent,
276
+
.get_parent = jh71x0_clk_get_parent,
277
+
.debug_init = jh71x0_clk_debug_init,
278
+
};
279
+
280
+
static const struct clk_ops jh71x0_clk_mdiv_ops = {
281
+
.recalc_rate = jh71x0_clk_recalc_rate,
282
+
.determine_rate = jh71x0_clk_determine_rate,
283
+
.get_parent = jh71x0_clk_get_parent,
284
+
.set_parent = jh71x0_clk_set_parent,
285
+
.set_rate = jh71x0_clk_set_rate,
286
+
.debug_init = jh71x0_clk_debug_init,
287
+
};
288
+
289
+
static const struct clk_ops jh71x0_clk_gmd_ops = {
290
+
.enable = jh71x0_clk_enable,
291
+
.disable = jh71x0_clk_disable,
292
+
.is_enabled = jh71x0_clk_is_enabled,
293
+
.recalc_rate = jh71x0_clk_recalc_rate,
294
+
.determine_rate = jh71x0_clk_determine_rate,
295
+
.get_parent = jh71x0_clk_get_parent,
296
+
.set_parent = jh71x0_clk_set_parent,
297
+
.set_rate = jh71x0_clk_set_rate,
298
+
.debug_init = jh71x0_clk_debug_init,
299
+
};
300
+
301
+
static const struct clk_ops jh71x0_clk_inv_ops = {
302
+
.get_phase = jh71x0_clk_get_phase,
303
+
.set_phase = jh71x0_clk_set_phase,
304
+
.debug_init = jh71x0_clk_debug_init,
305
+
};
306
+
307
+
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
308
+
{
309
+
if (max & JH71X0_CLK_DIV_MASK) {
310
+
if (max & JH71X0_CLK_MUX_MASK) {
311
+
if (max & JH71X0_CLK_ENABLE)
312
+
return &jh71x0_clk_gmd_ops;
313
+
return &jh71x0_clk_mdiv_ops;
314
+
}
315
+
if (max & JH71X0_CLK_ENABLE)
316
+
return &jh71x0_clk_gdiv_ops;
317
+
if (max == JH71X0_CLK_FRAC_MAX)
318
+
return &jh71x0_clk_fdiv_ops;
319
+
return &jh71x0_clk_div_ops;
320
+
}
321
+
322
+
if (max & JH71X0_CLK_MUX_MASK) {
323
+
if (max & JH71X0_CLK_ENABLE)
324
+
return &jh71x0_clk_gmux_ops;
325
+
return &jh71x0_clk_mux_ops;
326
+
}
327
+
328
+
if (max & JH71X0_CLK_ENABLE)
329
+
return &jh71x0_clk_gate_ops;
330
+
331
+
return &jh71x0_clk_inv_ops;
332
+
}
333
+
EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
+123
drivers/clk/starfive/clk-starfive-jh71x0.h
+123
drivers/clk/starfive/clk-starfive-jh71x0.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
#ifndef __CLK_STARFIVE_JH71X0_H
3
+
#define __CLK_STARFIVE_JH71X0_H
4
+
5
+
#include <linux/bits.h>
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/device.h>
8
+
#include <linux/spinlock.h>
9
+
10
+
/* register fields */
11
+
#define JH71X0_CLK_ENABLE BIT(31)
12
+
#define JH71X0_CLK_INVERT BIT(30)
13
+
#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
14
+
#define JH71X0_CLK_MUX_SHIFT 24
15
+
#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
16
+
#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
17
+
#define JH71X0_CLK_FRAC_SHIFT 8
18
+
#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
19
+
20
+
/* fractional divider min/max */
21
+
#define JH71X0_CLK_FRAC_MIN 100UL
22
+
#define JH71X0_CLK_FRAC_MAX 25599UL
23
+
24
+
/* clock data */
25
+
struct jh71x0_clk_data {
26
+
const char *name;
27
+
unsigned long flags;
28
+
u32 max;
29
+
u8 parents[4];
30
+
};
31
+
32
+
#define JH71X0_GATE(_idx, _name, _flags, _parent) \
33
+
[_idx] = { \
34
+
.name = _name, \
35
+
.flags = CLK_SET_RATE_PARENT | (_flags), \
36
+
.max = JH71X0_CLK_ENABLE, \
37
+
.parents = { [0] = _parent }, \
38
+
}
39
+
40
+
#define JH71X0__DIV(_idx, _name, _max, _parent) \
41
+
[_idx] = { \
42
+
.name = _name, \
43
+
.flags = 0, \
44
+
.max = _max, \
45
+
.parents = { [0] = _parent }, \
46
+
}
47
+
48
+
#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
49
+
[_idx] = { \
50
+
.name = _name, \
51
+
.flags = _flags, \
52
+
.max = JH71X0_CLK_ENABLE | (_max), \
53
+
.parents = { [0] = _parent }, \
54
+
}
55
+
56
+
#define JH71X0_FDIV(_idx, _name, _parent) \
57
+
[_idx] = { \
58
+
.name = _name, \
59
+
.flags = 0, \
60
+
.max = JH71X0_CLK_FRAC_MAX, \
61
+
.parents = { [0] = _parent }, \
62
+
}
63
+
64
+
#define JH71X0__MUX(_idx, _name, _nparents, ...) \
65
+
[_idx] = { \
66
+
.name = _name, \
67
+
.flags = 0, \
68
+
.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
69
+
.parents = { __VA_ARGS__ }, \
70
+
}
71
+
72
+
#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
73
+
[_idx] = { \
74
+
.name = _name, \
75
+
.flags = _flags, \
76
+
.max = JH71X0_CLK_ENABLE | \
77
+
(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
78
+
.parents = { __VA_ARGS__ }, \
79
+
}
80
+
81
+
#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
82
+
[_idx] = { \
83
+
.name = _name, \
84
+
.flags = 0, \
85
+
.max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
86
+
.parents = { __VA_ARGS__ }, \
87
+
}
88
+
89
+
#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
90
+
[_idx] = { \
91
+
.name = _name, \
92
+
.flags = _flags, \
93
+
.max = JH71X0_CLK_ENABLE | \
94
+
(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
95
+
.parents = { __VA_ARGS__ }, \
96
+
}
97
+
98
+
#define JH71X0__INV(_idx, _name, _parent) \
99
+
[_idx] = { \
100
+
.name = _name, \
101
+
.flags = CLK_SET_RATE_PARENT, \
102
+
.max = JH71X0_CLK_INVERT, \
103
+
.parents = { [0] = _parent }, \
104
+
}
105
+
106
+
struct jh71x0_clk {
107
+
struct clk_hw hw;
108
+
unsigned int idx;
109
+
unsigned int max_div;
110
+
};
111
+
112
+
struct jh71x0_clk_priv {
113
+
/* protect clk enable and set rate/parent from happening at the same time */
114
+
spinlock_t rmw_lock;
115
+
struct device *dev;
116
+
void __iomem *base;
117
+
struct clk_hw *pll[3];
118
+
struct jh71x0_clk reg[];
119
+
};
120
+
121
+
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
122
+
123
+
#endif
+1
-7
drivers/reset/Kconfig
+1
-7
drivers/reset/Kconfig
···
232
232
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
233
233
driver gets initialized early during platform init calls.
234
234
235
-
config RESET_STARFIVE_JH7100
236
-
bool "StarFive JH7100 Reset Driver"
237
-
depends on SOC_STARFIVE || COMPILE_TEST
238
-
default SOC_STARFIVE
239
-
help
240
-
This enables the reset controller driver for the StarFive JH7100 SoC.
241
-
242
235
config RESET_SUNPLUS
243
236
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
244
237
default ARCH_SUNPLUS
···
313
320
help
314
321
This enables the reset controller driver for Xilinx Zynq SoCs.
315
322
323
+
source "drivers/reset/starfive/Kconfig"
316
324
source "drivers/reset/sti/Kconfig"
317
325
source "drivers/reset/hisilicon/Kconfig"
318
326
source "drivers/reset/tegra/Kconfig"
+1
-1
drivers/reset/Makefile
+1
-1
drivers/reset/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
obj-y += core.o
3
3
obj-y += hisilicon/
4
+
obj-y += starfive/
4
5
obj-$(CONFIG_ARCH_STI) += sti/
5
6
obj-$(CONFIG_ARCH_TEGRA) += tegra/
6
7
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
···
31
30
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
32
31
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
33
32
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
34
-
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
35
33
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
36
34
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
37
35
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
-173
drivers/reset/reset-starfive-jh7100.c
-173
drivers/reset/reset-starfive-jh7100.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* Reset driver for the StarFive JH7100 SoC
4
-
*
5
-
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
6
-
*/
7
-
8
-
#include <linux/bitmap.h>
9
-
#include <linux/io.h>
10
-
#include <linux/io-64-nonatomic-lo-hi.h>
11
-
#include <linux/iopoll.h>
12
-
#include <linux/mod_devicetable.h>
13
-
#include <linux/platform_device.h>
14
-
#include <linux/reset-controller.h>
15
-
#include <linux/spinlock.h>
16
-
17
-
#include <dt-bindings/reset/starfive-jh7100.h>
18
-
19
-
/* register offsets */
20
-
#define JH7100_RESET_ASSERT0 0x00
21
-
#define JH7100_RESET_ASSERT1 0x04
22
-
#define JH7100_RESET_ASSERT2 0x08
23
-
#define JH7100_RESET_ASSERT3 0x0c
24
-
#define JH7100_RESET_STATUS0 0x10
25
-
#define JH7100_RESET_STATUS1 0x14
26
-
#define JH7100_RESET_STATUS2 0x18
27
-
#define JH7100_RESET_STATUS3 0x1c
28
-
29
-
/*
30
-
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
31
-
* line 32m + n, and writing a 0 deasserts the same line.
32
-
* Most reset lines have their status inverted so a 0 bit in the STATUS
33
-
* register means the line is asserted and a 1 means it's deasserted. A few
34
-
* lines don't though, so store the expected value of the status registers when
35
-
* all lines are asserted.
36
-
*/
37
-
static const u64 jh7100_reset_asserted[2] = {
38
-
/* STATUS0 */
39
-
BIT_ULL_MASK(JH7100_RST_U74) |
40
-
BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
41
-
BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
42
-
/* STATUS1 */
43
-
BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
44
-
BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
45
-
/* STATUS2 */
46
-
BIT_ULL_MASK(JH7100_RST_E24) |
47
-
/* STATUS3 */
48
-
0,
49
-
};
50
-
51
-
struct jh7100_reset {
52
-
struct reset_controller_dev rcdev;
53
-
/* protect registers against concurrent read-modify-write */
54
-
spinlock_t lock;
55
-
void __iomem *base;
56
-
};
57
-
58
-
static inline struct jh7100_reset *
59
-
jh7100_reset_from(struct reset_controller_dev *rcdev)
60
-
{
61
-
return container_of(rcdev, struct jh7100_reset, rcdev);
62
-
}
63
-
64
-
static int jh7100_reset_update(struct reset_controller_dev *rcdev,
65
-
unsigned long id, bool assert)
66
-
{
67
-
struct jh7100_reset *data = jh7100_reset_from(rcdev);
68
-
unsigned long offset = BIT_ULL_WORD(id);
69
-
u64 mask = BIT_ULL_MASK(id);
70
-
void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
71
-
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
72
-
u64 done = jh7100_reset_asserted[offset] & mask;
73
-
u64 value;
74
-
unsigned long flags;
75
-
int ret;
76
-
77
-
if (!assert)
78
-
done ^= mask;
79
-
80
-
spin_lock_irqsave(&data->lock, flags);
81
-
82
-
value = readq(reg_assert);
83
-
if (assert)
84
-
value |= mask;
85
-
else
86
-
value &= ~mask;
87
-
writeq(value, reg_assert);
88
-
89
-
/* if the associated clock is gated, deasserting might otherwise hang forever */
90
-
ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
91
-
92
-
spin_unlock_irqrestore(&data->lock, flags);
93
-
return ret;
94
-
}
95
-
96
-
static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
97
-
unsigned long id)
98
-
{
99
-
return jh7100_reset_update(rcdev, id, true);
100
-
}
101
-
102
-
static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
103
-
unsigned long id)
104
-
{
105
-
return jh7100_reset_update(rcdev, id, false);
106
-
}
107
-
108
-
static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
109
-
unsigned long id)
110
-
{
111
-
int ret;
112
-
113
-
ret = jh7100_reset_assert(rcdev, id);
114
-
if (ret)
115
-
return ret;
116
-
117
-
return jh7100_reset_deassert(rcdev, id);
118
-
}
119
-
120
-
static int jh7100_reset_status(struct reset_controller_dev *rcdev,
121
-
unsigned long id)
122
-
{
123
-
struct jh7100_reset *data = jh7100_reset_from(rcdev);
124
-
unsigned long offset = BIT_ULL_WORD(id);
125
-
u64 mask = BIT_ULL_MASK(id);
126
-
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
127
-
u64 value = readq(reg_status);
128
-
129
-
return !((value ^ jh7100_reset_asserted[offset]) & mask);
130
-
}
131
-
132
-
static const struct reset_control_ops jh7100_reset_ops = {
133
-
.assert = jh7100_reset_assert,
134
-
.deassert = jh7100_reset_deassert,
135
-
.reset = jh7100_reset_reset,
136
-
.status = jh7100_reset_status,
137
-
};
138
-
139
-
static int __init jh7100_reset_probe(struct platform_device *pdev)
140
-
{
141
-
struct jh7100_reset *data;
142
-
143
-
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
144
-
if (!data)
145
-
return -ENOMEM;
146
-
147
-
data->base = devm_platform_ioremap_resource(pdev, 0);
148
-
if (IS_ERR(data->base))
149
-
return PTR_ERR(data->base);
150
-
151
-
data->rcdev.ops = &jh7100_reset_ops;
152
-
data->rcdev.owner = THIS_MODULE;
153
-
data->rcdev.nr_resets = JH7100_RSTN_END;
154
-
data->rcdev.dev = &pdev->dev;
155
-
data->rcdev.of_node = pdev->dev.of_node;
156
-
spin_lock_init(&data->lock);
157
-
158
-
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
159
-
}
160
-
161
-
static const struct of_device_id jh7100_reset_dt_ids[] = {
162
-
{ .compatible = "starfive,jh7100-reset" },
163
-
{ /* sentinel */ }
164
-
};
165
-
166
-
static struct platform_driver jh7100_reset_driver = {
167
-
.driver = {
168
-
.name = "jh7100-reset",
169
-
.of_match_table = jh7100_reset_dt_ids,
170
-
.suppress_bind_attrs = true,
171
-
},
172
-
};
173
-
builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
+20
drivers/reset/starfive/Kconfig
+20
drivers/reset/starfive/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config RESET_STARFIVE_JH71X0
4
+
bool
5
+
6
+
config RESET_STARFIVE_JH7100
7
+
bool "StarFive JH7100 Reset Driver"
8
+
depends on ARCH_STARFIVE || COMPILE_TEST
9
+
select RESET_STARFIVE_JH71X0
10
+
default ARCH_STARFIVE
11
+
help
12
+
This enables the reset controller driver for the StarFive JH7100 SoC.
13
+
14
+
config RESET_STARFIVE_JH7110
15
+
bool "StarFive JH7110 Reset Driver"
16
+
depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
17
+
select RESET_STARFIVE_JH71X0
18
+
default ARCH_STARFIVE
19
+
help
20
+
This enables the reset controller driver for the StarFive JH7110 SoC.
+5
drivers/reset/starfive/Makefile
+5
drivers/reset/starfive/Makefile
+74
drivers/reset/starfive/reset-starfive-jh7100.c
+74
drivers/reset/starfive/reset-starfive-jh7100.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Reset driver for the StarFive JH7100 SoC
4
+
*
5
+
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
6
+
*/
7
+
8
+
#include <linux/mod_devicetable.h>
9
+
#include <linux/platform_device.h>
10
+
11
+
#include "reset-starfive-jh71x0.h"
12
+
13
+
#include <dt-bindings/reset/starfive-jh7100.h>
14
+
15
+
/* register offsets */
16
+
#define JH7100_RESET_ASSERT0 0x00
17
+
#define JH7100_RESET_ASSERT1 0x04
18
+
#define JH7100_RESET_ASSERT2 0x08
19
+
#define JH7100_RESET_ASSERT3 0x0c
20
+
#define JH7100_RESET_STATUS0 0x10
21
+
#define JH7100_RESET_STATUS1 0x14
22
+
#define JH7100_RESET_STATUS2 0x18
23
+
#define JH7100_RESET_STATUS3 0x1c
24
+
25
+
/*
26
+
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
27
+
* line 32m + n, and writing a 0 deasserts the same line.
28
+
* Most reset lines have their status inverted so a 0 bit in the STATUS
29
+
* register means the line is asserted and a 1 means it's deasserted. A few
30
+
* lines don't though, so store the expected value of the status registers when
31
+
* all lines are asserted.
32
+
*/
33
+
static const u32 jh7100_reset_asserted[4] = {
34
+
/* STATUS0 */
35
+
BIT(JH7100_RST_U74 % 32) |
36
+
BIT(JH7100_RST_VP6_DRESET % 32) |
37
+
BIT(JH7100_RST_VP6_BRESET % 32),
38
+
/* STATUS1 */
39
+
BIT(JH7100_RST_HIFI4_DRESET % 32) |
40
+
BIT(JH7100_RST_HIFI4_BRESET % 32),
41
+
/* STATUS2 */
42
+
BIT(JH7100_RST_E24 % 32),
43
+
/* STATUS3 */
44
+
0,
45
+
};
46
+
47
+
static int __init jh7100_reset_probe(struct platform_device *pdev)
48
+
{
49
+
void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
50
+
51
+
if (IS_ERR(base))
52
+
return PTR_ERR(base);
53
+
54
+
return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
55
+
base + JH7100_RESET_ASSERT0,
56
+
base + JH7100_RESET_STATUS0,
57
+
jh7100_reset_asserted,
58
+
JH7100_RSTN_END,
59
+
THIS_MODULE);
60
+
}
61
+
62
+
static const struct of_device_id jh7100_reset_dt_ids[] = {
63
+
{ .compatible = "starfive,jh7100-reset" },
64
+
{ /* sentinel */ }
65
+
};
66
+
67
+
static struct platform_driver jh7100_reset_driver = {
68
+
.driver = {
69
+
.name = "jh7100-reset",
70
+
.of_match_table = jh7100_reset_dt_ids,
71
+
.suppress_bind_attrs = true,
72
+
},
73
+
};
74
+
builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
+70
drivers/reset/starfive/reset-starfive-jh7110.c
+70
drivers/reset/starfive/reset-starfive-jh7110.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Reset driver for the StarFive JH7110 SoC
4
+
*
5
+
* Copyright (C) 2022 StarFive Technology Co., Ltd.
6
+
*/
7
+
8
+
#include <linux/auxiliary_bus.h>
9
+
10
+
#include "reset-starfive-jh71x0.h"
11
+
12
+
#include <dt-bindings/reset/starfive,jh7110-crg.h>
13
+
14
+
struct jh7110_reset_info {
15
+
unsigned int nr_resets;
16
+
unsigned int assert_offset;
17
+
unsigned int status_offset;
18
+
};
19
+
20
+
static const struct jh7110_reset_info jh7110_sys_info = {
21
+
.nr_resets = JH7110_SYSRST_END,
22
+
.assert_offset = 0x2F8,
23
+
.status_offset = 0x308,
24
+
};
25
+
26
+
static const struct jh7110_reset_info jh7110_aon_info = {
27
+
.nr_resets = JH7110_AONRST_END,
28
+
.assert_offset = 0x38,
29
+
.status_offset = 0x3C,
30
+
};
31
+
32
+
static int jh7110_reset_probe(struct auxiliary_device *adev,
33
+
const struct auxiliary_device_id *id)
34
+
{
35
+
struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
36
+
void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
37
+
38
+
if (!info || !base)
39
+
return -ENODEV;
40
+
41
+
return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
42
+
*base + info->assert_offset,
43
+
*base + info->status_offset,
44
+
NULL,
45
+
info->nr_resets,
46
+
NULL);
47
+
}
48
+
49
+
static const struct auxiliary_device_id jh7110_reset_ids[] = {
50
+
{
51
+
.name = "clk_starfive_jh7110_sys.rst-sys",
52
+
.driver_data = (kernel_ulong_t)&jh7110_sys_info,
53
+
},
54
+
{
55
+
.name = "clk_starfive_jh7110_sys.rst-aon",
56
+
.driver_data = (kernel_ulong_t)&jh7110_aon_info,
57
+
},
58
+
{ /* sentinel */ }
59
+
};
60
+
MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids);
61
+
62
+
static struct auxiliary_driver jh7110_reset_driver = {
63
+
.probe = jh7110_reset_probe,
64
+
.id_table = jh7110_reset_ids,
65
+
};
66
+
module_auxiliary_driver(jh7110_reset_driver);
67
+
68
+
MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
69
+
MODULE_DESCRIPTION("StarFive JH7110 reset driver");
70
+
MODULE_LICENSE("GPL");
+131
drivers/reset/starfive/reset-starfive-jh71x0.c
+131
drivers/reset/starfive/reset-starfive-jh71x0.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Reset driver for the StarFive JH71X0 SoCs
4
+
*
5
+
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
6
+
*/
7
+
8
+
#include <linux/bitmap.h>
9
+
#include <linux/device.h>
10
+
#include <linux/io.h>
11
+
#include <linux/iopoll.h>
12
+
#include <linux/reset-controller.h>
13
+
#include <linux/spinlock.h>
14
+
15
+
#include "reset-starfive-jh71x0.h"
16
+
17
+
struct jh71x0_reset {
18
+
struct reset_controller_dev rcdev;
19
+
/* protect registers against concurrent read-modify-write */
20
+
spinlock_t lock;
21
+
void __iomem *assert;
22
+
void __iomem *status;
23
+
const u32 *asserted;
24
+
};
25
+
26
+
static inline struct jh71x0_reset *
27
+
jh71x0_reset_from(struct reset_controller_dev *rcdev)
28
+
{
29
+
return container_of(rcdev, struct jh71x0_reset, rcdev);
30
+
}
31
+
32
+
static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
33
+
unsigned long id, bool assert)
34
+
{
35
+
struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
36
+
unsigned long offset = id / 32;
37
+
u32 mask = BIT(id % 32);
38
+
void __iomem *reg_assert = data->assert + offset * sizeof(u32);
39
+
void __iomem *reg_status = data->status + offset * sizeof(u32);
40
+
u32 done = data->asserted ? data->asserted[offset] & mask : 0;
41
+
u32 value;
42
+
unsigned long flags;
43
+
int ret;
44
+
45
+
if (!assert)
46
+
done ^= mask;
47
+
48
+
spin_lock_irqsave(&data->lock, flags);
49
+
50
+
value = readl(reg_assert);
51
+
if (assert)
52
+
value |= mask;
53
+
else
54
+
value &= ~mask;
55
+
writel(value, reg_assert);
56
+
57
+
/* if the associated clock is gated, deasserting might otherwise hang forever */
58
+
ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
59
+
60
+
spin_unlock_irqrestore(&data->lock, flags);
61
+
return ret;
62
+
}
63
+
64
+
static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
65
+
unsigned long id)
66
+
{
67
+
return jh71x0_reset_update(rcdev, id, true);
68
+
}
69
+
70
+
static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
71
+
unsigned long id)
72
+
{
73
+
return jh71x0_reset_update(rcdev, id, false);
74
+
}
75
+
76
+
static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
77
+
unsigned long id)
78
+
{
79
+
int ret;
80
+
81
+
ret = jh71x0_reset_assert(rcdev, id);
82
+
if (ret)
83
+
return ret;
84
+
85
+
return jh71x0_reset_deassert(rcdev, id);
86
+
}
87
+
88
+
static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
89
+
unsigned long id)
90
+
{
91
+
struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
92
+
unsigned long offset = id / 32;
93
+
u32 mask = BIT(id % 32);
94
+
void __iomem *reg_status = data->status + offset * sizeof(u32);
95
+
u32 value = readl(reg_status);
96
+
97
+
return !((value ^ data->asserted[offset]) & mask);
98
+
}
99
+
100
+
static const struct reset_control_ops jh71x0_reset_ops = {
101
+
.assert = jh71x0_reset_assert,
102
+
.deassert = jh71x0_reset_deassert,
103
+
.reset = jh71x0_reset_reset,
104
+
.status = jh71x0_reset_status,
105
+
};
106
+
107
+
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
108
+
void __iomem *assert, void __iomem *status,
109
+
const u32 *asserted, unsigned int nr_resets,
110
+
struct module *owner)
111
+
{
112
+
struct jh71x0_reset *data;
113
+
114
+
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
115
+
if (!data)
116
+
return -ENOMEM;
117
+
118
+
data->rcdev.ops = &jh71x0_reset_ops;
119
+
data->rcdev.owner = owner;
120
+
data->rcdev.nr_resets = nr_resets;
121
+
data->rcdev.dev = dev;
122
+
data->rcdev.of_node = of_node;
123
+
124
+
spin_lock_init(&data->lock);
125
+
data->assert = assert;
126
+
data->status = status;
127
+
data->asserted = asserted;
128
+
129
+
return devm_reset_controller_register(dev, &data->rcdev);
130
+
}
131
+
EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
+14
drivers/reset/starfive/reset-starfive-jh71x0.h
+14
drivers/reset/starfive/reset-starfive-jh71x0.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
4
+
*/
5
+
6
+
#ifndef __RESET_STARFIVE_JH71X0_H
7
+
#define __RESET_STARFIVE_JH71X0_H
8
+
9
+
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
10
+
void __iomem *assert, void __iomem *status,
11
+
const u32 *asserted, unsigned int nr_resets,
12
+
struct module *owner);
13
+
14
+
#endif /* __RESET_STARFIVE_JH71X0_H */
+221
include/dt-bindings/clock/starfive,jh7110-crg.h
+221
include/dt-bindings/clock/starfive,jh7110-crg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
+
/*
3
+
* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
7
+
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
8
+
9
+
/* SYSCRG clocks */
10
+
#define JH7110_SYSCLK_CPU_ROOT 0
11
+
#define JH7110_SYSCLK_CPU_CORE 1
12
+
#define JH7110_SYSCLK_CPU_BUS 2
13
+
#define JH7110_SYSCLK_GPU_ROOT 3
14
+
#define JH7110_SYSCLK_PERH_ROOT 4
15
+
#define JH7110_SYSCLK_BUS_ROOT 5
16
+
#define JH7110_SYSCLK_NOCSTG_BUS 6
17
+
#define JH7110_SYSCLK_AXI_CFG0 7
18
+
#define JH7110_SYSCLK_STG_AXIAHB 8
19
+
#define JH7110_SYSCLK_AHB0 9
20
+
#define JH7110_SYSCLK_AHB1 10
21
+
#define JH7110_SYSCLK_APB_BUS 11
22
+
#define JH7110_SYSCLK_APB0 12
23
+
#define JH7110_SYSCLK_PLL0_DIV2 13
24
+
#define JH7110_SYSCLK_PLL1_DIV2 14
25
+
#define JH7110_SYSCLK_PLL2_DIV2 15
26
+
#define JH7110_SYSCLK_AUDIO_ROOT 16
27
+
#define JH7110_SYSCLK_MCLK_INNER 17
28
+
#define JH7110_SYSCLK_MCLK 18
29
+
#define JH7110_SYSCLK_MCLK_OUT 19
30
+
#define JH7110_SYSCLK_ISP_2X 20
31
+
#define JH7110_SYSCLK_ISP_AXI 21
32
+
#define JH7110_SYSCLK_GCLK0 22
33
+
#define JH7110_SYSCLK_GCLK1 23
34
+
#define JH7110_SYSCLK_GCLK2 24
35
+
#define JH7110_SYSCLK_CORE 25
36
+
#define JH7110_SYSCLK_CORE1 26
37
+
#define JH7110_SYSCLK_CORE2 27
38
+
#define JH7110_SYSCLK_CORE3 28
39
+
#define JH7110_SYSCLK_CORE4 29
40
+
#define JH7110_SYSCLK_DEBUG 30
41
+
#define JH7110_SYSCLK_RTC_TOGGLE 31
42
+
#define JH7110_SYSCLK_TRACE0 32
43
+
#define JH7110_SYSCLK_TRACE1 33
44
+
#define JH7110_SYSCLK_TRACE2 34
45
+
#define JH7110_SYSCLK_TRACE3 35
46
+
#define JH7110_SYSCLK_TRACE4 36
47
+
#define JH7110_SYSCLK_TRACE_COM 37
48
+
#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
49
+
#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
50
+
#define JH7110_SYSCLK_OSC_DIV2 40
51
+
#define JH7110_SYSCLK_PLL1_DIV4 41
52
+
#define JH7110_SYSCLK_PLL1_DIV8 42
53
+
#define JH7110_SYSCLK_DDR_BUS 43
54
+
#define JH7110_SYSCLK_DDR_AXI 44
55
+
#define JH7110_SYSCLK_GPU_CORE 45
56
+
#define JH7110_SYSCLK_GPU_CORE_CLK 46
57
+
#define JH7110_SYSCLK_GPU_SYS_CLK 47
58
+
#define JH7110_SYSCLK_GPU_APB 48
59
+
#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
60
+
#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
61
+
#define JH7110_SYSCLK_ISP_TOP_CORE 51
62
+
#define JH7110_SYSCLK_ISP_TOP_AXI 52
63
+
#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
64
+
#define JH7110_SYSCLK_HIFI4_CORE 54
65
+
#define JH7110_SYSCLK_HIFI4_AXI 55
66
+
#define JH7110_SYSCLK_AXI_CFG1_MAIN 56
67
+
#define JH7110_SYSCLK_AXI_CFG1_AHB 57
68
+
#define JH7110_SYSCLK_VOUT_SRC 58
69
+
#define JH7110_SYSCLK_VOUT_AXI 59
70
+
#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
71
+
#define JH7110_SYSCLK_VOUT_TOP_AHB 61
72
+
#define JH7110_SYSCLK_VOUT_TOP_AXI 62
73
+
#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
74
+
#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
75
+
#define JH7110_SYSCLK_JPEGC_AXI 65
76
+
#define JH7110_SYSCLK_CODAJ12_AXI 66
77
+
#define JH7110_SYSCLK_CODAJ12_CORE 67
78
+
#define JH7110_SYSCLK_CODAJ12_APB 68
79
+
#define JH7110_SYSCLK_VDEC_AXI 69
80
+
#define JH7110_SYSCLK_WAVE511_AXI 70
81
+
#define JH7110_SYSCLK_WAVE511_BPU 71
82
+
#define JH7110_SYSCLK_WAVE511_VCE 72
83
+
#define JH7110_SYSCLK_WAVE511_APB 73
84
+
#define JH7110_SYSCLK_VDEC_JPG 74
85
+
#define JH7110_SYSCLK_VDEC_MAIN 75
86
+
#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
87
+
#define JH7110_SYSCLK_VENC_AXI 77
88
+
#define JH7110_SYSCLK_WAVE420L_AXI 78
89
+
#define JH7110_SYSCLK_WAVE420L_BPU 79
90
+
#define JH7110_SYSCLK_WAVE420L_VCE 80
91
+
#define JH7110_SYSCLK_WAVE420L_APB 81
92
+
#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
93
+
#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83
94
+
#define JH7110_SYSCLK_AXI_CFG0_MAIN 84
95
+
#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85
96
+
#define JH7110_SYSCLK_AXIMEM2_AXI 86
97
+
#define JH7110_SYSCLK_QSPI_AHB 87
98
+
#define JH7110_SYSCLK_QSPI_APB 88
99
+
#define JH7110_SYSCLK_QSPI_REF_SRC 89
100
+
#define JH7110_SYSCLK_QSPI_REF 90
101
+
#define JH7110_SYSCLK_SDIO0_AHB 91
102
+
#define JH7110_SYSCLK_SDIO1_AHB 92
103
+
#define JH7110_SYSCLK_SDIO0_SDCARD 93
104
+
#define JH7110_SYSCLK_SDIO1_SDCARD 94
105
+
#define JH7110_SYSCLK_USB_125M 95
106
+
#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
107
+
#define JH7110_SYSCLK_GMAC1_AHB 97
108
+
#define JH7110_SYSCLK_GMAC1_AXI 98
109
+
#define JH7110_SYSCLK_GMAC_SRC 99
110
+
#define JH7110_SYSCLK_GMAC1_GTXCLK 100
111
+
#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
112
+
#define JH7110_SYSCLK_GMAC1_PTP 102
113
+
#define JH7110_SYSCLK_GMAC1_RX 103
114
+
#define JH7110_SYSCLK_GMAC1_RX_INV 104
115
+
#define JH7110_SYSCLK_GMAC1_TX 105
116
+
#define JH7110_SYSCLK_GMAC1_TX_INV 106
117
+
#define JH7110_SYSCLK_GMAC1_GTXC 107
118
+
#define JH7110_SYSCLK_GMAC0_GTXCLK 108
119
+
#define JH7110_SYSCLK_GMAC0_PTP 109
120
+
#define JH7110_SYSCLK_GMAC_PHY 110
121
+
#define JH7110_SYSCLK_GMAC0_GTXC 111
122
+
#define JH7110_SYSCLK_IOMUX_APB 112
123
+
#define JH7110_SYSCLK_MAILBOX_APB 113
124
+
#define JH7110_SYSCLK_INT_CTRL_APB 114
125
+
#define JH7110_SYSCLK_CAN0_APB 115
126
+
#define JH7110_SYSCLK_CAN0_TIMER 116
127
+
#define JH7110_SYSCLK_CAN0_CAN 117
128
+
#define JH7110_SYSCLK_CAN1_APB 118
129
+
#define JH7110_SYSCLK_CAN1_TIMER 119
130
+
#define JH7110_SYSCLK_CAN1_CAN 120
131
+
#define JH7110_SYSCLK_PWM_APB 121
132
+
#define JH7110_SYSCLK_WDT_APB 122
133
+
#define JH7110_SYSCLK_WDT_CORE 123
134
+
#define JH7110_SYSCLK_TIMER_APB 124
135
+
#define JH7110_SYSCLK_TIMER0 125
136
+
#define JH7110_SYSCLK_TIMER1 126
137
+
#define JH7110_SYSCLK_TIMER2 127
138
+
#define JH7110_SYSCLK_TIMER3 128
139
+
#define JH7110_SYSCLK_TEMP_APB 129
140
+
#define JH7110_SYSCLK_TEMP_CORE 130
141
+
#define JH7110_SYSCLK_SPI0_APB 131
142
+
#define JH7110_SYSCLK_SPI1_APB 132
143
+
#define JH7110_SYSCLK_SPI2_APB 133
144
+
#define JH7110_SYSCLK_SPI3_APB 134
145
+
#define JH7110_SYSCLK_SPI4_APB 135
146
+
#define JH7110_SYSCLK_SPI5_APB 136
147
+
#define JH7110_SYSCLK_SPI6_APB 137
148
+
#define JH7110_SYSCLK_I2C0_APB 138
149
+
#define JH7110_SYSCLK_I2C1_APB 139
150
+
#define JH7110_SYSCLK_I2C2_APB 140
151
+
#define JH7110_SYSCLK_I2C3_APB 141
152
+
#define JH7110_SYSCLK_I2C4_APB 142
153
+
#define JH7110_SYSCLK_I2C5_APB 143
154
+
#define JH7110_SYSCLK_I2C6_APB 144
155
+
#define JH7110_SYSCLK_UART0_APB 145
156
+
#define JH7110_SYSCLK_UART0_CORE 146
157
+
#define JH7110_SYSCLK_UART1_APB 147
158
+
#define JH7110_SYSCLK_UART1_CORE 148
159
+
#define JH7110_SYSCLK_UART2_APB 149
160
+
#define JH7110_SYSCLK_UART2_CORE 150
161
+
#define JH7110_SYSCLK_UART3_APB 151
162
+
#define JH7110_SYSCLK_UART3_CORE 152
163
+
#define JH7110_SYSCLK_UART4_APB 153
164
+
#define JH7110_SYSCLK_UART4_CORE 154
165
+
#define JH7110_SYSCLK_UART5_APB 155
166
+
#define JH7110_SYSCLK_UART5_CORE 156
167
+
#define JH7110_SYSCLK_PWMDAC_APB 157
168
+
#define JH7110_SYSCLK_PWMDAC_CORE 158
169
+
#define JH7110_SYSCLK_SPDIF_APB 159
170
+
#define JH7110_SYSCLK_SPDIF_CORE 160
171
+
#define JH7110_SYSCLK_I2STX0_APB 161
172
+
#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
173
+
#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
174
+
#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
175
+
#define JH7110_SYSCLK_I2STX0_BCLK 165
176
+
#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
177
+
#define JH7110_SYSCLK_I2STX0_LRCK 167
178
+
#define JH7110_SYSCLK_I2STX1_APB 168
179
+
#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
180
+
#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
181
+
#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
182
+
#define JH7110_SYSCLK_I2STX1_BCLK 172
183
+
#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
184
+
#define JH7110_SYSCLK_I2STX1_LRCK 174
185
+
#define JH7110_SYSCLK_I2SRX_APB 175
186
+
#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
187
+
#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
188
+
#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
189
+
#define JH7110_SYSCLK_I2SRX_BCLK 179
190
+
#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
191
+
#define JH7110_SYSCLK_I2SRX_LRCK 181
192
+
#define JH7110_SYSCLK_PDM_DMIC 182
193
+
#define JH7110_SYSCLK_PDM_APB 183
194
+
#define JH7110_SYSCLK_TDM_AHB 184
195
+
#define JH7110_SYSCLK_TDM_APB 185
196
+
#define JH7110_SYSCLK_TDM_INTERNAL 186
197
+
#define JH7110_SYSCLK_TDM_TDM 187
198
+
#define JH7110_SYSCLK_TDM_TDM_INV 188
199
+
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
200
+
201
+
#define JH7110_SYSCLK_END 190
202
+
203
+
/* AONCRG clocks */
204
+
#define JH7110_AONCLK_OSC_DIV4 0
205
+
#define JH7110_AONCLK_APB_FUNC 1
206
+
#define JH7110_AONCLK_GMAC0_AHB 2
207
+
#define JH7110_AONCLK_GMAC0_AXI 3
208
+
#define JH7110_AONCLK_GMAC0_RMII_RTX 4
209
+
#define JH7110_AONCLK_GMAC0_TX 5
210
+
#define JH7110_AONCLK_GMAC0_TX_INV 6
211
+
#define JH7110_AONCLK_GMAC0_RX 7
212
+
#define JH7110_AONCLK_GMAC0_RX_INV 8
213
+
#define JH7110_AONCLK_OTPC_APB 9
214
+
#define JH7110_AONCLK_RTC_APB 10
215
+
#define JH7110_AONCLK_RTC_INTERNAL 11
216
+
#define JH7110_AONCLK_RTC_32K 12
217
+
#define JH7110_AONCLK_RTC_CAL 13
218
+
219
+
#define JH7110_AONCLK_END 14
220
+
221
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
+154
include/dt-bindings/reset/starfive,jh7110-crg.h
+154
include/dt-bindings/reset/starfive,jh7110-crg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
+
/*
3
+
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
7
+
#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
8
+
9
+
/* SYSCRG resets */
10
+
#define JH7110_SYSRST_JTAG_APB 0
11
+
#define JH7110_SYSRST_SYSCON_APB 1
12
+
#define JH7110_SYSRST_IOMUX_APB 2
13
+
#define JH7110_SYSRST_BUS 3
14
+
#define JH7110_SYSRST_DEBUG 4
15
+
#define JH7110_SYSRST_CORE0 5
16
+
#define JH7110_SYSRST_CORE1 6
17
+
#define JH7110_SYSRST_CORE2 7
18
+
#define JH7110_SYSRST_CORE3 8
19
+
#define JH7110_SYSRST_CORE4 9
20
+
#define JH7110_SYSRST_CORE0_ST 10
21
+
#define JH7110_SYSRST_CORE1_ST 11
22
+
#define JH7110_SYSRST_CORE2_ST 12
23
+
#define JH7110_SYSRST_CORE3_ST 13
24
+
#define JH7110_SYSRST_CORE4_ST 14
25
+
#define JH7110_SYSRST_TRACE0 15
26
+
#define JH7110_SYSRST_TRACE1 16
27
+
#define JH7110_SYSRST_TRACE2 17
28
+
#define JH7110_SYSRST_TRACE3 18
29
+
#define JH7110_SYSRST_TRACE4 19
30
+
#define JH7110_SYSRST_TRACE_COM 20
31
+
#define JH7110_SYSRST_GPU_APB 21
32
+
#define JH7110_SYSRST_GPU_DOMA 22
33
+
#define JH7110_SYSRST_NOC_BUS_APB 23
34
+
#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
35
+
#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
36
+
#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
37
+
#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
38
+
#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
39
+
#define JH7110_SYSRST_NOC_BUS_DDRC 29
40
+
#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
41
+
#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
42
+
43
+
#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
44
+
#define JH7110_SYSRST_AXI_CFG1_AHB 33
45
+
#define JH7110_SYSRST_AXI_CFG1_MAIN 34
46
+
#define JH7110_SYSRST_AXI_CFG0_MAIN 35
47
+
#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
48
+
#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
49
+
#define JH7110_SYSRST_DDR_AXI 38
50
+
#define JH7110_SYSRST_DDR_OSC 39
51
+
#define JH7110_SYSRST_DDR_APB 40
52
+
#define JH7110_SYSRST_ISP_TOP 41
53
+
#define JH7110_SYSRST_ISP_TOP_AXI 42
54
+
#define JH7110_SYSRST_VOUT_TOP_SRC 43
55
+
#define JH7110_SYSRST_CODAJ12_AXI 44
56
+
#define JH7110_SYSRST_CODAJ12_CORE 45
57
+
#define JH7110_SYSRST_CODAJ12_APB 46
58
+
#define JH7110_SYSRST_WAVE511_AXI 47
59
+
#define JH7110_SYSRST_WAVE511_BPU 48
60
+
#define JH7110_SYSRST_WAVE511_VCE 49
61
+
#define JH7110_SYSRST_WAVE511_APB 50
62
+
#define JH7110_SYSRST_VDEC_JPG 51
63
+
#define JH7110_SYSRST_VDEC_MAIN 52
64
+
#define JH7110_SYSRST_AXIMEM0_AXI 53
65
+
#define JH7110_SYSRST_WAVE420L_AXI 54
66
+
#define JH7110_SYSRST_WAVE420L_BPU 55
67
+
#define JH7110_SYSRST_WAVE420L_VCE 56
68
+
#define JH7110_SYSRST_WAVE420L_APB 57
69
+
#define JH7110_SYSRST_AXIMEM1_AXI 58
70
+
#define JH7110_SYSRST_AXIMEM2_AXI 59
71
+
#define JH7110_SYSRST_INTMEM 60
72
+
#define JH7110_SYSRST_QSPI_AHB 61
73
+
#define JH7110_SYSRST_QSPI_APB 62
74
+
#define JH7110_SYSRST_QSPI_REF 63
75
+
76
+
#define JH7110_SYSRST_SDIO0_AHB 64
77
+
#define JH7110_SYSRST_SDIO1_AHB 65
78
+
#define JH7110_SYSRST_GMAC1_AXI 66
79
+
#define JH7110_SYSRST_GMAC1_AHB 67
80
+
#define JH7110_SYSRST_MAILBOX_APB 68
81
+
#define JH7110_SYSRST_SPI0_APB 69
82
+
#define JH7110_SYSRST_SPI1_APB 70
83
+
#define JH7110_SYSRST_SPI2_APB 71
84
+
#define JH7110_SYSRST_SPI3_APB 72
85
+
#define JH7110_SYSRST_SPI4_APB 73
86
+
#define JH7110_SYSRST_SPI5_APB 74
87
+
#define JH7110_SYSRST_SPI6_APB 75
88
+
#define JH7110_SYSRST_I2C0_APB 76
89
+
#define JH7110_SYSRST_I2C1_APB 77
90
+
#define JH7110_SYSRST_I2C2_APB 78
91
+
#define JH7110_SYSRST_I2C3_APB 79
92
+
#define JH7110_SYSRST_I2C4_APB 80
93
+
#define JH7110_SYSRST_I2C5_APB 81
94
+
#define JH7110_SYSRST_I2C6_APB 82
95
+
#define JH7110_SYSRST_UART0_APB 83
96
+
#define JH7110_SYSRST_UART0_CORE 84
97
+
#define JH7110_SYSRST_UART1_APB 85
98
+
#define JH7110_SYSRST_UART1_CORE 86
99
+
#define JH7110_SYSRST_UART2_APB 87
100
+
#define JH7110_SYSRST_UART2_CORE 88
101
+
#define JH7110_SYSRST_UART3_APB 89
102
+
#define JH7110_SYSRST_UART3_CORE 90
103
+
#define JH7110_SYSRST_UART4_APB 91
104
+
#define JH7110_SYSRST_UART4_CORE 92
105
+
#define JH7110_SYSRST_UART5_APB 93
106
+
#define JH7110_SYSRST_UART5_CORE 94
107
+
#define JH7110_SYSRST_SPDIF_APB 95
108
+
109
+
#define JH7110_SYSRST_PWMDAC_APB 96
110
+
#define JH7110_SYSRST_PDM_DMIC 97
111
+
#define JH7110_SYSRST_PDM_APB 98
112
+
#define JH7110_SYSRST_I2SRX_APB 99
113
+
#define JH7110_SYSRST_I2SRX_BCLK 100
114
+
#define JH7110_SYSRST_I2STX0_APB 101
115
+
#define JH7110_SYSRST_I2STX0_BCLK 102
116
+
#define JH7110_SYSRST_I2STX1_APB 103
117
+
#define JH7110_SYSRST_I2STX1_BCLK 104
118
+
#define JH7110_SYSRST_TDM_AHB 105
119
+
#define JH7110_SYSRST_TDM_CORE 106
120
+
#define JH7110_SYSRST_TDM_APB 107
121
+
#define JH7110_SYSRST_PWM_APB 108
122
+
#define JH7110_SYSRST_WDT_APB 109
123
+
#define JH7110_SYSRST_WDT_CORE 110
124
+
#define JH7110_SYSRST_CAN0_APB 111
125
+
#define JH7110_SYSRST_CAN0_CORE 112
126
+
#define JH7110_SYSRST_CAN0_TIMER 113
127
+
#define JH7110_SYSRST_CAN1_APB 114
128
+
#define JH7110_SYSRST_CAN1_CORE 115
129
+
#define JH7110_SYSRST_CAN1_TIMER 116
130
+
#define JH7110_SYSRST_TIMER_APB 117
131
+
#define JH7110_SYSRST_TIMER0 118
132
+
#define JH7110_SYSRST_TIMER1 119
133
+
#define JH7110_SYSRST_TIMER2 120
134
+
#define JH7110_SYSRST_TIMER3 121
135
+
#define JH7110_SYSRST_INT_CTRL_APB 122
136
+
#define JH7110_SYSRST_TEMP_APB 123
137
+
#define JH7110_SYSRST_TEMP_CORE 124
138
+
#define JH7110_SYSRST_JTAG_CERTIFICATION 125
139
+
140
+
#define JH7110_SYSRST_END 126
141
+
142
+
/* AONCRG resets */
143
+
#define JH7110_AONRST_GMAC0_AXI 0
144
+
#define JH7110_AONRST_GMAC0_AHB 1
145
+
#define JH7110_AONRST_IOMUX 2
146
+
#define JH7110_AONRST_PMU_APB 3
147
+
#define JH7110_AONRST_PMU_WKUP 4
148
+
#define JH7110_AONRST_RTC_APB 5
149
+
#define JH7110_AONRST_RTC_CAL 6
150
+
#define JH7110_AONRST_RTC_32K 7
151
+
152
+
#define JH7110_AONRST_END 8
153
+
154
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */