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linux
clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.
Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
authored by
Geliang Tang
and committed by
Stephen Boyd
5fd9c05c
f9285b54
+33
-51
-2
drivers/clk/clk-composite.c
-2
drivers/clk/clk-composite.c
-2
drivers/clk/clk-divider.c
-2
drivers/clk/clk-divider.c
-2
drivers/clk/clk-fixed-factor.c
-2
drivers/clk/clk-fixed-factor.c
-2
drivers/clk/clk-fixed-rate.c
-2
drivers/clk/clk-fixed-rate.c
-2
drivers/clk/clk-fractional-divider.c
-2
drivers/clk/clk-fractional-divider.c
-2
drivers/clk/clk-gate.c
-2
drivers/clk/clk-gate.c
-2
drivers/clk/clk-gpio.c
-2
drivers/clk/clk-gpio.c
-2
drivers/clk/clk-multiplier.c
-2
drivers/clk/clk-multiplier.c
-2
drivers/clk/clk-mux.c
-2
drivers/clk/clk-mux.c
+2
-2
drivers/clk/imx/clk-busy.c
+2
-2
drivers/clk/imx/clk-busy.c
···
38
38
39
39
static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
40
40
{
41
-
struct clk_divider *div = container_of(hw, struct clk_divider, hw);
41
+
struct clk_divider *div = to_clk_divider(hw);
42
42
43
43
return container_of(div, struct clk_busy_divider, div);
44
44
}
···
123
123
124
124
static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
125
125
{
126
-
struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
126
+
struct clk_mux *mux = to_clk_mux(hw);
127
127
128
128
return container_of(mux, struct clk_busy_mux, mux);
129
129
}
+2
-3
drivers/clk/imx/clk-fixup-div.c
+2
-3
drivers/clk/imx/clk-fixup-div.c
···
15
15
#include <linux/slab.h>
16
16
#include "clk.h"
17
17
18
-
#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
19
18
#define div_mask(d) ((1 << (d->width)) - 1)
20
19
21
20
/**
···
34
35
35
36
static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
36
37
{
37
-
struct clk_divider *divider = to_clk_div(hw);
38
+
struct clk_divider *divider = to_clk_divider(hw);
38
39
39
40
return container_of(divider, struct clk_fixup_div, divider);
40
41
}
···
59
60
unsigned long parent_rate)
60
61
{
61
62
struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
62
-
struct clk_divider *div = to_clk_div(hw);
63
+
struct clk_divider *div = to_clk_divider(hw);
63
64
unsigned int divider, value;
64
65
unsigned long flags = 0;
65
66
u32 val;
-2
drivers/clk/imx/clk-fixup-mux.c
-2
drivers/clk/imx/clk-fixup-mux.c
+1
-1
drivers/clk/imx/clk-gate-exclusive.c
+1
-1
drivers/clk/imx/clk-gate-exclusive.c
···
31
31
32
32
static int clk_gate_exclusive_enable(struct clk_hw *hw)
33
33
{
34
-
struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
34
+
struct clk_gate *gate = to_clk_gate(hw);
35
35
struct clk_gate_exclusive *exgate = container_of(gate,
36
36
struct clk_gate_exclusive, gate);
37
37
u32 val = readl(gate->reg);
+4
-4
drivers/clk/mediatek/clk-gate.c
+4
-4
drivers/clk/mediatek/clk-gate.c
···
25
25
26
26
static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
27
27
{
28
-
struct mtk_clk_gate *cg = to_clk_gate(hw);
28
+
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
29
29
u32 val;
30
30
31
31
regmap_read(cg->regmap, cg->sta_ofs, &val);
···
37
37
38
38
static int mtk_cg_bit_is_set(struct clk_hw *hw)
39
39
{
40
-
struct mtk_clk_gate *cg = to_clk_gate(hw);
40
+
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
41
41
u32 val;
42
42
43
43
regmap_read(cg->regmap, cg->sta_ofs, &val);
···
49
49
50
50
static void mtk_cg_set_bit(struct clk_hw *hw)
51
51
{
52
-
struct mtk_clk_gate *cg = to_clk_gate(hw);
52
+
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
53
53
54
54
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
55
55
}
56
56
57
57
static void mtk_cg_clr_bit(struct clk_hw *hw)
58
58
{
59
-
struct mtk_clk_gate *cg = to_clk_gate(hw);
59
+
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
60
60
61
61
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
62
62
}
+1
-1
drivers/clk/mediatek/clk-gate.h
+1
-1
drivers/clk/mediatek/clk-gate.h
-2
drivers/clk/mvebu/common.c
-2
drivers/clk/mvebu/common.c
-2
drivers/clk/mvebu/kirkwood.c
-2
drivers/clk/mvebu/kirkwood.c
+1
-1
drivers/clk/mxs/clk-div.c
+1
-1
drivers/clk/mxs/clk-div.c
-2
drivers/clk/nxp/clk-lpc18xx-ccu.c
-2
drivers/clk/nxp/clk-lpc18xx-ccu.c
+4
-5
drivers/clk/st/clkgen-mux.c
+4
-5
drivers/clk/st/clkgen-mux.c
···
822
822
if (!clk_data->clks[i])
823
823
continue;
824
824
825
-
composite = container_of(__clk_get_hw(clk_data->clks[i]),
826
-
struct clk_composite, hw);
827
-
kfree(container_of(composite->gate_hw, struct clk_gate, hw));
828
-
kfree(container_of(composite->rate_hw, struct clk_divider, hw));
829
-
kfree(container_of(composite->mux_hw, struct clk_mux, hw));
825
+
composite = to_clk_composite(__clk_get_hw(clk_data->clks[i]));
826
+
kfree(to_clk_gate(composite->gate_hw));
827
+
kfree(to_clk_divider(composite->rate_hw));
828
+
kfree(to_clk_mux(composite->mux_hw));
830
829
}
831
830
832
831
kfree(clk_data->clks);
-2
drivers/clk/ti/composite.c
-2
drivers/clk/ti/composite.c
-2
drivers/clk/ti/divider.c
-2
drivers/clk/ti/divider.c
-2
drivers/clk/ti/gate.c
-2
drivers/clk/ti/gate.c
-2
drivers/clk/ti/mux.c
-2
drivers/clk/ti/mux.c
+18
include/linux/clk-provider.h
+18
include/linux/clk-provider.h
···
276
276
u8 flags;
277
277
};
278
278
279
+
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
280
+
279
281
extern const struct clk_ops clk_fixed_rate_ops;
280
282
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
281
283
const char *parent_name, unsigned long flags,
···
315
313
u8 flags;
316
314
spinlock_t *lock;
317
315
};
316
+
317
+
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
318
318
319
319
#define CLK_GATE_SET_TO_DISABLE BIT(0)
320
320
#define CLK_GATE_HIWORD_MASK BIT(1)
···
379
375
const struct clk_div_table *table;
380
376
spinlock_t *lock;
381
377
};
378
+
379
+
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
382
380
383
381
#define CLK_DIVIDER_ONE_BASED BIT(0)
384
382
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
···
447
441
spinlock_t *lock;
448
442
};
449
443
444
+
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
445
+
450
446
#define CLK_MUX_INDEX_ONE BIT(0)
451
447
#define CLK_MUX_INDEX_BIT BIT(1)
452
448
#define CLK_MUX_HIWORD_MASK BIT(2)
···
492
484
unsigned int div;
493
485
};
494
486
487
+
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
488
+
495
489
extern const struct clk_ops clk_fixed_factor_ops;
496
490
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
497
491
const char *parent_name, unsigned long flags,
···
524
514
u8 flags;
525
515
spinlock_t *lock;
526
516
};
517
+
518
+
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
527
519
528
520
extern const struct clk_ops clk_fractional_divider_ops;
529
521
struct clk *clk_register_fractional_divider(struct device *dev,
···
563
551
spinlock_t *lock;
564
552
};
565
553
554
+
#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
555
+
566
556
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
567
557
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
568
558
···
594
580
const struct clk_ops *gate_ops;
595
581
};
596
582
583
+
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
584
+
597
585
struct clk *clk_register_composite(struct device *dev, const char *name,
598
586
const char * const *parent_names, int num_parents,
599
587
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
···
617
601
struct clk_hw hw;
618
602
struct gpio_desc *gpiod;
619
603
};
604
+
605
+
#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
620
606
621
607
extern const struct clk_ops clk_gpio_gate_ops;
622
608
struct clk *clk_register_gpio_gate(struct device *dev, const char *name,