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linux
ARM: dts: uniphier: add MIO DMAC nodes
Add MIO-DMAC (Media IO DMA Controller) nodes, and use them as
the DMA engine of SD/eMMC controllers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+44
+14
arch/arm/boot/dts/uniphier-ld4.dtsi
+14
arch/arm/boot/dts/uniphier-ld4.dtsi
···
235
235
};
236
236
};
237
237
238
+
dmac: dma-controller@5a000000 {
239
+
compatible = "socionext,uniphier-mio-dmac";
240
+
reg = <0x5a000000 0x1000>;
241
+
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
242
+
<0 71 4>, <0 72 4>, <0 73 4>;
243
+
clocks = <&mio_clk 7>;
244
+
resets = <&mio_rst 7>;
245
+
#dma-cells = <1>;
246
+
};
247
+
238
248
sd: sdhc@5a400000 {
239
249
compatible = "socionext,uniphier-sd-v2.91";
240
250
status = "disabled";
···
256
246
clocks = <&mio_clk 0>;
257
247
reset-names = "host", "bridge";
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248
resets = <&mio_rst 0>, <&mio_rst 3>;
249
+
dma-names = "rx-tx";
250
+
dmas = <&dmac 4>;
259
251
bus-width = <4>;
260
252
cap-sd-highspeed;
261
253
sd-uhs-sdr12;
···
275
263
clocks = <&mio_clk 1>;
276
264
reset-names = "host", "bridge", "hw";
277
265
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
266
+
dma-names = "rx-tx";
267
+
dmas = <&dmac 6>;
278
268
bus-width = <8>;
279
269
cap-mmc-highspeed;
280
270
cap-mmc-hw-reset;
+16
arch/arm/boot/dts/uniphier-pro4.dtsi
+16
arch/arm/boot/dts/uniphier-pro4.dtsi
···
269
269
};
270
270
};
271
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272
+
dmac: dma-controller@5a000000 {
273
+
compatible = "socionext,uniphier-mio-dmac";
274
+
reg = <0x5a000000 0x1000>;
275
+
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
276
+
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
277
+
clocks = <&mio_clk 7>;
278
+
resets = <&mio_rst 7>;
279
+
#dma-cells = <1>;
280
+
};
281
+
272
282
sd: sdhc@5a400000 {
273
283
compatible = "socionext,uniphier-sd-v2.91";
274
284
status = "disabled";
···
290
280
clocks = <&mio_clk 0>;
291
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reset-names = "host", "bridge";
292
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resets = <&mio_rst 0>, <&mio_rst 3>;
283
+
dma-names = "rx-tx";
284
+
dmas = <&dmac 4>;
293
285
bus-width = <4>;
294
286
cap-sd-highspeed;
295
287
sd-uhs-sdr12;
···
309
297
clocks = <&mio_clk 1>;
310
298
reset-names = "host", "bridge", "hw";
311
299
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
300
+
dma-names = "rx-tx";
301
+
dmas = <&dmac 5>;
312
302
bus-width = <8>;
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303
cap-mmc-highspeed;
314
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cap-mmc-hw-reset;
···
327
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clocks = <&mio_clk 2>;
328
314
reset-names = "host", "bridge";
329
315
resets = <&mio_rst 2>, <&mio_rst 5>;
316
+
dma-names = "rx-tx";
317
+
dmas = <&dmac 6>;
330
318
bus-width = <4>;
331
319
cap-sd-highspeed;
332
320
};
+14
arch/arm/boot/dts/uniphier-sld8.dtsi
+14
arch/arm/boot/dts/uniphier-sld8.dtsi
···
239
239
};
240
240
};
241
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242
+
dmac: dma-controller@5a000000 {
243
+
compatible = "socionext,uniphier-mio-dmac";
244
+
reg = <0x5a000000 0x1000>;
245
+
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
246
+
<0 71 4>, <0 72 4>, <0 73 4>;
247
+
clocks = <&mio_clk 7>;
248
+
resets = <&mio_rst 7>;
249
+
#dma-cells = <1>;
250
+
};
251
+
242
252
sd: sdhc@5a400000 {
243
253
compatible = "socionext,uniphier-sd-v2.91";
244
254
status = "disabled";
···
260
250
clocks = <&mio_clk 0>;
261
251
reset-names = "host", "bridge";
262
252
resets = <&mio_rst 0>, <&mio_rst 3>;
253
+
dma-names = "rx-tx";
254
+
dmas = <&dmac 4>;
263
255
bus-width = <4>;
264
256
cap-sd-highspeed;
265
257
sd-uhs-sdr12;
···
279
267
clocks = <&mio_clk 1>;
280
268
reset-names = "host", "bridge", "hw";
281
269
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
270
+
dma-names = "rx-tx";
271
+
dmas = <&dmac 6>;
282
272
bus-width = <8>;
283
273
cap-mmc-highspeed;
284
274
cap-mmc-hw-reset;