drm/amdgpu: Add hdp v7_0_0 ip headers (v3)

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

v1: Add hdp v7_0_0 register offset and shift masks
header files (Hawking)
v2: Update hdp v7_0_0 register offset and shift masks
header files for RE2.5 (Likun)
v3: Clean up hdp v7_0_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by

Alex Deucher 2 years ago 5fb2f479 56018e83

+954

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

hdp

hdp_7_0_0_offset.h

hdp_7_0_0_sh_mask.h

+219

drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_7_0_0_offset.h

+735

drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_7_0_0_sh_mask.h

··· 1 + /* 2 + * Copyright 2023 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _hdp_7_0_0_SH_MASK_HEADER 24 + #define _hdp_7_0_0_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: hdp_hdpdec 28 + //HDP_MMHUB_TLVL 29 + #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 30 + #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 31 + #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 32 + #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc 33 + #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 34 + #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x0000000FL 35 + #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x000000F0L 36 + #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000F00L 37 + #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x0000F000L 38 + #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x000F0000L 39 + //HDP_MMHUB_UNITID 40 + #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 41 + #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 42 + #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 43 + #define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL 44 + #define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L 45 + #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L 46 + //HDP_NONSURFACE_BASE 47 + #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 48 + #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 49 + //HDP_NONSURFACE_INFO 50 + #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 51 + #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 52 + #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 53 + #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 54 + //HDP_NONSURFACE_BASE_HI 55 + #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 56 + #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 57 + //HDP_SURFACE_WRITE_FLAGS 58 + #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 59 + #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 60 + #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L 61 + #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L 62 + //HDP_SURFACE_READ_FLAGS 63 + #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 64 + #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 65 + #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L 66 + #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L 67 + //HDP_SURFACE_WRITE_FLAGS_CLR 68 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 69 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 70 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L 71 + #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L 72 + //HDP_SURFACE_READ_FLAGS_CLR 73 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 74 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 75 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L 76 + #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L 77 + //HDP_NONSURF_FLAGS 78 + #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 79 + #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 80 + #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 81 + #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 82 + //HDP_NONSURF_FLAGS_CLR 83 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 84 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 85 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 86 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 87 + //HDP_SW_SEMAPHORE 88 + #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 89 + #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 90 + //HDP_DEBUG0 91 + #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 92 + #define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL 93 + //HDP_LAST_SURFACE_HIT 94 + #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 95 + #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 96 + //HDP_OUTSTANDING_REQ 97 + #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 98 + #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 99 + #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 100 + #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 101 + //HDP_HOST_PATH_CNTL 102 + #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 103 + #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 104 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 105 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 106 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 107 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 108 + #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 109 + #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 110 + #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 111 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 112 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 113 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 114 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 115 + #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 116 + //HDP_MISC_CNTL 117 + #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 118 + #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 119 + #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 120 + #define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE__SHIFT 0x9 121 + #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 122 + #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe 123 + #define HDP_MISC_CNTL__NACK_ENABLE__SHIFT 0x13 124 + #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14 125 + #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 126 + #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 127 + #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 128 + #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 129 + #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 130 + #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 131 + #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 132 + #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L 133 + #define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE_MASK 0x00000200L 134 + #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 135 + #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L 136 + #define HDP_MISC_CNTL__NACK_ENABLE_MASK 0x00080000L 137 + #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK 0x00100000L 138 + #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 139 + #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L 140 + #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L 141 + #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 142 + #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 143 + //HDP_MEM_POWER_CTRL 144 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT 0x0 145 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT 0x1 146 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT 0x2 147 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT 0x3 148 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT 0x4 149 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 150 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe 151 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 152 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 153 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 154 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 155 + #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 156 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 157 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e 158 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK 0x00000001L 159 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK 0x00000002L 160 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK 0x00000004L 161 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK 0x00000008L 162 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 163 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 164 + #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L 165 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 166 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 167 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L 168 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L 169 + #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 170 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 171 + #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L 172 + //HDP_CLK_CNTL 173 + #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 174 + #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 175 + #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b 176 + #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 177 + #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 178 + #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 179 + #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 180 + #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 181 + #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 182 + #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L 183 + #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 184 + #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 185 + #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 186 + #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 187 + //HDP_MMHUB_CNTL 188 + #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 189 + #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 190 + #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 191 + #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT 0x4 192 + #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE__SHIFT 0x5 193 + #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE__SHIFT 0x6 194 + #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 195 + #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 196 + #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 197 + #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK 0x00000010L 198 + #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE_MASK 0x00000020L 199 + #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE_MASK 0x00000040L 200 + //HDP_XDP_BUSY_STS 201 + #define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT 0x0 202 + #define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT 0x1 203 + #define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT 0x2 204 + #define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT 0x3 205 + #define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT 0x4 206 + #define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT 0x5 207 + #define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT 0x6 208 + #define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT 0x7 209 + #define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT 0x8 210 + #define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT 0x9 211 + #define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT 0xa 212 + #define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT 0xb 213 + #define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT 0xc 214 + #define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT 0xd 215 + #define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe 216 + #define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT 0xf 217 + #define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT 0x10 218 + #define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT 0x11 219 + #define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT 0x12 220 + #define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT 0x13 221 + #define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT 0x14 222 + #define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT 0x15 223 + #define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT 0x16 224 + #define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT 0x17 225 + #define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT 0x18 226 + #define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK 0x00000001L 227 + #define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK 0x00000002L 228 + #define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK 0x00000004L 229 + #define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK 0x00000008L 230 + #define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK 0x00000010L 231 + #define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK 0x00000020L 232 + #define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK 0x00000040L 233 + #define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK 0x00000080L 234 + #define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK 0x00000100L 235 + #define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK 0x00000200L 236 + #define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK 0x00000400L 237 + #define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK 0x00000800L 238 + #define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK 0x00001000L 239 + #define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK 0x00002000L 240 + #define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK 0x00004000L 241 + #define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK 0x00008000L 242 + #define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK 0x00010000L 243 + #define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK 0x00020000L 244 + #define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK 0x00040000L 245 + #define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK 0x00080000L 246 + #define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK 0x00100000L 247 + #define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK 0x00200000L 248 + #define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK 0x00400000L 249 + #define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK 0x00800000L 250 + #define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK 0x01000000L 251 + //HDP_XDP_MMHUB_ERROR 252 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 253 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 254 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 255 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 256 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 257 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 258 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 259 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 260 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 261 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 262 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 263 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 264 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 265 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 266 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 267 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 268 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 269 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 270 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 271 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 272 + #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 273 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 274 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 275 + #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 276 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 277 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 278 + #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 279 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 280 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 281 + #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 282 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 283 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 284 + #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 285 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 286 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 287 + #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 288 + //HDP_XDP_MMHUB_ERROR_CLR 289 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_01_CLR__SHIFT 0x1 290 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_10_CLR__SHIFT 0x2 291 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_11_CLR__SHIFT 0x3 292 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_FED_CLR__SHIFT 0x4 293 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_01_CLR__SHIFT 0x5 294 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_10_CLR__SHIFT 0x6 295 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_11_CLR__SHIFT 0x7 296 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_01_CLR__SHIFT 0x9 297 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_10_CLR__SHIFT 0xa 298 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_11_CLR__SHIFT 0xb 299 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_FED_CLR__SHIFT 0xc 300 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_01_CLR__SHIFT 0xd 301 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR__SHIFT 0xe 302 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_11_CLR__SHIFT 0xf 303 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_WUSER_FED_CLR__SHIFT 0x10 304 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_01_CLR__SHIFT 0x11 305 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_10_CLR__SHIFT 0x12 306 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_11_CLR__SHIFT 0x13 307 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_01_CLR__SHIFT 0x15 308 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_10_CLR__SHIFT 0x16 309 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_11_CLR__SHIFT 0x17 310 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_01_CLR_MASK 0x00000002L 311 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_10_CLR_MASK 0x00000004L 312 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_11_CLR_MASK 0x00000008L 313 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_FED_CLR_MASK 0x00000010L 314 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_01_CLR_MASK 0x00000020L 315 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_10_CLR_MASK 0x00000040L 316 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_11_CLR_MASK 0x00000080L 317 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_01_CLR_MASK 0x00000200L 318 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_10_CLR_MASK 0x00000400L 319 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_11_CLR_MASK 0x00000800L 320 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_FED_CLR_MASK 0x00001000L 321 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_01_CLR_MASK 0x00002000L 322 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR_MASK 0x00004000L 323 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_11_CLR_MASK 0x00008000L 324 + #define HDP_XDP_MMHUB_ERROR_CLR__HDP_WUSER_FED_CLR_MASK 0x00010000L 325 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_01_CLR_MASK 0x00020000L 326 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_10_CLR_MASK 0x00040000L 327 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_11_CLR_MASK 0x00080000L 328 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_01_CLR_MASK 0x00200000L 329 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_10_CLR_MASK 0x00400000L 330 + #define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_11_CLR_MASK 0x00800000L 331 + //HDP_VERSION 332 + #define HDP_VERSION__MINVER__SHIFT 0x0 333 + #define HDP_VERSION__MAJVER__SHIFT 0x8 334 + #define HDP_VERSION__REV__SHIFT 0x10 335 + #define HDP_VERSION__MINVER_MASK 0x000000FFL 336 + #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 337 + #define HDP_VERSION__REV_MASK 0x00FF0000L 338 + //HDP_MEMIO_CNTL 339 + #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 340 + #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 341 + #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 342 + #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 343 + #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 344 + #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 345 + #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 346 + #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 347 + #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 348 + #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 349 + #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 350 + #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 351 + #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 352 + #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 353 + #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 354 + #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 355 + #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 356 + #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 357 + #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 358 + #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 359 + //HDP_MEMIO_ADDR 360 + #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 361 + #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 362 + //HDP_MEMIO_STATUS 363 + #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 364 + #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 365 + #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 366 + #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 367 + #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 368 + #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 369 + #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 370 + #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 371 + //HDP_MEMIO_WR_DATA 372 + #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 373 + #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 374 + //HDP_MEMIO_RD_DATA 375 + #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 376 + #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 377 + //HDP_XDP_DIRECT2HDP_FIRST 378 + #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 379 + #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 380 + //HDP_XDP_D2H_FLUSH 381 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 382 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 383 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 384 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 385 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 386 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 387 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 388 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 389 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 390 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 391 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 392 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 393 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 394 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 395 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 396 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 397 + //HDP_XDP_D2H_BAR_UPDATE 398 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 399 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 400 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 401 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 402 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 403 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 404 + //HDP_XDP_D2H_RSVD_3 405 + #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 406 + #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 407 + //HDP_XDP_D2H_RSVD_4 408 + #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 409 + #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 410 + //HDP_XDP_D2H_RSVD_5 411 + #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 412 + #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 413 + //HDP_XDP_D2H_RSVD_6 414 + #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 415 + #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 416 + //HDP_XDP_D2H_RSVD_7 417 + #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 418 + #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 419 + //HDP_XDP_D2H_RSVD_8 420 + #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 421 + #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 422 + //HDP_XDP_D2H_RSVD_9 423 + #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 424 + #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 425 + //HDP_XDP_D2H_RSVD_10 426 + #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 427 + #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 428 + //HDP_XDP_D2H_RSVD_11 429 + #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 430 + #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 431 + //HDP_XDP_D2H_RSVD_12 432 + #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 433 + #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 434 + //HDP_XDP_D2H_RSVD_13 435 + #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 436 + #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 437 + //HDP_XDP_D2H_RSVD_14 438 + #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 439 + #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 440 + //HDP_XDP_D2H_RSVD_15 441 + #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 442 + #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 443 + //HDP_XDP_D2H_RSVD_16 444 + #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 445 + #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 446 + //HDP_XDP_D2H_RSVD_17 447 + #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 448 + #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 449 + //HDP_XDP_D2H_RSVD_18 450 + #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 451 + #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 452 + //HDP_XDP_D2H_RSVD_19 453 + #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 454 + #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 455 + //HDP_XDP_D2H_RSVD_20 456 + #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 457 + #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 458 + //HDP_XDP_D2H_RSVD_21 459 + #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 460 + #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 461 + //HDP_XDP_D2H_RSVD_22 462 + #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 463 + #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 464 + //HDP_XDP_D2H_RSVD_23 465 + #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 466 + #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 467 + //HDP_XDP_D2H_RSVD_24 468 + #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 469 + #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 470 + //HDP_XDP_D2H_RSVD_25 471 + #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 472 + #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 473 + //HDP_XDP_D2H_RSVD_26 474 + #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 475 + #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 476 + //HDP_XDP_D2H_RSVD_27 477 + #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 478 + #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 479 + //HDP_XDP_D2H_RSVD_28 480 + #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 481 + #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 482 + //HDP_XDP_D2H_RSVD_29 483 + #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 484 + #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 485 + //HDP_XDP_D2H_RSVD_30 486 + #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 487 + #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 488 + //HDP_XDP_D2H_RSVD_31 489 + #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 490 + #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 491 + //HDP_XDP_D2H_RSVD_32 492 + #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 493 + #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 494 + //HDP_XDP_D2H_RSVD_33 495 + #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 496 + #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 497 + //HDP_XDP_D2H_RSVD_34 498 + #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 499 + #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 500 + //HDP_XDP_DIRECT2HDP_LAST 501 + #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 502 + #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 503 + //HDP_XDP_P2P_BAR_CFG 504 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 505 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 506 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 507 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 508 + //HDP_XDP_P2P_MBX_OFFSET 509 + #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 510 + #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 511 + //HDP_XDP_P2P_MBX_ADDR0 512 + #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 513 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 514 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 515 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 516 + #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 517 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 518 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 519 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 520 + //HDP_XDP_P2P_MBX_ADDR1 521 + #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 522 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 523 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 524 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 525 + #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 526 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 527 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 528 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 529 + //HDP_XDP_P2P_MBX_ADDR2 530 + #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 531 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 532 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 533 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 534 + #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 535 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 536 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 537 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 538 + //HDP_XDP_P2P_MBX_ADDR3 539 + #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 540 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 541 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 542 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 543 + #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 544 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 545 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 546 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 547 + //HDP_XDP_P2P_MBX_ADDR4 548 + #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 549 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 550 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 551 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 552 + #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 553 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 554 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 555 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 556 + //HDP_XDP_P2P_MBX_ADDR5 557 + #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 558 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 559 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 560 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 561 + #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 562 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 563 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 564 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 565 + //HDP_XDP_P2P_MBX_ADDR6 566 + #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 567 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 568 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 569 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 570 + #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 571 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 572 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 573 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 574 + //HDP_XDP_HDP_MBX_MC_CFG 575 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 576 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 577 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 578 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 579 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 580 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 581 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 582 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 583 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 584 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 585 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 586 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 587 + //HDP_XDP_HDP_MC_CFG 588 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE__SHIFT 0x0 589 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE__SHIFT 0x1 590 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE__SHIFT 0x2 591 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 592 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 593 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 594 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 595 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 596 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 597 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE_MASK 0x00000001L 598 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE_MASK 0x00000002L 599 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE_MASK 0x00000004L 600 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 601 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 602 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 603 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 604 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 605 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 606 + //HDP_XDP_HST_CFG 607 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 608 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 609 + #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 610 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 611 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 612 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 613 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 614 + #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 615 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 616 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 617 + //HDP_XDP_HDP_IPH_CFG 618 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 619 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 620 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 621 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 622 + //HDP_XDP_P2P_BAR0 623 + #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 624 + #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 625 + #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 626 + #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 627 + #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 628 + #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 629 + //HDP_XDP_P2P_BAR1 630 + #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 631 + #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 632 + #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 633 + #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 634 + #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 635 + #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 636 + //HDP_XDP_P2P_BAR2 637 + #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 638 + #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 639 + #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 640 + #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 641 + #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 642 + #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 643 + //HDP_XDP_P2P_BAR3 644 + #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 645 + #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 646 + #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 647 + #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 648 + #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 649 + #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 650 + //HDP_XDP_P2P_BAR4 651 + #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 652 + #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 653 + #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 654 + #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 655 + #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 656 + #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 657 + //HDP_XDP_P2P_BAR5 658 + #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 659 + #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 660 + #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 661 + #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 662 + #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 663 + #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 664 + //HDP_XDP_P2P_BAR6 665 + #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 666 + #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 667 + #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 668 + #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 669 + #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 670 + #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 671 + //HDP_XDP_P2P_BAR7 672 + #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 673 + #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 674 + #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 675 + #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 676 + #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 677 + #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 678 + //HDP_XDP_FLUSH_ARMED_STS 679 + #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 680 + #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 681 + //HDP_XDP_FLUSH_CNTR0_STS 682 + #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 683 + #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 684 + //HDP_XDP_STICKY 685 + #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 686 + #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 687 + #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 688 + #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 689 + //HDP_XDP_CHKN 690 + #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 691 + #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 692 + #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 693 + #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 694 + #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 695 + #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 696 + #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 697 + #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 698 + //HDP_XDP_BARS_ADDR_39_36 699 + #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 700 + #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 701 + #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 702 + #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 703 + #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 704 + #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 705 + #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 706 + #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 707 + #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 708 + #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 709 + #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 710 + #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 711 + #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 712 + #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 713 + #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 714 + #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 715 + //HDP_XDP_MC_VM_FB_LOCATION_BASE 716 + #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 717 + #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 718 + //HDP_XDP_GPU_IOV_VIOLATION_LOG 719 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 720 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 721 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 722 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 723 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 724 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 725 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 726 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 727 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 728 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 729 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 730 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x01F00000L 731 + //HDP_XDP_GPU_IOV_VIOLATION_LOG2 732 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 733 + #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 734 + 735 + #endif