ARM: OMAP: Add 24xx GPIO debounce support

Add 24xx GPIO debounce support. Also minor formatting
clean-up.

Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

authored by Kevin Hilman and committed by Tony Lindgren 5eb3bb9c d11ac979

+57 -5
+55 -5
arch/arm/plat-omap/gpio.c
··· 110 110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 111 111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048 112 112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c 113 + #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 114 + #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 113 115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 114 116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 115 117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 ··· 465 463 __raw_writel(l, base + reg); \ 466 464 } while(0) 467 465 466 + void omap_set_gpio_debounce(int gpio, int enable) 467 + { 468 + struct gpio_bank *bank; 469 + void __iomem *reg; 470 + u32 val, l = 1 << get_gpio_index(gpio); 471 + 472 + if (cpu_class_is_omap1()) 473 + return; 474 + 475 + bank = get_gpio_bank(gpio); 476 + reg = bank->base; 477 + 478 + reg += OMAP24XX_GPIO_DEBOUNCE_EN; 479 + val = __raw_readl(reg); 480 + 481 + if (enable) 482 + val |= l; 483 + else 484 + val &= ~l; 485 + 486 + __raw_writel(val, reg); 487 + } 488 + EXPORT_SYMBOL(omap_set_gpio_debounce); 489 + 490 + void omap_set_gpio_debounce_time(int gpio, int enc_time) 491 + { 492 + struct gpio_bank *bank; 493 + void __iomem *reg; 494 + 495 + if (cpu_class_is_omap1()) 496 + return; 497 + 498 + bank = get_gpio_bank(gpio); 499 + reg = bank->base; 500 + 501 + enc_time &= 0xff; 502 + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 503 + __raw_writel(enc_time, reg); 504 + } 505 + EXPORT_SYMBOL(omap_set_gpio_debounce_time); 506 + 468 507 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 469 - static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 508 + static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, 509 + int trigger) 470 510 { 471 511 void __iomem *base = bank->base; 472 512 u32 gpio_bit = 1 << gpio; ··· 521 477 trigger & __IRQT_RISEDGE); 522 478 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 523 479 trigger & __IRQT_FALEDGE); 480 + 524 481 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 525 482 if (trigger != 0) 526 - __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); 483 + __raw_writel(1 << gpio, bank->base 484 + + OMAP24XX_GPIO_SETWKUENA); 527 485 else 528 - __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); 486 + __raw_writel(1 << gpio, bank->base 487 + + OMAP24XX_GPIO_CLEARWKUENA); 529 488 } else { 530 489 if (trigger != 0) 531 490 bank->enabled_non_wakeup_gpios |= gpio_bit; 532 491 else 533 492 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 534 493 } 535 - /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level 536 - * triggering requested. */ 494 + 495 + /* 496 + * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only 497 + * level triggering requested. 498 + */ 537 499 } 538 500 #endif 539 501
+2
include/asm-arm/arch-omap/gpio.h
··· 77 77 extern void omap_set_gpio_direction(int gpio, int is_input); 78 78 extern void omap_set_gpio_dataout(int gpio, int enable); 79 79 extern int omap_get_gpio_datain(int gpio); 80 + extern void omap_set_gpio_debounce(int gpio, int enable); 81 + extern void omap_set_gpio_debounce_time(int gpio, int enable); 80 82 81 83 /*-------------------------------------------------------------------------*/ 82 84