tjh.dev / kernel
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drm/i915/display: use x100 version for full version and release

Use x100, or ver * 100 + rel, versions for full IP version checks,
similar to what xe driver does:

- Replace IP_VER(14, 1) inline with 1401, etc.

- Convert DISPLAY_VER_FULL() to DISPLAY_VERx100()

- Convert IS_DISPLAY_VER_FULL() to IS_DISPLAY_VERx100()

- Convert IS_DISPLAY_VER_STEP() to IS_DISPLAY_VERx100_STEP()

This makes ver.rel versions easier to use, follows the xe driver
pattern, and drops the dependency on the IP_VER() macro.

v2: Rebase, drop IP_VER() from xe compat headers

v3: Rebase

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029155536.753413-1-jani.nikula@intel.com

Jani Nikula 5eb2e785 3291b741

+36 -38
+2 -2
drivers/gpu/drm/i915/display/intel_atomic_plane.c
··· 1026 1026 vsub = 1; 1027 1027 1028 1028 /* Wa_16023981245 */ 1029 - if ((DISPLAY_VER_FULL(i915) == IP_VER(20, 0) || 1030 - DISPLAY_VER_FULL(i915) == IP_VER(30, 0)) && 1029 + if ((DISPLAY_VERx100(i915) == 2000 || 1030 + DISPLAY_VERx100(i915) == 3000) && 1031 1031 src_x % 2 != 0) 1032 1032 hsub = 2; 1033 1033 } else {
+1 -1
drivers/gpu/drm/i915/display/intel_bw.c
··· 743 743 if (!HAS_DISPLAY(dev_priv)) 744 744 return; 745 745 746 - if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv)) 746 + if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv)) 747 747 xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info); 748 748 else if (DISPLAY_VER(dev_priv) >= 14) 749 749 tgl_get_bw_info(dev_priv, &mtl_sa_info);
+3 -3
drivers/gpu/drm/i915/display/intel_cdclk.c
··· 2058 2058 { 2059 2059 struct drm_i915_private *dev_priv = to_i915(display->drm); 2060 2060 2061 - return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) || 2062 - DISPLAY_VER_FULL(display) == IP_VER(14, 0) || 2061 + return (DISPLAY_VERx100(display) == 2000 || 2062 + DISPLAY_VERx100(display) == 1400 || 2063 2063 IS_DG2(dev_priv)) && 2064 2064 display->cdclk.hw.vco > 0; 2065 2065 } ··· 3852 3852 } else if (DISPLAY_VER(display) >= 20) { 3853 3853 display->funcs.cdclk = &rplu_cdclk_funcs; 3854 3854 display->cdclk.table = xe2lpd_cdclk_table; 3855 - } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) { 3855 + } else if (DISPLAY_VERx100(display) >= 1401) { 3856 3856 display->funcs.cdclk = &rplu_cdclk_funcs; 3857 3857 display->cdclk.table = xe2hpd_cdclk_table; 3858 3858 } else if (DISPLAY_VER(display) >= 14) {
+2 -2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 2286 2286 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 2287 2287 if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support) 2288 2288 return xe3lpd_c20_dp_edp_tables; 2289 - if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) 2289 + if (DISPLAY_VERx100(display) == 1401) 2290 2290 return xe2hpd_c20_edp_tables; 2291 2291 } 2292 2292 2293 2293 if (DISPLAY_VER(display) >= 30) 2294 2294 return xe3lpd_c20_dp_edp_tables; 2295 - else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) 2295 + else if (DISPLAY_VERx100(display) == 1401) 2296 2296 return xe2hpd_c20_dp_tables; 2297 2297 else 2298 2298 return mtl_c20_dp_tables;
+1 -1
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
··· 273 273 #define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 274 274 #define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 275 275 276 - #define _IS_XE2HPD_C20(i915) (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) 276 + #define _IS_XE2HPD_C20(i915) (DISPLAY_VERx100(i915) == 1401) 277 277 278 278 #define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ 279 279 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx))
+10 -10
drivers/gpu/drm/i915/display/intel_display_device.h
··· 186 186 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 187 187 188 188 /* Check that device has a display IP version within the specific range. */ 189 - #define IS_DISPLAY_VER_FULL(__i915, from, until) ( \ 190 - BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 191 - (DISPLAY_VER_FULL(__i915) >= (from) && \ 192 - DISPLAY_VER_FULL(__i915) <= (until))) 189 + #define IS_DISPLAY_VERx100(__i915, from, until) ( \ 190 + BUILD_BUG_ON_ZERO((from) < 200) + \ 191 + (DISPLAY_VERx100(__i915) >= (from) && \ 192 + DISPLAY_VERx100(__i915) <= (until))) 193 193 194 194 /* 195 195 * Check if a device has a specific IP version as well as a stepping within the ··· 200 200 * hardware fix is present and the software workaround is no longer necessary. 201 201 * E.g., 202 202 * 203 - * IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2) 204 - * IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER) 203 + * IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_B2) 204 + * IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_C0, STEP_FOREVER) 205 205 * 206 206 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 207 207 * stepping bound for the specified IP version. 208 208 */ 209 - #define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \ 210 - (IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \ 209 + #define IS_DISPLAY_VERx100_STEP(__i915, ipver, from, until) \ 210 + (IS_DISPLAY_VERx100((__i915), (ipver), (ipver)) && \ 211 211 IS_DISPLAY_STEP((__i915), (from), (until))) 212 212 213 213 #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) 214 214 #define DISPLAY_RUNTIME_INFO(i915) (&__to_intel_display(i915)->info.__runtime_info) 215 215 216 216 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 217 - #define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ 218 - DISPLAY_RUNTIME_INFO(i915)->ip.rel) 217 + #define DISPLAY_VERx100(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver * 100 + \ 218 + DISPLAY_RUNTIME_INFO(i915)->ip.rel) 219 219 #define IS_DISPLAY_VER(i915, from, until) \ 220 220 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 221 221
+2 -2
drivers/gpu/drm/i915/display/intel_display_power.c
··· 1684 1684 intel_snps_phy_wait_for_calibration(dev_priv); 1685 1685 1686 1686 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1687 - if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) 1687 + if (DISPLAY_VERx100(dev_priv) == 1401) 1688 1688 intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1689 1689 1690 1690 if (resume) 1691 1691 intel_dmc_load_program(display); 1692 1692 1693 1693 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1694 - if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0))) 1694 + if (IS_DISPLAY_VERx100(dev_priv, 1200, 1300)) 1695 1695 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, 1696 1696 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1697 1697 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);
+4 -4
drivers/gpu/drm/i915/display/intel_dmc.c
··· 171 171 const char *fw_path = NULL; 172 172 u32 max_fw_size = 0; 173 173 174 - if (DISPLAY_VER_FULL(display) == IP_VER(30, 0)) { 174 + if (DISPLAY_VERx100(display) == 3000) { 175 175 fw_path = XE3LPD_DMC_PATH; 176 176 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 177 - } else if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) { 177 + } else if (DISPLAY_VERx100(display) == 2000) { 178 178 fw_path = XE2LPD_DMC_PATH; 179 179 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 180 - } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) { 180 + } else if (DISPLAY_VERx100(display) == 1401) { 181 181 fw_path = BMG_DMC_PATH; 182 182 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 183 - } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) { 183 + } else if (DISPLAY_VERx100(display) == 1400) { 184 184 fw_path = MTL_DMC_PATH; 185 185 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 186 186 } else if (IS_DG2(i915)) {
+1 -1
drivers/gpu/drm/i915/display/intel_dp.c
··· 497 497 if (intel_encoder_is_c10phy(encoder)) 498 498 return 810000; 499 499 500 - if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) 500 + if (DISPLAY_VERx100(to_i915(encoder->base.dev)) == 1401) 501 501 return 1350000; 502 502 503 503 return 2000000;
+1 -1
drivers/gpu/drm/i915/display/intel_fbc.c
··· 1347 1347 1348 1348 /* Wa_14016291713 */ 1349 1349 if ((IS_DISPLAY_VER(display, 12, 13) || 1350 - IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) && 1350 + IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0)) && 1351 1351 crtc_state->has_psr && !crtc_state->has_panel_replay) { 1352 1352 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; 1353 1353 return 0;
+3 -3
drivers/gpu/drm/i915/display/intel_hdcp.c
··· 43 43 return; 44 44 45 45 if (DISPLAY_VER(display) >= 14) { 46 - if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_D0, STEP_FOREVER)) 46 + if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) 47 47 intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), 48 48 0, HDCP_LINE_REKEY_DISABLE); 49 - else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || 50 - IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) 49 + else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 50 + IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) 51 51 intel_de_rmw(display, 52 52 TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), 53 53 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);
+1 -1
drivers/gpu/drm/i915/display/intel_pmdemand.c
··· 92 92 &pmdemand_state->base, 93 93 &intel_pmdemand_funcs); 94 94 95 - if (IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) 95 + if (IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0)) 96 96 /* Wa_14016740474 */ 97 97 intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); 98 98
+4 -4
drivers/gpu/drm/i915/display/intel_psr.c
··· 1918 1918 * cause issues if non-supported panels are used. 1919 1919 */ 1920 1920 if (!intel_dp->psr.panel_replay_enabled && 1921 - (IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0) || 1921 + (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 1922 1922 IS_ALDERLAKE_P(dev_priv))) 1923 1923 intel_de_rmw(display, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 1924 1924 0, ADLP_1_BASED_X_GRANULARITY); 1925 1925 1926 1926 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1927 1927 if (!intel_dp->psr.panel_replay_enabled && 1928 - IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0)) 1928 + IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 1929 1929 intel_de_rmw(display, 1930 1930 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 1931 1931 0, ··· 2110 2110 if (intel_dp->psr.sel_update_enabled) { 2111 2111 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2112 2112 if (!intel_dp->psr.panel_replay_enabled && 2113 - IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0)) 2113 + IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2114 2114 intel_de_rmw(display, 2115 2115 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2116 2116 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); ··· 2565 2565 2566 2566 /* Wa_14014971492 */ 2567 2567 if (!crtc_state->has_panel_replay && 2568 - ((IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0) || 2568 + ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2569 2569 IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && 2570 2570 crtc_state->splitter.enable) 2571 2571 crtc_state->psr2_su_area.y1 = 0;
+1 -1
drivers/gpu/drm/i915/display/skl_watermark.c
··· 3533 3533 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) { 3534 3534 u32 pipe_val = val; 3535 3535 3536 - if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { 3536 + if (DISPLAY_VERx100(i915) == 1400) { 3537 3537 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, 3538 3538 new_dbuf_state->active_pipes)) 3539 3539 pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
-2
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
··· 73 73 #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) 74 74 #define IS_BROADWELL_ULX(dev_priv) (dev_priv && 0) 75 75 76 - #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 77 - 78 76 #define IS_MOBILE(xe) (xe && 0) 79 77 80 78 #define IS_TIGERLAKE_UY(xe) (xe && 0)