[SPARC64]: Fix trap state reading for instruction_access_exception.

1) Read ASI_IMMU SFSR not ASI_DMMU.
2) IMMU has no SFAR, read TPC instead
3) Delete old and incorrect comment about the DTLB protection
trap having a dependency on the SFSR contents in order to
function correctly

Signed-off-by: David S. Miller <davem@davemloft.net>

+4 -11
+4 -11
arch/sparc64/kernel/entry.S
··· 690 690 retl 691 691 nop 692 692 693 - /* These next few routines must be sure to clear the 694 - * SFSR FaultValid bit so that the fast tlb data protection 695 - * handler does not flush the wrong context and lock up the 696 - * box. 697 - */ 698 693 .globl __do_data_access_exception 699 694 .globl __do_data_access_exception_tl1 700 695 __do_data_access_exception_tl1: ··· 728 733 rdpr %pstate, %g4 729 734 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate 730 735 mov TLB_SFSR, %g3 731 - mov DMMU_SFAR, %g5 732 - ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR 733 - ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR 736 + ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR 737 + rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC 734 738 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit 735 739 membar #Sync 736 740 sethi %hi(109f), %g7 ··· 746 752 rdpr %pstate, %g4 747 753 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate 748 754 mov TLB_SFSR, %g3 749 - mov DMMU_SFAR, %g5 750 - ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR 751 - ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR 755 + ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR 756 + rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC 752 757 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit 753 758 membar #Sync 754 759 sethi %hi(109f), %g7