tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: add RT5670 CODEC driver
This patch adds a minimum support of Realtek ALC5670 codec.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
authored by
Bard Liao
and committed by
Mark Brown
5e8351de
099d334e
+4781
+27
include/sound/rt5670.h
+27
include/sound/rt5670.h
···
1
+
/*
2
+
* linux/sound/rt5670.h -- Platform data for RT5670
3
+
*
4
+
* Copyright 2014 Realtek Microelectronics
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
#ifndef __LINUX_SND_RT5670_H
12
+
#define __LINUX_SND_RT5670_H
13
+
14
+
struct rt5670_platform_data {
15
+
int jd_mode;
16
+
bool in2_diff;
17
+
18
+
bool dmic_en;
19
+
unsigned int dmic1_data_pin;
20
+
/* 0 = GPIO6; 1 = IN2P; 3 = GPIO7*/
21
+
unsigned int dmic2_data_pin;
22
+
/* 0 = GPIO8; 1 = IN3N; */
23
+
unsigned int dmic3_data_pin;
24
+
/* 0 = GPIO9; 1 = GPIO10; 2 = GPIO5*/
25
+
};
26
+
27
+
#endif
+6
sound/soc/codecs/Kconfig
+6
sound/soc/codecs/Kconfig
···
78
78
select SND_SOC_RT5640 if I2C
79
79
select SND_SOC_RT5645 if I2C
80
80
select SND_SOC_RT5651 if I2C
81
+
select SND_SOC_RT5670 if I2C
81
82
select SND_SOC_RT5677 if I2C
82
83
select SND_SOC_SGTL5000 if I2C
83
84
select SND_SOC_SI476X if MFD_SI476X_CORE
···
446
445
default y if SND_SOC_RT5640=y
447
446
default y if SND_SOC_RT5645=y
448
447
default y if SND_SOC_RT5651=y
448
+
default y if SND_SOC_RT5670=y
449
449
default y if SND_SOC_RT5677=y
450
450
default m if SND_SOC_RT5640=m
451
451
default m if SND_SOC_RT5645=m
452
452
default m if SND_SOC_RT5651=m
453
+
default m if SND_SOC_RT5670=m
453
454
default m if SND_SOC_RT5677=m
454
455
455
456
config SND_SOC_RT5631
···
464
461
tristate
465
462
466
463
config SND_SOC_RT5651
464
+
tristate
465
+
466
+
config SND_SOC_RT5670
467
467
tristate
468
468
469
469
config SND_SOC_RT5677
+2
sound/soc/codecs/Makefile
+2
sound/soc/codecs/Makefile
···
72
72
snd-soc-rt5640-objs := rt5640.o
73
73
snd-soc-rt5645-objs := rt5645.o
74
74
snd-soc-rt5651-objs := rt5651.o
75
+
snd-soc-rt5670-objs := rt5670.o
75
76
snd-soc-rt5677-objs := rt5677.o
76
77
snd-soc-sgtl5000-objs := sgtl5000.o
77
78
snd-soc-alc5623-objs := alc5623.o
···
238
237
obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
239
238
obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
240
239
obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
240
+
obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
241
241
obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
242
242
obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
243
243
obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
+54
sound/soc/codecs/rt5670-dsp.h
+54
sound/soc/codecs/rt5670-dsp.h
···
1
+
/*
2
+
* rt5670-dsp.h -- RT5670 ALSA SoC DSP driver
3
+
*
4
+
* Copyright 2014 Realtek Microelectronics
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#ifndef __RT5670_DSP_H__
13
+
#define __RT5670_DSP_H__
14
+
15
+
#define RT5670_DSP_CTRL1 0xe0
16
+
#define RT5670_DSP_CTRL2 0xe1
17
+
#define RT5670_DSP_CTRL3 0xe2
18
+
#define RT5670_DSP_CTRL4 0xe3
19
+
#define RT5670_DSP_CTRL5 0xe4
20
+
21
+
/* DSP Control 1 (0xe0) */
22
+
#define RT5670_DSP_CMD_MASK (0xff << 8)
23
+
#define RT5670_DSP_CMD_PE (0x0d << 8) /* Patch Entry */
24
+
#define RT5670_DSP_CMD_MW (0x3b << 8) /* Memory Write */
25
+
#define RT5670_DSP_CMD_MR (0x37 << 8) /* Memory Read */
26
+
#define RT5670_DSP_CMD_RR (0x60 << 8) /* Register Read */
27
+
#define RT5670_DSP_CMD_RW (0x68 << 8) /* Register Write */
28
+
#define RT5670_DSP_REG_DATHI (0x26 << 8) /* High Data Addr */
29
+
#define RT5670_DSP_REG_DATLO (0x25 << 8) /* Low Data Addr */
30
+
#define RT5670_DSP_CLK_MASK (0x3 << 6)
31
+
#define RT5670_DSP_CLK_SFT 6
32
+
#define RT5670_DSP_CLK_768K (0x0 << 6)
33
+
#define RT5670_DSP_CLK_384K (0x1 << 6)
34
+
#define RT5670_DSP_CLK_192K (0x2 << 6)
35
+
#define RT5670_DSP_CLK_96K (0x3 << 6)
36
+
#define RT5670_DSP_BUSY_MASK (0x1 << 5)
37
+
#define RT5670_DSP_RW_MASK (0x1 << 4)
38
+
#define RT5670_DSP_DL_MASK (0x3 << 2)
39
+
#define RT5670_DSP_DL_0 (0x0 << 2)
40
+
#define RT5670_DSP_DL_1 (0x1 << 2)
41
+
#define RT5670_DSP_DL_2 (0x2 << 2)
42
+
#define RT5670_DSP_DL_3 (0x3 << 2)
43
+
#define RT5670_DSP_I2C_AL_16 (0x1 << 1)
44
+
#define RT5670_DSP_CMD_EN (0x1)
45
+
46
+
struct rt5670_dsp_param {
47
+
u16 cmd_fmt;
48
+
u16 addr;
49
+
u16 data;
50
+
u8 cmd;
51
+
};
52
+
53
+
#endif /* __RT5670_DSP_H__ */
54
+
+2692
sound/soc/codecs/rt5670.c
+2692
sound/soc/codecs/rt5670.c
···
1
+
/*
2
+
* rt5670.c -- RT5670 ALSA SoC audio codec driver
3
+
*
4
+
* Copyright 2014 Realtek Semiconductor Corp.
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/moduleparam.h>
14
+
#include <linux/init.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/pm.h>
17
+
#include <linux/i2c.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/spi/spi.h>
20
+
#include <sound/core.h>
21
+
#include <sound/pcm.h>
22
+
#include <sound/pcm_params.h>
23
+
#include <sound/jack.h>
24
+
#include <sound/soc.h>
25
+
#include <sound/soc-dapm.h>
26
+
#include <sound/initval.h>
27
+
#include <sound/tlv.h>
28
+
#include <sound/rt5670.h>
29
+
30
+
#include "rl6231.h"
31
+
#include "rt5670.h"
32
+
#include "rt5670-dsp.h"
33
+
34
+
#define RT5670_DEVICE_ID 0x6271
35
+
36
+
#define RT5670_PR_RANGE_BASE (0xff + 1)
37
+
#define RT5670_PR_SPACING 0x100
38
+
39
+
#define RT5670_PR_BASE (RT5670_PR_RANGE_BASE + (0 * RT5670_PR_SPACING))
40
+
41
+
static const struct regmap_range_cfg rt5670_ranges[] = {
42
+
{ .name = "PR", .range_min = RT5670_PR_BASE,
43
+
.range_max = RT5670_PR_BASE + 0xf8,
44
+
.selector_reg = RT5670_PRIV_INDEX,
45
+
.selector_mask = 0xff,
46
+
.selector_shift = 0x0,
47
+
.window_start = RT5670_PRIV_DATA,
48
+
.window_len = 0x1, },
49
+
};
50
+
51
+
static struct reg_default init_list[] = {
52
+
{ RT5670_PR_BASE + 0x14, 0x9a8a },
53
+
{ RT5670_PR_BASE + 0x38, 0x3ba1 },
54
+
{ RT5670_PR_BASE + 0x3d, 0x3640 },
55
+
};
56
+
#define RT5670_INIT_REG_LEN ARRAY_SIZE(init_list)
57
+
58
+
static const struct reg_default rt5670_reg[] = {
59
+
{ 0x00, 0x0000 },
60
+
{ 0x02, 0x8888 },
61
+
{ 0x03, 0x8888 },
62
+
{ 0x0a, 0x0001 },
63
+
{ 0x0b, 0x0827 },
64
+
{ 0x0c, 0x0000 },
65
+
{ 0x0d, 0x0008 },
66
+
{ 0x0e, 0x0000 },
67
+
{ 0x0f, 0x0808 },
68
+
{ 0x19, 0xafaf },
69
+
{ 0x1a, 0xafaf },
70
+
{ 0x1b, 0x0011 },
71
+
{ 0x1c, 0x2f2f },
72
+
{ 0x1d, 0x2f2f },
73
+
{ 0x1e, 0x0000 },
74
+
{ 0x1f, 0x2f2f },
75
+
{ 0x20, 0x0000 },
76
+
{ 0x26, 0x7860 },
77
+
{ 0x27, 0x7860 },
78
+
{ 0x28, 0x7871 },
79
+
{ 0x29, 0x8080 },
80
+
{ 0x2a, 0x5656 },
81
+
{ 0x2b, 0x5454 },
82
+
{ 0x2c, 0xaaa0 },
83
+
{ 0x2d, 0x0000 },
84
+
{ 0x2e, 0x2f2f },
85
+
{ 0x2f, 0x1002 },
86
+
{ 0x30, 0x0000 },
87
+
{ 0x31, 0x5f00 },
88
+
{ 0x32, 0x0000 },
89
+
{ 0x33, 0x0000 },
90
+
{ 0x34, 0x0000 },
91
+
{ 0x35, 0x0000 },
92
+
{ 0x36, 0x0000 },
93
+
{ 0x37, 0x0000 },
94
+
{ 0x38, 0x0000 },
95
+
{ 0x3b, 0x0000 },
96
+
{ 0x3c, 0x007f },
97
+
{ 0x3d, 0x0000 },
98
+
{ 0x3e, 0x007f },
99
+
{ 0x45, 0xe00f },
100
+
{ 0x4c, 0x5380 },
101
+
{ 0x4f, 0x0073 },
102
+
{ 0x52, 0x00d3 },
103
+
{ 0x53, 0xf0f0 },
104
+
{ 0x61, 0x0000 },
105
+
{ 0x62, 0x0001 },
106
+
{ 0x63, 0x00c3 },
107
+
{ 0x64, 0x0000 },
108
+
{ 0x65, 0x0000 },
109
+
{ 0x66, 0x0000 },
110
+
{ 0x6f, 0x8000 },
111
+
{ 0x70, 0x8000 },
112
+
{ 0x71, 0x8000 },
113
+
{ 0x72, 0x8000 },
114
+
{ 0x73, 0x1110 },
115
+
{ 0x74, 0x0e00 },
116
+
{ 0x75, 0x1505 },
117
+
{ 0x76, 0x0015 },
118
+
{ 0x77, 0x0c00 },
119
+
{ 0x78, 0x4000 },
120
+
{ 0x79, 0x0123 },
121
+
{ 0x7f, 0x1100 },
122
+
{ 0x80, 0x0000 },
123
+
{ 0x81, 0x0000 },
124
+
{ 0x82, 0x0000 },
125
+
{ 0x83, 0x0000 },
126
+
{ 0x84, 0x0000 },
127
+
{ 0x85, 0x0000 },
128
+
{ 0x86, 0x0008 },
129
+
{ 0x87, 0x0000 },
130
+
{ 0x88, 0x0000 },
131
+
{ 0x89, 0x0000 },
132
+
{ 0x8a, 0x0000 },
133
+
{ 0x8b, 0x0000 },
134
+
{ 0x8c, 0x0007 },
135
+
{ 0x8d, 0x0000 },
136
+
{ 0x8e, 0x0004 },
137
+
{ 0x8f, 0x1100 },
138
+
{ 0x90, 0x0646 },
139
+
{ 0x91, 0x0c06 },
140
+
{ 0x93, 0x0000 },
141
+
{ 0x94, 0x0000 },
142
+
{ 0x95, 0x0000 },
143
+
{ 0x97, 0x0000 },
144
+
{ 0x98, 0x0000 },
145
+
{ 0x99, 0x0000 },
146
+
{ 0x9a, 0x2184 },
147
+
{ 0x9b, 0x010a },
148
+
{ 0x9c, 0x0aea },
149
+
{ 0x9d, 0x000c },
150
+
{ 0x9e, 0x0400 },
151
+
{ 0xae, 0x7000 },
152
+
{ 0xaf, 0x0000 },
153
+
{ 0xb0, 0x6000 },
154
+
{ 0xb1, 0x0000 },
155
+
{ 0xb2, 0x0000 },
156
+
{ 0xb3, 0x001f },
157
+
{ 0xb4, 0x2206 },
158
+
{ 0xb5, 0x1f00 },
159
+
{ 0xb6, 0x0000 },
160
+
{ 0xb7, 0x0000 },
161
+
{ 0xbb, 0x0000 },
162
+
{ 0xbc, 0x0000 },
163
+
{ 0xbd, 0x0000 },
164
+
{ 0xbe, 0x0000 },
165
+
{ 0xbf, 0x0000 },
166
+
{ 0xc0, 0x0000 },
167
+
{ 0xc1, 0x0000 },
168
+
{ 0xc2, 0x0000 },
169
+
{ 0xcd, 0x0000 },
170
+
{ 0xce, 0x0000 },
171
+
{ 0xcf, 0x1813 },
172
+
{ 0xd0, 0x0690 },
173
+
{ 0xd1, 0x1c17 },
174
+
{ 0xd3, 0xb320 },
175
+
{ 0xd4, 0x0000 },
176
+
{ 0xd6, 0x0400 },
177
+
{ 0xd9, 0x0809 },
178
+
{ 0xda, 0x0000 },
179
+
{ 0xdb, 0x0001 },
180
+
{ 0xdc, 0x0049 },
181
+
{ 0xdd, 0x0009 },
182
+
{ 0xe6, 0x8000 },
183
+
{ 0xe7, 0x0000 },
184
+
{ 0xec, 0xb300 },
185
+
{ 0xed, 0x0000 },
186
+
{ 0xee, 0xb300 },
187
+
{ 0xef, 0x0000 },
188
+
{ 0xf8, 0x0000 },
189
+
{ 0xf9, 0x0000 },
190
+
{ 0xfa, 0x8010 },
191
+
{ 0xfb, 0x0033 },
192
+
{ 0xfc, 0x0080 },
193
+
};
194
+
195
+
static bool rt5670_volatile_register(struct device *dev, unsigned int reg)
196
+
{
197
+
int i;
198
+
199
+
for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
200
+
if ((reg >= rt5670_ranges[i].window_start &&
201
+
reg <= rt5670_ranges[i].window_start +
202
+
rt5670_ranges[i].window_len) ||
203
+
(reg >= rt5670_ranges[i].range_min &&
204
+
reg <= rt5670_ranges[i].range_max)) {
205
+
return true;
206
+
}
207
+
}
208
+
209
+
switch (reg) {
210
+
case RT5670_RESET:
211
+
case RT5670_PDM_DATA_CTRL1:
212
+
case RT5670_PDM1_DATA_CTRL4:
213
+
case RT5670_PDM2_DATA_CTRL4:
214
+
case RT5670_PRIV_DATA:
215
+
case RT5670_ASRC_5:
216
+
case RT5670_CJ_CTRL1:
217
+
case RT5670_CJ_CTRL2:
218
+
case RT5670_CJ_CTRL3:
219
+
case RT5670_A_JD_CTRL1:
220
+
case RT5670_A_JD_CTRL2:
221
+
case RT5670_VAD_CTRL5:
222
+
case RT5670_ADC_EQ_CTRL1:
223
+
case RT5670_EQ_CTRL1:
224
+
case RT5670_ALC_CTRL_1:
225
+
case RT5670_IRQ_CTRL1:
226
+
case RT5670_IRQ_CTRL2:
227
+
case RT5670_INT_IRQ_ST:
228
+
case RT5670_IL_CMD:
229
+
case RT5670_DSP_CTRL1:
230
+
case RT5670_DSP_CTRL2:
231
+
case RT5670_DSP_CTRL3:
232
+
case RT5670_DSP_CTRL4:
233
+
case RT5670_DSP_CTRL5:
234
+
case RT5670_VENDOR_ID:
235
+
case RT5670_VENDOR_ID1:
236
+
case RT5670_VENDOR_ID2:
237
+
return true;
238
+
default:
239
+
return false;
240
+
}
241
+
}
242
+
243
+
static bool rt5670_readable_register(struct device *dev, unsigned int reg)
244
+
{
245
+
int i;
246
+
247
+
for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
248
+
if ((reg >= rt5670_ranges[i].window_start &&
249
+
reg <= rt5670_ranges[i].window_start +
250
+
rt5670_ranges[i].window_len) ||
251
+
(reg >= rt5670_ranges[i].range_min &&
252
+
reg <= rt5670_ranges[i].range_max)) {
253
+
return true;
254
+
}
255
+
}
256
+
257
+
switch (reg) {
258
+
case RT5670_RESET:
259
+
case RT5670_HP_VOL:
260
+
case RT5670_LOUT1:
261
+
case RT5670_CJ_CTRL1:
262
+
case RT5670_CJ_CTRL2:
263
+
case RT5670_CJ_CTRL3:
264
+
case RT5670_IN2:
265
+
case RT5670_INL1_INR1_VOL:
266
+
case RT5670_DAC1_DIG_VOL:
267
+
case RT5670_DAC2_DIG_VOL:
268
+
case RT5670_DAC_CTRL:
269
+
case RT5670_STO1_ADC_DIG_VOL:
270
+
case RT5670_MONO_ADC_DIG_VOL:
271
+
case RT5670_STO2_ADC_DIG_VOL:
272
+
case RT5670_ADC_BST_VOL1:
273
+
case RT5670_ADC_BST_VOL2:
274
+
case RT5670_STO2_ADC_MIXER:
275
+
case RT5670_STO1_ADC_MIXER:
276
+
case RT5670_MONO_ADC_MIXER:
277
+
case RT5670_AD_DA_MIXER:
278
+
case RT5670_STO_DAC_MIXER:
279
+
case RT5670_DD_MIXER:
280
+
case RT5670_DIG_MIXER:
281
+
case RT5670_DSP_PATH1:
282
+
case RT5670_DSP_PATH2:
283
+
case RT5670_DIG_INF1_DATA:
284
+
case RT5670_DIG_INF2_DATA:
285
+
case RT5670_PDM_OUT_CTRL:
286
+
case RT5670_PDM_DATA_CTRL1:
287
+
case RT5670_PDM1_DATA_CTRL2:
288
+
case RT5670_PDM1_DATA_CTRL3:
289
+
case RT5670_PDM1_DATA_CTRL4:
290
+
case RT5670_PDM2_DATA_CTRL2:
291
+
case RT5670_PDM2_DATA_CTRL3:
292
+
case RT5670_PDM2_DATA_CTRL4:
293
+
case RT5670_REC_L1_MIXER:
294
+
case RT5670_REC_L2_MIXER:
295
+
case RT5670_REC_R1_MIXER:
296
+
case RT5670_REC_R2_MIXER:
297
+
case RT5670_HPO_MIXER:
298
+
case RT5670_MONO_MIXER:
299
+
case RT5670_OUT_L1_MIXER:
300
+
case RT5670_OUT_R1_MIXER:
301
+
case RT5670_LOUT_MIXER:
302
+
case RT5670_PWR_DIG1:
303
+
case RT5670_PWR_DIG2:
304
+
case RT5670_PWR_ANLG1:
305
+
case RT5670_PWR_ANLG2:
306
+
case RT5670_PWR_MIXER:
307
+
case RT5670_PWR_VOL:
308
+
case RT5670_PRIV_INDEX:
309
+
case RT5670_PRIV_DATA:
310
+
case RT5670_I2S4_SDP:
311
+
case RT5670_I2S1_SDP:
312
+
case RT5670_I2S2_SDP:
313
+
case RT5670_I2S3_SDP:
314
+
case RT5670_ADDA_CLK1:
315
+
case RT5670_ADDA_CLK2:
316
+
case RT5670_DMIC_CTRL1:
317
+
case RT5670_DMIC_CTRL2:
318
+
case RT5670_TDM_CTRL_1:
319
+
case RT5670_TDM_CTRL_2:
320
+
case RT5670_TDM_CTRL_3:
321
+
case RT5670_DSP_CLK:
322
+
case RT5670_GLB_CLK:
323
+
case RT5670_PLL_CTRL1:
324
+
case RT5670_PLL_CTRL2:
325
+
case RT5670_ASRC_1:
326
+
case RT5670_ASRC_2:
327
+
case RT5670_ASRC_3:
328
+
case RT5670_ASRC_4:
329
+
case RT5670_ASRC_5:
330
+
case RT5670_ASRC_7:
331
+
case RT5670_ASRC_8:
332
+
case RT5670_ASRC_9:
333
+
case RT5670_ASRC_10:
334
+
case RT5670_ASRC_11:
335
+
case RT5670_ASRC_12:
336
+
case RT5670_ASRC_13:
337
+
case RT5670_ASRC_14:
338
+
case RT5670_DEPOP_M1:
339
+
case RT5670_DEPOP_M2:
340
+
case RT5670_DEPOP_M3:
341
+
case RT5670_CHARGE_PUMP:
342
+
case RT5670_MICBIAS:
343
+
case RT5670_A_JD_CTRL1:
344
+
case RT5670_A_JD_CTRL2:
345
+
case RT5670_VAD_CTRL1:
346
+
case RT5670_VAD_CTRL2:
347
+
case RT5670_VAD_CTRL3:
348
+
case RT5670_VAD_CTRL4:
349
+
case RT5670_VAD_CTRL5:
350
+
case RT5670_ADC_EQ_CTRL1:
351
+
case RT5670_ADC_EQ_CTRL2:
352
+
case RT5670_EQ_CTRL1:
353
+
case RT5670_EQ_CTRL2:
354
+
case RT5670_ALC_DRC_CTRL1:
355
+
case RT5670_ALC_DRC_CTRL2:
356
+
case RT5670_ALC_CTRL_1:
357
+
case RT5670_ALC_CTRL_2:
358
+
case RT5670_ALC_CTRL_3:
359
+
case RT5670_JD_CTRL:
360
+
case RT5670_IRQ_CTRL1:
361
+
case RT5670_IRQ_CTRL2:
362
+
case RT5670_INT_IRQ_ST:
363
+
case RT5670_GPIO_CTRL1:
364
+
case RT5670_GPIO_CTRL2:
365
+
case RT5670_GPIO_CTRL3:
366
+
case RT5670_SCRABBLE_FUN:
367
+
case RT5670_SCRABBLE_CTRL:
368
+
case RT5670_BASE_BACK:
369
+
case RT5670_MP3_PLUS1:
370
+
case RT5670_MP3_PLUS2:
371
+
case RT5670_ADJ_HPF1:
372
+
case RT5670_ADJ_HPF2:
373
+
case RT5670_HP_CALIB_AMP_DET:
374
+
case RT5670_SV_ZCD1:
375
+
case RT5670_SV_ZCD2:
376
+
case RT5670_IL_CMD:
377
+
case RT5670_IL_CMD2:
378
+
case RT5670_IL_CMD3:
379
+
case RT5670_DRC_HL_CTRL1:
380
+
case RT5670_DRC_HL_CTRL2:
381
+
case RT5670_ADC_MONO_HP_CTRL1:
382
+
case RT5670_ADC_MONO_HP_CTRL2:
383
+
case RT5670_ADC_STO2_HP_CTRL1:
384
+
case RT5670_ADC_STO2_HP_CTRL2:
385
+
case RT5670_JD_CTRL3:
386
+
case RT5670_JD_CTRL4:
387
+
case RT5670_DIG_MISC:
388
+
case RT5670_DSP_CTRL1:
389
+
case RT5670_DSP_CTRL2:
390
+
case RT5670_DSP_CTRL3:
391
+
case RT5670_DSP_CTRL4:
392
+
case RT5670_DSP_CTRL5:
393
+
case RT5670_GEN_CTRL2:
394
+
case RT5670_GEN_CTRL3:
395
+
case RT5670_VENDOR_ID:
396
+
case RT5670_VENDOR_ID1:
397
+
case RT5670_VENDOR_ID2:
398
+
return true;
399
+
default:
400
+
return false;
401
+
}
402
+
}
403
+
404
+
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
405
+
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
406
+
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
407
+
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
408
+
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
409
+
410
+
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
411
+
static unsigned int bst_tlv[] = {
412
+
TLV_DB_RANGE_HEAD(7),
413
+
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
414
+
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
415
+
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
416
+
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
417
+
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
418
+
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
419
+
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
420
+
};
421
+
422
+
/* Interface data select */
423
+
static const char * const rt5670_data_select[] = {
424
+
"Normal", "Swap", "left copy to right", "right copy to left"
425
+
};
426
+
427
+
static const SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA,
428
+
RT5670_IF2_DAC_SEL_SFT, rt5670_data_select);
429
+
430
+
static const SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA,
431
+
RT5670_IF2_ADC_SEL_SFT, rt5670_data_select);
432
+
433
+
static const struct snd_kcontrol_new rt5670_snd_controls[] = {
434
+
/* Headphone Output Volume */
435
+
SOC_DOUBLE("HP Playback Switch", RT5670_HP_VOL,
436
+
RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
437
+
SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
438
+
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
439
+
39, 0, out_vol_tlv),
440
+
/* OUTPUT Control */
441
+
SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,
442
+
RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),
443
+
SOC_DOUBLE_TLV("OUT Playback Volume", RT5670_LOUT1,
444
+
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT, 39, 1, out_vol_tlv),
445
+
/* DAC Digital Volume */
446
+
SOC_DOUBLE("DAC2 Playback Switch", RT5670_DAC_CTRL,
447
+
RT5670_M_DAC_L2_VOL_SFT, RT5670_M_DAC_R2_VOL_SFT, 1, 1),
448
+
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5670_DAC1_DIG_VOL,
449
+
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
450
+
175, 0, dac_vol_tlv),
451
+
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5670_DAC2_DIG_VOL,
452
+
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
453
+
175, 0, dac_vol_tlv),
454
+
/* IN1/IN2 Control */
455
+
SOC_SINGLE_TLV("IN1 Boost Volume", RT5670_CJ_CTRL1,
456
+
RT5670_BST_SFT1, 8, 0, bst_tlv),
457
+
SOC_SINGLE_TLV("IN2 Boost Volume", RT5670_IN2,
458
+
RT5670_BST_SFT1, 8, 0, bst_tlv),
459
+
/* INL/INR Volume Control */
460
+
SOC_DOUBLE_TLV("IN Capture Volume", RT5670_INL1_INR1_VOL,
461
+
RT5670_INL_VOL_SFT, RT5670_INR_VOL_SFT,
462
+
31, 1, in_vol_tlv),
463
+
/* ADC Digital Volume Control */
464
+
SOC_DOUBLE("ADC Capture Switch", RT5670_STO1_ADC_DIG_VOL,
465
+
RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
466
+
SOC_DOUBLE_TLV("ADC Capture Volume", RT5670_STO1_ADC_DIG_VOL,
467
+
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
468
+
127, 0, adc_vol_tlv),
469
+
470
+
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5670_MONO_ADC_DIG_VOL,
471
+
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
472
+
127, 0, adc_vol_tlv),
473
+
474
+
/* ADC Boost Volume Control */
475
+
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
476
+
RT5670_STO1_ADC_L_BST_SFT, RT5670_STO1_ADC_R_BST_SFT,
477
+
3, 0, adc_bst_tlv),
478
+
479
+
SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
480
+
RT5670_STO2_ADC_L_BST_SFT, RT5670_STO2_ADC_R_BST_SFT,
481
+
3, 0, adc_bst_tlv),
482
+
483
+
SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum),
484
+
SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum),
485
+
};
486
+
487
+
/**
488
+
* set_dmic_clk - Set parameter of dmic.
489
+
*
490
+
* @w: DAPM widget.
491
+
* @kcontrol: The kcontrol of this widget.
492
+
* @event: Event id.
493
+
*
494
+
* Choose dmic clock between 1MHz and 3MHz.
495
+
* It is better for clock to approximate 3MHz.
496
+
*/
497
+
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
498
+
struct snd_kcontrol *kcontrol, int event)
499
+
{
500
+
struct snd_soc_codec *codec = w->codec;
501
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
502
+
int idx = -EINVAL;
503
+
504
+
idx = rl6231_calc_dmic_clk(rt5670->sysclk);
505
+
506
+
if (idx < 0)
507
+
dev_err(codec->dev, "Failed to set DMIC clock\n");
508
+
else
509
+
snd_soc_update_bits(codec, RT5670_DMIC_CTRL1,
510
+
RT5670_DMIC_CLK_MASK, idx << RT5670_DMIC_CLK_SFT);
511
+
return idx;
512
+
}
513
+
514
+
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
515
+
struct snd_soc_dapm_widget *sink)
516
+
{
517
+
unsigned int val;
518
+
519
+
val = snd_soc_read(source->codec, RT5670_GLB_CLK);
520
+
val &= RT5670_SCLK_SRC_MASK;
521
+
if (val == RT5670_SCLK_SRC_PLL1)
522
+
return 1;
523
+
else
524
+
return 0;
525
+
}
526
+
527
+
static int is_using_asrc(struct snd_soc_dapm_widget *source,
528
+
struct snd_soc_dapm_widget *sink)
529
+
{
530
+
unsigned int reg, shift, val;
531
+
532
+
switch (source->shift) {
533
+
case 0:
534
+
reg = RT5670_ASRC_3;
535
+
shift = 0;
536
+
break;
537
+
case 1:
538
+
reg = RT5670_ASRC_3;
539
+
shift = 4;
540
+
break;
541
+
case 2:
542
+
reg = RT5670_ASRC_5;
543
+
shift = 12;
544
+
break;
545
+
case 3:
546
+
reg = RT5670_ASRC_2;
547
+
shift = 0;
548
+
break;
549
+
case 8:
550
+
reg = RT5670_ASRC_2;
551
+
shift = 4;
552
+
break;
553
+
case 9:
554
+
reg = RT5670_ASRC_2;
555
+
shift = 8;
556
+
break;
557
+
case 10:
558
+
reg = RT5670_ASRC_2;
559
+
shift = 12;
560
+
break;
561
+
default:
562
+
return 0;
563
+
}
564
+
565
+
val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
566
+
switch (val) {
567
+
case 1:
568
+
case 2:
569
+
case 3:
570
+
case 4:
571
+
return 1;
572
+
default:
573
+
return 0;
574
+
}
575
+
576
+
}
577
+
578
+
/* Digital Mixer */
579
+
static const struct snd_kcontrol_new rt5670_sto1_adc_l_mix[] = {
580
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
581
+
RT5670_M_ADC_L1_SFT, 1, 1),
582
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
583
+
RT5670_M_ADC_L2_SFT, 1, 1),
584
+
};
585
+
586
+
static const struct snd_kcontrol_new rt5670_sto1_adc_r_mix[] = {
587
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
588
+
RT5670_M_ADC_R1_SFT, 1, 1),
589
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
590
+
RT5670_M_ADC_R2_SFT, 1, 1),
591
+
};
592
+
593
+
static const struct snd_kcontrol_new rt5670_sto2_adc_l_mix[] = {
594
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
595
+
RT5670_M_ADC_L1_SFT, 1, 1),
596
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
597
+
RT5670_M_ADC_L2_SFT, 1, 1),
598
+
};
599
+
600
+
static const struct snd_kcontrol_new rt5670_sto2_adc_r_mix[] = {
601
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
602
+
RT5670_M_ADC_R1_SFT, 1, 1),
603
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
604
+
RT5670_M_ADC_R2_SFT, 1, 1),
605
+
};
606
+
607
+
static const struct snd_kcontrol_new rt5670_mono_adc_l_mix[] = {
608
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
609
+
RT5670_M_MONO_ADC_L1_SFT, 1, 1),
610
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
611
+
RT5670_M_MONO_ADC_L2_SFT, 1, 1),
612
+
};
613
+
614
+
static const struct snd_kcontrol_new rt5670_mono_adc_r_mix[] = {
615
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
616
+
RT5670_M_MONO_ADC_R1_SFT, 1, 1),
617
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
618
+
RT5670_M_MONO_ADC_R2_SFT, 1, 1),
619
+
};
620
+
621
+
static const struct snd_kcontrol_new rt5670_dac_l_mix[] = {
622
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
623
+
RT5670_M_ADCMIX_L_SFT, 1, 1),
624
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
625
+
RT5670_M_DAC1_L_SFT, 1, 1),
626
+
};
627
+
628
+
static const struct snd_kcontrol_new rt5670_dac_r_mix[] = {
629
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
630
+
RT5670_M_ADCMIX_R_SFT, 1, 1),
631
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
632
+
RT5670_M_DAC1_R_SFT, 1, 1),
633
+
};
634
+
635
+
static const struct snd_kcontrol_new rt5670_sto_dac_l_mix[] = {
636
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
637
+
RT5670_M_DAC_L1_SFT, 1, 1),
638
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
639
+
RT5670_M_DAC_L2_SFT, 1, 1),
640
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
641
+
RT5670_M_DAC_R1_STO_L_SFT, 1, 1),
642
+
};
643
+
644
+
static const struct snd_kcontrol_new rt5670_sto_dac_r_mix[] = {
645
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
646
+
RT5670_M_DAC_R1_SFT, 1, 1),
647
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
648
+
RT5670_M_DAC_R2_SFT, 1, 1),
649
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
650
+
RT5670_M_DAC_L1_STO_R_SFT, 1, 1),
651
+
};
652
+
653
+
static const struct snd_kcontrol_new rt5670_mono_dac_l_mix[] = {
654
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_DD_MIXER,
655
+
RT5670_M_DAC_L1_MONO_L_SFT, 1, 1),
656
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
657
+
RT5670_M_DAC_L2_MONO_L_SFT, 1, 1),
658
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
659
+
RT5670_M_DAC_R2_MONO_L_SFT, 1, 1),
660
+
};
661
+
662
+
static const struct snd_kcontrol_new rt5670_mono_dac_r_mix[] = {
663
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
664
+
RT5670_M_DAC_R1_MONO_R_SFT, 1, 1),
665
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
666
+
RT5670_M_DAC_R2_MONO_R_SFT, 1, 1),
667
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
668
+
RT5670_M_DAC_L2_MONO_R_SFT, 1, 1),
669
+
};
670
+
671
+
static const struct snd_kcontrol_new rt5670_dig_l_mix[] = {
672
+
SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5670_DIG_MIXER,
673
+
RT5670_M_STO_L_DAC_L_SFT, 1, 1),
674
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
675
+
RT5670_M_DAC_L2_DAC_L_SFT, 1, 1),
676
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
677
+
RT5670_M_DAC_R2_DAC_L_SFT, 1, 1),
678
+
};
679
+
680
+
static const struct snd_kcontrol_new rt5670_dig_r_mix[] = {
681
+
SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5670_DIG_MIXER,
682
+
RT5670_M_STO_R_DAC_R_SFT, 1, 1),
683
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
684
+
RT5670_M_DAC_R2_DAC_R_SFT, 1, 1),
685
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
686
+
RT5670_M_DAC_L2_DAC_R_SFT, 1, 1),
687
+
};
688
+
689
+
/* Analog Input Mixer */
690
+
static const struct snd_kcontrol_new rt5670_rec_l_mix[] = {
691
+
SOC_DAPM_SINGLE("INL Switch", RT5670_REC_L2_MIXER,
692
+
RT5670_M_IN_L_RM_L_SFT, 1, 1),
693
+
SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_L2_MIXER,
694
+
RT5670_M_BST2_RM_L_SFT, 1, 1),
695
+
SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_L2_MIXER,
696
+
RT5670_M_BST1_RM_L_SFT, 1, 1),
697
+
};
698
+
699
+
static const struct snd_kcontrol_new rt5670_rec_r_mix[] = {
700
+
SOC_DAPM_SINGLE("INR Switch", RT5670_REC_R2_MIXER,
701
+
RT5670_M_IN_R_RM_R_SFT, 1, 1),
702
+
SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_R2_MIXER,
703
+
RT5670_M_BST2_RM_R_SFT, 1, 1),
704
+
SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_R2_MIXER,
705
+
RT5670_M_BST1_RM_R_SFT, 1, 1),
706
+
};
707
+
708
+
static const struct snd_kcontrol_new rt5670_out_l_mix[] = {
709
+
SOC_DAPM_SINGLE("BST1 Switch", RT5670_OUT_L1_MIXER,
710
+
RT5670_M_BST1_OM_L_SFT, 1, 1),
711
+
SOC_DAPM_SINGLE("INL Switch", RT5670_OUT_L1_MIXER,
712
+
RT5670_M_IN_L_OM_L_SFT, 1, 1),
713
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
714
+
RT5670_M_DAC_L2_OM_L_SFT, 1, 1),
715
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_OUT_L1_MIXER,
716
+
RT5670_M_DAC_L1_OM_L_SFT, 1, 1),
717
+
};
718
+
719
+
static const struct snd_kcontrol_new rt5670_out_r_mix[] = {
720
+
SOC_DAPM_SINGLE("BST2 Switch", RT5670_OUT_R1_MIXER,
721
+
RT5670_M_BST2_OM_R_SFT, 1, 1),
722
+
SOC_DAPM_SINGLE("INR Switch", RT5670_OUT_R1_MIXER,
723
+
RT5670_M_IN_R_OM_R_SFT, 1, 1),
724
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
725
+
RT5670_M_DAC_R2_OM_R_SFT, 1, 1),
726
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
727
+
RT5670_M_DAC_R1_OM_R_SFT, 1, 1),
728
+
};
729
+
730
+
static const struct snd_kcontrol_new rt5670_hpo_mix[] = {
731
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
732
+
RT5670_M_DAC1_HM_SFT, 1, 1),
733
+
SOC_DAPM_SINGLE("HPVOL Switch", RT5670_HPO_MIXER,
734
+
RT5670_M_HPVOL_HM_SFT, 1, 1),
735
+
};
736
+
737
+
static const struct snd_kcontrol_new rt5670_hpvoll_mix[] = {
738
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
739
+
RT5670_M_DACL1_HML_SFT, 1, 1),
740
+
SOC_DAPM_SINGLE("INL Switch", RT5670_HPO_MIXER,
741
+
RT5670_M_INL1_HML_SFT, 1, 1),
742
+
};
743
+
744
+
static const struct snd_kcontrol_new rt5670_hpvolr_mix[] = {
745
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
746
+
RT5670_M_DACR1_HMR_SFT, 1, 1),
747
+
SOC_DAPM_SINGLE("INR Switch", RT5670_HPO_MIXER,
748
+
RT5670_M_INR1_HMR_SFT, 1, 1),
749
+
};
750
+
751
+
static const struct snd_kcontrol_new rt5670_lout_mix[] = {
752
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_LOUT_MIXER,
753
+
RT5670_M_DAC_L1_LM_SFT, 1, 1),
754
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
755
+
RT5670_M_DAC_R1_LM_SFT, 1, 1),
756
+
SOC_DAPM_SINGLE("OUTMIX L Switch", RT5670_LOUT_MIXER,
757
+
RT5670_M_OV_L_LM_SFT, 1, 1),
758
+
SOC_DAPM_SINGLE("OUTMIX R Switch", RT5670_LOUT_MIXER,
759
+
RT5670_M_OV_R_LM_SFT, 1, 1),
760
+
};
761
+
762
+
static const struct snd_kcontrol_new rt5670_hpl_mix[] = {
763
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_HPO_MIXER,
764
+
RT5670_M_DACL1_HML_SFT, 1, 1),
765
+
SOC_DAPM_SINGLE("INL1 Switch", RT5670_HPO_MIXER,
766
+
RT5670_M_INL1_HML_SFT, 1, 1),
767
+
};
768
+
769
+
static const struct snd_kcontrol_new rt5670_hpr_mix[] = {
770
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_HPO_MIXER,
771
+
RT5670_M_DACR1_HMR_SFT, 1, 1),
772
+
SOC_DAPM_SINGLE("INR1 Switch", RT5670_HPO_MIXER,
773
+
RT5670_M_INR1_HMR_SFT, 1, 1),
774
+
};
775
+
776
+
static const struct snd_kcontrol_new lout_l_enable_control =
777
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
778
+
RT5670_L_MUTE_SFT, 1, 1);
779
+
780
+
static const struct snd_kcontrol_new lout_r_enable_control =
781
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
782
+
RT5670_R_MUTE_SFT, 1, 1);
783
+
784
+
/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
785
+
static const char * const rt5670_dac1_src[] = {
786
+
"IF1 DAC", "IF2 DAC"
787
+
};
788
+
789
+
static const SOC_ENUM_SINGLE_DECL(
790
+
rt5670_dac1l_enum, RT5670_AD_DA_MIXER,
791
+
RT5670_DAC1_L_SEL_SFT, rt5670_dac1_src);
792
+
793
+
static const struct snd_kcontrol_new rt5670_dac1l_mux =
794
+
SOC_DAPM_ENUM("DAC1 L source", rt5670_dac1l_enum);
795
+
796
+
static const SOC_ENUM_SINGLE_DECL(
797
+
rt5670_dac1r_enum, RT5670_AD_DA_MIXER,
798
+
RT5670_DAC1_R_SEL_SFT, rt5670_dac1_src);
799
+
800
+
static const struct snd_kcontrol_new rt5670_dac1r_mux =
801
+
SOC_DAPM_ENUM("DAC1 R source", rt5670_dac1r_enum);
802
+
803
+
/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
804
+
/* TODO Use SOC_VALUE_ENUM_SINGLE_DECL */
805
+
static const char * const rt5670_dac12_src[] = {
806
+
"IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC",
807
+
"Bass", "VAD_ADC", "IF4 DAC"
808
+
};
809
+
810
+
static const SOC_ENUM_SINGLE_DECL(
811
+
rt5670_dac2l_enum, RT5670_DAC_CTRL,
812
+
RT5670_DAC2_L_SEL_SFT, rt5670_dac12_src);
813
+
814
+
static const struct snd_kcontrol_new rt5670_dac_l2_mux =
815
+
SOC_DAPM_ENUM("DAC2 L source", rt5670_dac2l_enum);
816
+
817
+
static const char * const rt5670_dacr2_src[] = {
818
+
"IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
819
+
};
820
+
821
+
static const SOC_ENUM_SINGLE_DECL(
822
+
rt5670_dac2r_enum, RT5670_DAC_CTRL,
823
+
RT5670_DAC2_R_SEL_SFT, rt5670_dacr2_src);
824
+
825
+
static const struct snd_kcontrol_new rt5670_dac_r2_mux =
826
+
SOC_DAPM_ENUM("DAC2 R source", rt5670_dac2r_enum);
827
+
828
+
/*RxDP source*/ /* MX-2D [15:13] */
829
+
static const char * const rt5670_rxdp_src[] = {
830
+
"IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
831
+
"Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
832
+
};
833
+
834
+
static const SOC_ENUM_SINGLE_DECL(
835
+
rt5670_rxdp_enum, RT5670_DSP_PATH1,
836
+
RT5670_RXDP_SEL_SFT, rt5670_rxdp_src);
837
+
838
+
static const struct snd_kcontrol_new rt5670_rxdp_mux =
839
+
SOC_DAPM_ENUM("DAC2 L source", rt5670_rxdp_enum);
840
+
841
+
/* MX-2D [1] [0] */
842
+
static const char * const rt5670_dsp_bypass_src[] = {
843
+
"DSP", "Bypass"
844
+
};
845
+
846
+
static const SOC_ENUM_SINGLE_DECL(
847
+
rt5670_dsp_ul_enum, RT5670_DSP_PATH1,
848
+
RT5670_DSP_UL_SFT, rt5670_dsp_bypass_src);
849
+
850
+
static const struct snd_kcontrol_new rt5670_dsp_ul_mux =
851
+
SOC_DAPM_ENUM("DSP UL source", rt5670_dsp_ul_enum);
852
+
853
+
static const SOC_ENUM_SINGLE_DECL(
854
+
rt5670_dsp_dl_enum, RT5670_DSP_PATH1,
855
+
RT5670_DSP_DL_SFT, rt5670_dsp_bypass_src);
856
+
857
+
static const struct snd_kcontrol_new rt5670_dsp_dl_mux =
858
+
SOC_DAPM_ENUM("DSP DL source", rt5670_dsp_dl_enum);
859
+
860
+
/* Stereo2 ADC source */
861
+
/* MX-26 [15] */
862
+
static const char * const rt5670_stereo2_adc_lr_src[] = {
863
+
"L", "LR"
864
+
};
865
+
866
+
static const SOC_ENUM_SINGLE_DECL(
867
+
rt5670_stereo2_adc_lr_enum, RT5670_STO2_ADC_MIXER,
868
+
RT5670_STO2_ADC_SRC_SFT, rt5670_stereo2_adc_lr_src);
869
+
870
+
static const struct snd_kcontrol_new rt5670_sto2_adc_lr_mux =
871
+
SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5670_stereo2_adc_lr_enum);
872
+
873
+
/* Stereo1 ADC source */
874
+
/* MX-27 MX-26 [12] */
875
+
static const char * const rt5670_stereo_adc1_src[] = {
876
+
"DAC MIX", "ADC"
877
+
};
878
+
879
+
static const SOC_ENUM_SINGLE_DECL(
880
+
rt5670_stereo1_adc1_enum, RT5670_STO1_ADC_MIXER,
881
+
RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
882
+
883
+
static const struct snd_kcontrol_new rt5670_sto_adc_l1_mux =
884
+
SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5670_stereo1_adc1_enum);
885
+
886
+
static const struct snd_kcontrol_new rt5670_sto_adc_r1_mux =
887
+
SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5670_stereo1_adc1_enum);
888
+
889
+
static const SOC_ENUM_SINGLE_DECL(
890
+
rt5670_stereo2_adc1_enum, RT5670_STO2_ADC_MIXER,
891
+
RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
892
+
893
+
static const struct snd_kcontrol_new rt5670_sto2_adc_l1_mux =
894
+
SOC_DAPM_ENUM("Stereo2 ADC L1 source", rt5670_stereo2_adc1_enum);
895
+
896
+
static const struct snd_kcontrol_new rt5670_sto2_adc_r1_mux =
897
+
SOC_DAPM_ENUM("Stereo2 ADC R1 source", rt5670_stereo2_adc1_enum);
898
+
899
+
/* MX-27 MX-26 [11] */
900
+
static const char * const rt5670_stereo_adc2_src[] = {
901
+
"DAC MIX", "DMIC"
902
+
};
903
+
904
+
static const SOC_ENUM_SINGLE_DECL(
905
+
rt5670_stereo1_adc2_enum, RT5670_STO1_ADC_MIXER,
906
+
RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
907
+
908
+
static const struct snd_kcontrol_new rt5670_sto_adc_l2_mux =
909
+
SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5670_stereo1_adc2_enum);
910
+
911
+
static const struct snd_kcontrol_new rt5670_sto_adc_r2_mux =
912
+
SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5670_stereo1_adc2_enum);
913
+
914
+
static const SOC_ENUM_SINGLE_DECL(
915
+
rt5670_stereo2_adc2_enum, RT5670_STO2_ADC_MIXER,
916
+
RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
917
+
918
+
static const struct snd_kcontrol_new rt5670_sto2_adc_l2_mux =
919
+
SOC_DAPM_ENUM("Stereo2 ADC L2 source", rt5670_stereo2_adc2_enum);
920
+
921
+
static const struct snd_kcontrol_new rt5670_sto2_adc_r2_mux =
922
+
SOC_DAPM_ENUM("Stereo2 ADC R2 source", rt5670_stereo2_adc2_enum);
923
+
924
+
/* MX-27 MX26 [10] */
925
+
static const char * const rt5670_stereo_adc_src[] = {
926
+
"ADC1L ADC2R", "ADC3"
927
+
};
928
+
929
+
static const SOC_ENUM_SINGLE_DECL(
930
+
rt5670_stereo1_adc_enum, RT5670_STO1_ADC_MIXER,
931
+
RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
932
+
933
+
static const struct snd_kcontrol_new rt5670_sto_adc_mux =
934
+
SOC_DAPM_ENUM("Stereo1 ADC source", rt5670_stereo1_adc_enum);
935
+
936
+
static const SOC_ENUM_SINGLE_DECL(
937
+
rt5670_stereo2_adc_enum, RT5670_STO2_ADC_MIXER,
938
+
RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
939
+
940
+
static const struct snd_kcontrol_new rt5670_sto2_adc_mux =
941
+
SOC_DAPM_ENUM("Stereo2 ADC source", rt5670_stereo2_adc_enum);
942
+
943
+
/* MX-27 MX-26 [9:8] */
944
+
static const char * const rt5670_stereo_dmic_src[] = {
945
+
"DMIC1", "DMIC2", "DMIC3"
946
+
};
947
+
948
+
static const SOC_ENUM_SINGLE_DECL(
949
+
rt5670_stereo1_dmic_enum, RT5670_STO1_ADC_MIXER,
950
+
RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
951
+
952
+
static const struct snd_kcontrol_new rt5670_sto1_dmic_mux =
953
+
SOC_DAPM_ENUM("Stereo1 DMIC source", rt5670_stereo1_dmic_enum);
954
+
955
+
static const SOC_ENUM_SINGLE_DECL(
956
+
rt5670_stereo2_dmic_enum, RT5670_STO2_ADC_MIXER,
957
+
RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
958
+
959
+
static const struct snd_kcontrol_new rt5670_sto2_dmic_mux =
960
+
SOC_DAPM_ENUM("Stereo2 DMIC source", rt5670_stereo2_dmic_enum);
961
+
962
+
/* MX-27 [0] */
963
+
static const char * const rt5670_stereo_dmic3_src[] = {
964
+
"DMIC3", "PDM ADC"
965
+
};
966
+
967
+
static const SOC_ENUM_SINGLE_DECL(
968
+
rt5670_stereo_dmic3_enum, RT5670_STO1_ADC_MIXER,
969
+
RT5670_DMIC3_SRC_SFT, rt5670_stereo_dmic3_src);
970
+
971
+
static const struct snd_kcontrol_new rt5670_sto_dmic3_mux =
972
+
SOC_DAPM_ENUM("Stereo DMIC3 source", rt5670_stereo_dmic3_enum);
973
+
974
+
/* Mono ADC source */
975
+
/* MX-28 [12] */
976
+
static const char * const rt5670_mono_adc_l1_src[] = {
977
+
"Mono DAC MIXL", "ADC1"
978
+
};
979
+
980
+
static const SOC_ENUM_SINGLE_DECL(
981
+
rt5670_mono_adc_l1_enum, RT5670_MONO_ADC_MIXER,
982
+
RT5670_MONO_ADC_L1_SRC_SFT, rt5670_mono_adc_l1_src);
983
+
984
+
static const struct snd_kcontrol_new rt5670_mono_adc_l1_mux =
985
+
SOC_DAPM_ENUM("Mono ADC1 left source", rt5670_mono_adc_l1_enum);
986
+
/* MX-28 [11] */
987
+
static const char * const rt5670_mono_adc_l2_src[] = {
988
+
"Mono DAC MIXL", "DMIC"
989
+
};
990
+
991
+
static const SOC_ENUM_SINGLE_DECL(
992
+
rt5670_mono_adc_l2_enum, RT5670_MONO_ADC_MIXER,
993
+
RT5670_MONO_ADC_L2_SRC_SFT, rt5670_mono_adc_l2_src);
994
+
995
+
static const struct snd_kcontrol_new rt5670_mono_adc_l2_mux =
996
+
SOC_DAPM_ENUM("Mono ADC2 left source", rt5670_mono_adc_l2_enum);
997
+
998
+
/* MX-28 [9:8] */
999
+
static const char * const rt5670_mono_dmic_src[] = {
1000
+
"DMIC1", "DMIC2", "DMIC3"
1001
+
};
1002
+
1003
+
static const SOC_ENUM_SINGLE_DECL(
1004
+
rt5670_mono_dmic_l_enum, RT5670_MONO_ADC_MIXER,
1005
+
RT5670_MONO_DMIC_L_SRC_SFT, rt5670_mono_dmic_src);
1006
+
1007
+
static const struct snd_kcontrol_new rt5670_mono_dmic_l_mux =
1008
+
SOC_DAPM_ENUM("Mono DMIC left source", rt5670_mono_dmic_l_enum);
1009
+
/* MX-28 [1:0] */
1010
+
static const SOC_ENUM_SINGLE_DECL(
1011
+
rt5670_mono_dmic_r_enum, RT5670_MONO_ADC_MIXER,
1012
+
RT5670_MONO_DMIC_R_SRC_SFT, rt5670_mono_dmic_src);
1013
+
1014
+
static const struct snd_kcontrol_new rt5670_mono_dmic_r_mux =
1015
+
SOC_DAPM_ENUM("Mono DMIC Right source", rt5670_mono_dmic_r_enum);
1016
+
/* MX-28 [4] */
1017
+
static const char * const rt5670_mono_adc_r1_src[] = {
1018
+
"Mono DAC MIXR", "ADC2"
1019
+
};
1020
+
1021
+
static const SOC_ENUM_SINGLE_DECL(
1022
+
rt5670_mono_adc_r1_enum, RT5670_MONO_ADC_MIXER,
1023
+
RT5670_MONO_ADC_R1_SRC_SFT, rt5670_mono_adc_r1_src);
1024
+
1025
+
static const struct snd_kcontrol_new rt5670_mono_adc_r1_mux =
1026
+
SOC_DAPM_ENUM("Mono ADC1 right source", rt5670_mono_adc_r1_enum);
1027
+
/* MX-28 [3] */
1028
+
static const char * const rt5670_mono_adc_r2_src[] = {
1029
+
"Mono DAC MIXR", "DMIC"
1030
+
};
1031
+
1032
+
static const SOC_ENUM_SINGLE_DECL(
1033
+
rt5670_mono_adc_r2_enum, RT5670_MONO_ADC_MIXER,
1034
+
RT5670_MONO_ADC_R2_SRC_SFT, rt5670_mono_adc_r2_src);
1035
+
1036
+
static const struct snd_kcontrol_new rt5670_mono_adc_r2_mux =
1037
+
SOC_DAPM_ENUM("Mono ADC2 right source", rt5670_mono_adc_r2_enum);
1038
+
1039
+
/* MX-2D [3:2] */
1040
+
static const char * const rt5670_txdp_slot_src[] = {
1041
+
"Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
1042
+
};
1043
+
1044
+
static const SOC_ENUM_SINGLE_DECL(
1045
+
rt5670_txdp_slot_enum, RT5670_DSP_PATH1,
1046
+
RT5670_TXDP_SLOT_SEL_SFT, rt5670_txdp_slot_src);
1047
+
1048
+
static const struct snd_kcontrol_new rt5670_txdp_slot_mux =
1049
+
SOC_DAPM_ENUM("TxDP Slot source", rt5670_txdp_slot_enum);
1050
+
1051
+
/* MX-2F [15] */
1052
+
static const char * const rt5670_if1_adc2_in_src[] = {
1053
+
"IF_ADC2", "VAD_ADC"
1054
+
};
1055
+
1056
+
static const SOC_ENUM_SINGLE_DECL(
1057
+
rt5670_if1_adc2_in_enum, RT5670_DIG_INF1_DATA,
1058
+
RT5670_IF1_ADC2_IN_SFT, rt5670_if1_adc2_in_src);
1059
+
1060
+
static const struct snd_kcontrol_new rt5670_if1_adc2_in_mux =
1061
+
SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5670_if1_adc2_in_enum);
1062
+
1063
+
/* MX-2F [14:12] */
1064
+
static const char * const rt5670_if2_adc_in_src[] = {
1065
+
"IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
1066
+
};
1067
+
1068
+
static const SOC_ENUM_SINGLE_DECL(
1069
+
rt5670_if2_adc_in_enum, RT5670_DIG_INF1_DATA,
1070
+
RT5670_IF2_ADC_IN_SFT, rt5670_if2_adc_in_src);
1071
+
1072
+
static const struct snd_kcontrol_new rt5670_if2_adc_in_mux =
1073
+
SOC_DAPM_ENUM("IF2 ADC IN source", rt5670_if2_adc_in_enum);
1074
+
1075
+
/* MX-30 [5:4] */
1076
+
static const char * const rt5670_if4_adc_in_src[] = {
1077
+
"IF_ADC1", "IF_ADC2", "IF_ADC3"
1078
+
};
1079
+
1080
+
static const SOC_ENUM_SINGLE_DECL(
1081
+
rt5670_if4_adc_in_enum, RT5670_DIG_INF2_DATA,
1082
+
RT5670_IF4_ADC_IN_SFT, rt5670_if4_adc_in_src);
1083
+
1084
+
static const struct snd_kcontrol_new rt5670_if4_adc_in_mux =
1085
+
SOC_DAPM_ENUM("IF4 ADC IN source", rt5670_if4_adc_in_enum);
1086
+
1087
+
/* MX-31 [15] [13] [11] [9] */
1088
+
static const char * const rt5670_pdm_src[] = {
1089
+
"Mono DAC", "Stereo DAC"
1090
+
};
1091
+
1092
+
static const SOC_ENUM_SINGLE_DECL(
1093
+
rt5670_pdm1_l_enum, RT5670_PDM_OUT_CTRL,
1094
+
RT5670_PDM1_L_SFT, rt5670_pdm_src);
1095
+
1096
+
static const struct snd_kcontrol_new rt5670_pdm1_l_mux =
1097
+
SOC_DAPM_ENUM("PDM1 L source", rt5670_pdm1_l_enum);
1098
+
1099
+
static const SOC_ENUM_SINGLE_DECL(
1100
+
rt5670_pdm1_r_enum, RT5670_PDM_OUT_CTRL,
1101
+
RT5670_PDM1_R_SFT, rt5670_pdm_src);
1102
+
1103
+
static const struct snd_kcontrol_new rt5670_pdm1_r_mux =
1104
+
SOC_DAPM_ENUM("PDM1 R source", rt5670_pdm1_r_enum);
1105
+
1106
+
static const SOC_ENUM_SINGLE_DECL(
1107
+
rt5670_pdm2_l_enum, RT5670_PDM_OUT_CTRL,
1108
+
RT5670_PDM2_L_SFT, rt5670_pdm_src);
1109
+
1110
+
static const struct snd_kcontrol_new rt5670_pdm2_l_mux =
1111
+
SOC_DAPM_ENUM("PDM2 L source", rt5670_pdm2_l_enum);
1112
+
1113
+
static const SOC_ENUM_SINGLE_DECL(
1114
+
rt5670_pdm2_r_enum, RT5670_PDM_OUT_CTRL,
1115
+
RT5670_PDM2_R_SFT, rt5670_pdm_src);
1116
+
1117
+
static const struct snd_kcontrol_new rt5670_pdm2_r_mux =
1118
+
SOC_DAPM_ENUM("PDM2 R source", rt5670_pdm2_r_enum);
1119
+
1120
+
/* MX-FA [12] */
1121
+
static const char * const rt5670_if1_adc1_in1_src[] = {
1122
+
"IF_ADC1", "IF1_ADC3"
1123
+
};
1124
+
1125
+
static const SOC_ENUM_SINGLE_DECL(
1126
+
rt5670_if1_adc1_in1_enum, RT5670_DIG_MISC,
1127
+
RT5670_IF1_ADC1_IN1_SFT, rt5670_if1_adc1_in1_src);
1128
+
1129
+
static const struct snd_kcontrol_new rt5670_if1_adc1_in1_mux =
1130
+
SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5670_if1_adc1_in1_enum);
1131
+
1132
+
/* MX-FA [11] */
1133
+
static const char * const rt5670_if1_adc1_in2_src[] = {
1134
+
"IF1_ADC1_IN1", "IF1_ADC4"
1135
+
};
1136
+
1137
+
static const SOC_ENUM_SINGLE_DECL(
1138
+
rt5670_if1_adc1_in2_enum, RT5670_DIG_MISC,
1139
+
RT5670_IF1_ADC1_IN2_SFT, rt5670_if1_adc1_in2_src);
1140
+
1141
+
static const struct snd_kcontrol_new rt5670_if1_adc1_in2_mux =
1142
+
SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5670_if1_adc1_in2_enum);
1143
+
1144
+
/* MX-FA [10] */
1145
+
static const char * const rt5670_if1_adc2_in1_src[] = {
1146
+
"IF1_ADC2_IN", "IF1_ADC4"
1147
+
};
1148
+
1149
+
static const SOC_ENUM_SINGLE_DECL(
1150
+
rt5670_if1_adc2_in1_enum, RT5670_DIG_MISC,
1151
+
RT5670_IF1_ADC2_IN1_SFT, rt5670_if1_adc2_in1_src);
1152
+
1153
+
static const struct snd_kcontrol_new rt5670_if1_adc2_in1_mux =
1154
+
SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5670_if1_adc2_in1_enum);
1155
+
1156
+
/* MX-9D [9:8] */
1157
+
static const char * const rt5670_vad_adc_src[] = {
1158
+
"Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
1159
+
};
1160
+
1161
+
static const SOC_ENUM_SINGLE_DECL(
1162
+
rt5670_vad_adc_enum, RT5670_VAD_CTRL4,
1163
+
RT5670_VAD_SEL_SFT, rt5670_vad_adc_src);
1164
+
1165
+
static const struct snd_kcontrol_new rt5670_vad_adc_mux =
1166
+
SOC_DAPM_ENUM("VAD ADC source", rt5670_vad_adc_enum);
1167
+
1168
+
static int rt5670_hp_power_event(struct snd_soc_dapm_widget *w,
1169
+
struct snd_kcontrol *kcontrol, int event)
1170
+
{
1171
+
struct snd_soc_codec *codec = w->codec;
1172
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
1173
+
1174
+
switch (event) {
1175
+
case SND_SOC_DAPM_POST_PMU:
1176
+
regmap_update_bits(rt5670->regmap, RT5670_CHARGE_PUMP,
1177
+
RT5670_PM_HP_MASK, RT5670_PM_HP_HV);
1178
+
regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1179
+
0x0400, 0x0400);
1180
+
/* headphone amp power on */
1181
+
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
1182
+
RT5670_PWR_HA | RT5670_PWR_FV1 |
1183
+
RT5670_PWR_FV2, RT5670_PWR_HA |
1184
+
RT5670_PWR_FV1 | RT5670_PWR_FV2);
1185
+
/* depop parameters */
1186
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M2, 0x3100);
1187
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8009);
1188
+
regmap_write(rt5670->regmap, RT5670_PR_BASE +
1189
+
RT5670_HP_DCC_INT1, 0x9f00);
1190
+
mdelay(20);
1191
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1192
+
break;
1193
+
case SND_SOC_DAPM_PRE_PMD:
1194
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x0004);
1195
+
msleep(30);
1196
+
break;
1197
+
default:
1198
+
return 0;
1199
+
}
1200
+
1201
+
return 0;
1202
+
}
1203
+
1204
+
static int rt5670_hp_event(struct snd_soc_dapm_widget *w,
1205
+
struct snd_kcontrol *kcontrol, int event)
1206
+
{
1207
+
struct snd_soc_codec *codec = w->codec;
1208
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
1209
+
1210
+
switch (event) {
1211
+
case SND_SOC_DAPM_POST_PMU:
1212
+
/* headphone unmute sequence */
1213
+
regmap_write(rt5670->regmap, RT5670_PR_BASE +
1214
+
RT5670_MAMP_INT_REG2, 0xb400);
1215
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1216
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x805d);
1217
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1218
+
regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1219
+
0x0300, 0x0300);
1220
+
regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1221
+
RT5670_L_MUTE | RT5670_R_MUTE, 0);
1222
+
msleep(80);
1223
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1224
+
break;
1225
+
1226
+
case SND_SOC_DAPM_PRE_PMD:
1227
+
/* headphone mute sequence */
1228
+
regmap_write(rt5670->regmap, RT5670_PR_BASE +
1229
+
RT5670_MAMP_INT_REG2, 0xb400);
1230
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1231
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x803d);
1232
+
mdelay(10);
1233
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1234
+
mdelay(10);
1235
+
regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1236
+
RT5670_L_MUTE | RT5670_R_MUTE,
1237
+
RT5670_L_MUTE | RT5670_R_MUTE);
1238
+
msleep(20);
1239
+
regmap_update_bits(rt5670->regmap,
1240
+
RT5670_GEN_CTRL2, 0x0300, 0x0);
1241
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1242
+
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0707);
1243
+
regmap_write(rt5670->regmap, RT5670_PR_BASE +
1244
+
RT5670_MAMP_INT_REG2, 0xfc00);
1245
+
break;
1246
+
1247
+
default:
1248
+
return 0;
1249
+
}
1250
+
1251
+
return 0;
1252
+
}
1253
+
1254
+
static int rt5670_bst1_event(struct snd_soc_dapm_widget *w,
1255
+
struct snd_kcontrol *kcontrol, int event)
1256
+
{
1257
+
struct snd_soc_codec *codec = w->codec;
1258
+
1259
+
switch (event) {
1260
+
case SND_SOC_DAPM_POST_PMU:
1261
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1262
+
RT5670_PWR_BST1_P, RT5670_PWR_BST1_P);
1263
+
break;
1264
+
1265
+
case SND_SOC_DAPM_PRE_PMD:
1266
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1267
+
RT5670_PWR_BST1_P, 0);
1268
+
break;
1269
+
1270
+
default:
1271
+
return 0;
1272
+
}
1273
+
1274
+
return 0;
1275
+
}
1276
+
1277
+
static int rt5670_bst2_event(struct snd_soc_dapm_widget *w,
1278
+
struct snd_kcontrol *kcontrol, int event)
1279
+
{
1280
+
struct snd_soc_codec *codec = w->codec;
1281
+
1282
+
switch (event) {
1283
+
case SND_SOC_DAPM_POST_PMU:
1284
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1285
+
RT5670_PWR_BST2_P, RT5670_PWR_BST2_P);
1286
+
break;
1287
+
1288
+
case SND_SOC_DAPM_PRE_PMD:
1289
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1290
+
RT5670_PWR_BST2_P, 0);
1291
+
break;
1292
+
1293
+
default:
1294
+
return 0;
1295
+
}
1296
+
1297
+
return 0;
1298
+
}
1299
+
1300
+
static const struct snd_soc_dapm_widget rt5670_dapm_widgets[] = {
1301
+
SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
1302
+
RT5670_PWR_PLL_BIT, 0, NULL, 0),
1303
+
SND_SOC_DAPM_SUPPLY("I2S DSP", RT5670_PWR_DIG2,
1304
+
RT5670_PWR_I2S_DSP_BIT, 0, NULL, 0),
1305
+
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5670_PWR_VOL,
1306
+
RT5670_PWR_MIC_DET_BIT, 0, NULL, 0),
1307
+
1308
+
/* ASRC */
1309
+
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5670_ASRC_1,
1310
+
11, 0, NULL, 0),
1311
+
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5670_ASRC_1,
1312
+
12, 0, NULL, 0),
1313
+
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5670_ASRC_1,
1314
+
10, 0, NULL, 0),
1315
+
SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5670_ASRC_1,
1316
+
9, 0, NULL, 0),
1317
+
SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5670_ASRC_1,
1318
+
8, 0, NULL, 0),
1319
+
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5670_ASRC_1,
1320
+
3, 0, NULL, 0),
1321
+
SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5670_ASRC_1,
1322
+
2, 0, NULL, 0),
1323
+
SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5670_ASRC_1,
1324
+
1, 0, NULL, 0),
1325
+
SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5670_ASRC_1,
1326
+
0, 0, NULL, 0),
1327
+
1328
+
/* Input Side */
1329
+
/* micbias */
1330
+
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5670_PWR_ANLG2,
1331
+
RT5670_PWR_MB1_BIT, 0, NULL, 0),
1332
+
1333
+
/* Input Lines */
1334
+
SND_SOC_DAPM_INPUT("DMIC L1"),
1335
+
SND_SOC_DAPM_INPUT("DMIC R1"),
1336
+
SND_SOC_DAPM_INPUT("DMIC L2"),
1337
+
SND_SOC_DAPM_INPUT("DMIC R2"),
1338
+
SND_SOC_DAPM_INPUT("DMIC L3"),
1339
+
SND_SOC_DAPM_INPUT("DMIC R3"),
1340
+
1341
+
SND_SOC_DAPM_INPUT("IN1P"),
1342
+
SND_SOC_DAPM_INPUT("IN1N"),
1343
+
SND_SOC_DAPM_INPUT("IN2P"),
1344
+
SND_SOC_DAPM_INPUT("IN2N"),
1345
+
1346
+
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1347
+
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1348
+
SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1349
+
1350
+
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1351
+
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1352
+
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5670_DMIC_CTRL1,
1353
+
RT5670_DMIC_1_EN_SFT, 0, NULL, 0),
1354
+
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5670_DMIC_CTRL1,
1355
+
RT5670_DMIC_2_EN_SFT, 0, NULL, 0),
1356
+
SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5670_DMIC_CTRL1,
1357
+
RT5670_DMIC_3_EN_SFT, 0, NULL, 0),
1358
+
/* Boost */
1359
+
SND_SOC_DAPM_PGA_E("BST1", RT5670_PWR_ANLG2, RT5670_PWR_BST1_BIT,
1360
+
0, NULL, 0, rt5670_bst1_event,
1361
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1362
+
SND_SOC_DAPM_PGA_E("BST2", RT5670_PWR_ANLG2, RT5670_PWR_BST2_BIT,
1363
+
0, NULL, 0, rt5670_bst2_event,
1364
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1365
+
/* Input Volume */
1366
+
SND_SOC_DAPM_PGA("INL VOL", RT5670_PWR_VOL,
1367
+
RT5670_PWR_IN_L_BIT, 0, NULL, 0),
1368
+
SND_SOC_DAPM_PGA("INR VOL", RT5670_PWR_VOL,
1369
+
RT5670_PWR_IN_R_BIT, 0, NULL, 0),
1370
+
1371
+
/* REC Mixer */
1372
+
SND_SOC_DAPM_MIXER("RECMIXL", RT5670_PWR_MIXER, RT5670_PWR_RM_L_BIT, 0,
1373
+
rt5670_rec_l_mix, ARRAY_SIZE(rt5670_rec_l_mix)),
1374
+
SND_SOC_DAPM_MIXER("RECMIXR", RT5670_PWR_MIXER, RT5670_PWR_RM_R_BIT, 0,
1375
+
rt5670_rec_r_mix, ARRAY_SIZE(rt5670_rec_r_mix)),
1376
+
/* ADCs */
1377
+
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
1378
+
SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
1379
+
1380
+
SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1381
+
1382
+
SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5670_PWR_DIG1,
1383
+
RT5670_PWR_ADC_L_BIT, 0, NULL, 0),
1384
+
SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5670_PWR_DIG1,
1385
+
RT5670_PWR_ADC_R_BIT, 0, NULL, 0),
1386
+
SND_SOC_DAPM_SUPPLY("ADC clock", RT5670_PR_BASE +
1387
+
RT5670_CHOP_DAC_ADC, 12, 0, NULL, 0),
1388
+
/* ADC Mux */
1389
+
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1390
+
&rt5670_sto1_dmic_mux),
1391
+
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1392
+
&rt5670_sto_adc_l2_mux),
1393
+
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1394
+
&rt5670_sto_adc_r2_mux),
1395
+
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1396
+
&rt5670_sto_adc_l1_mux),
1397
+
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1398
+
&rt5670_sto_adc_r1_mux),
1399
+
SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1400
+
&rt5670_sto2_dmic_mux),
1401
+
SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1402
+
&rt5670_sto2_adc_l2_mux),
1403
+
SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1404
+
&rt5670_sto2_adc_r2_mux),
1405
+
SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1406
+
&rt5670_sto2_adc_l1_mux),
1407
+
SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1408
+
&rt5670_sto2_adc_r1_mux),
1409
+
SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1410
+
&rt5670_sto2_adc_lr_mux),
1411
+
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1412
+
&rt5670_mono_dmic_l_mux),
1413
+
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1414
+
&rt5670_mono_dmic_r_mux),
1415
+
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1416
+
&rt5670_mono_adc_l2_mux),
1417
+
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1418
+
&rt5670_mono_adc_l1_mux),
1419
+
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1420
+
&rt5670_mono_adc_r1_mux),
1421
+
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1422
+
&rt5670_mono_adc_r2_mux),
1423
+
/* ADC Mixer */
1424
+
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5670_PWR_DIG2,
1425
+
RT5670_PWR_ADC_S1F_BIT, 0, NULL, 0),
1426
+
SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5670_PWR_DIG2,
1427
+
RT5670_PWR_ADC_S2F_BIT, 0, NULL, 0),
1428
+
SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", RT5670_STO1_ADC_DIG_VOL,
1429
+
RT5670_L_MUTE_SFT, 1, rt5670_sto1_adc_l_mix,
1430
+
ARRAY_SIZE(rt5670_sto1_adc_l_mix)),
1431
+
SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", RT5670_STO1_ADC_DIG_VOL,
1432
+
RT5670_R_MUTE_SFT, 1, rt5670_sto1_adc_r_mix,
1433
+
ARRAY_SIZE(rt5670_sto1_adc_r_mix)),
1434
+
SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1435
+
rt5670_sto2_adc_l_mix,
1436
+
ARRAY_SIZE(rt5670_sto2_adc_l_mix)),
1437
+
SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1438
+
rt5670_sto2_adc_r_mix,
1439
+
ARRAY_SIZE(rt5670_sto2_adc_r_mix)),
1440
+
SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5670_PWR_DIG2,
1441
+
RT5670_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1442
+
SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5670_MONO_ADC_DIG_VOL,
1443
+
RT5670_L_MUTE_SFT, 1, rt5670_mono_adc_l_mix,
1444
+
ARRAY_SIZE(rt5670_mono_adc_l_mix)),
1445
+
SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5670_PWR_DIG2,
1446
+
RT5670_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1447
+
SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5670_MONO_ADC_DIG_VOL,
1448
+
RT5670_R_MUTE_SFT, 1, rt5670_mono_adc_r_mix,
1449
+
ARRAY_SIZE(rt5670_mono_adc_r_mix)),
1450
+
1451
+
/* ADC PGA */
1452
+
SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1453
+
SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1454
+
SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1455
+
SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1456
+
SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1457
+
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1458
+
SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1459
+
SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1460
+
SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1461
+
SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1462
+
SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1463
+
SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1464
+
SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1465
+
SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1466
+
SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1467
+
SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1468
+
1469
+
/* DSP */
1470
+
SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1471
+
SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
1472
+
SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
1473
+
SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1474
+
1475
+
SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
1476
+
&rt5670_txdp_slot_mux),
1477
+
1478
+
SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
1479
+
&rt5670_dsp_ul_mux),
1480
+
SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
1481
+
&rt5670_dsp_dl_mux),
1482
+
1483
+
SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
1484
+
&rt5670_rxdp_mux),
1485
+
1486
+
/* IF2 Mux */
1487
+
SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
1488
+
&rt5670_if2_adc_in_mux),
1489
+
1490
+
/* Digital Interface */
1491
+
SND_SOC_DAPM_SUPPLY("I2S1", RT5670_PWR_DIG1,
1492
+
RT5670_PWR_I2S1_BIT, 0, NULL, 0),
1493
+
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1494
+
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1495
+
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1496
+
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1497
+
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1498
+
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1499
+
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1500
+
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1501
+
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1502
+
SND_SOC_DAPM_SUPPLY("I2S2", RT5670_PWR_DIG1,
1503
+
RT5670_PWR_I2S2_BIT, 0, NULL, 0),
1504
+
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1505
+
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1506
+
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1507
+
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1508
+
SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1509
+
SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1510
+
1511
+
/* Digital Interface Select */
1512
+
SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
1513
+
&rt5670_if1_adc1_in1_mux),
1514
+
SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
1515
+
&rt5670_if1_adc1_in2_mux),
1516
+
SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
1517
+
&rt5670_if1_adc2_in_mux),
1518
+
SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
1519
+
&rt5670_if1_adc2_in1_mux),
1520
+
SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1521
+
&rt5670_vad_adc_mux),
1522
+
1523
+
/* Audio Interface */
1524
+
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1525
+
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1526
+
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1527
+
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1528
+
RT5670_GPIO_CTRL1, RT5670_I2S2_PIN_SFT, 1),
1529
+
1530
+
/* Audio DSP */
1531
+
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1532
+
1533
+
/* Output Side */
1534
+
/* DAC mixer before sound effect */
1535
+
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1536
+
rt5670_dac_l_mix, ARRAY_SIZE(rt5670_dac_l_mix)),
1537
+
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1538
+
rt5670_dac_r_mix, ARRAY_SIZE(rt5670_dac_r_mix)),
1539
+
SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1540
+
1541
+
/* DAC2 channel Mux */
1542
+
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1543
+
&rt5670_dac_l2_mux),
1544
+
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1545
+
&rt5670_dac_r2_mux),
1546
+
SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
1547
+
RT5670_PWR_DAC_L2_BIT, 0, NULL, 0),
1548
+
SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
1549
+
RT5670_PWR_DAC_R2_BIT, 0, NULL, 0),
1550
+
1551
+
SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1l_mux),
1552
+
SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1r_mux),
1553
+
1554
+
/* DAC Mixer */
1555
+
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5670_PWR_DIG2,
1556
+
RT5670_PWR_DAC_S1F_BIT, 0, NULL, 0),
1557
+
SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5670_PWR_DIG2,
1558
+
RT5670_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1559
+
SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5670_PWR_DIG2,
1560
+
RT5670_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1561
+
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1562
+
rt5670_sto_dac_l_mix,
1563
+
ARRAY_SIZE(rt5670_sto_dac_l_mix)),
1564
+
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1565
+
rt5670_sto_dac_r_mix,
1566
+
ARRAY_SIZE(rt5670_sto_dac_r_mix)),
1567
+
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1568
+
rt5670_mono_dac_l_mix,
1569
+
ARRAY_SIZE(rt5670_mono_dac_l_mix)),
1570
+
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1571
+
rt5670_mono_dac_r_mix,
1572
+
ARRAY_SIZE(rt5670_mono_dac_r_mix)),
1573
+
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1574
+
rt5670_dig_l_mix,
1575
+
ARRAY_SIZE(rt5670_dig_l_mix)),
1576
+
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1577
+
rt5670_dig_r_mix,
1578
+
ARRAY_SIZE(rt5670_dig_r_mix)),
1579
+
1580
+
/* DACs */
1581
+
SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5670_PWR_DIG1,
1582
+
RT5670_PWR_DAC_L1_BIT, 0, NULL, 0),
1583
+
SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
1584
+
RT5670_PWR_DAC_R1_BIT, 0, NULL, 0),
1585
+
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1586
+
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1587
+
SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
1588
+
RT5670_PWR_DAC_L2_BIT, 0),
1589
+
1590
+
SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
1591
+
RT5670_PWR_DAC_R2_BIT, 0),
1592
+
/* OUT Mixer */
1593
+
1594
+
SND_SOC_DAPM_MIXER("OUT MIXL", RT5670_PWR_MIXER, RT5670_PWR_OM_L_BIT,
1595
+
0, rt5670_out_l_mix, ARRAY_SIZE(rt5670_out_l_mix)),
1596
+
SND_SOC_DAPM_MIXER("OUT MIXR", RT5670_PWR_MIXER, RT5670_PWR_OM_R_BIT,
1597
+
0, rt5670_out_r_mix, ARRAY_SIZE(rt5670_out_r_mix)),
1598
+
/* Ouput Volume */
1599
+
SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5670_PWR_VOL,
1600
+
RT5670_PWR_HV_L_BIT, 0,
1601
+
rt5670_hpvoll_mix, ARRAY_SIZE(rt5670_hpvoll_mix)),
1602
+
SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5670_PWR_VOL,
1603
+
RT5670_PWR_HV_R_BIT, 0,
1604
+
rt5670_hpvolr_mix, ARRAY_SIZE(rt5670_hpvolr_mix)),
1605
+
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1606
+
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1607
+
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1608
+
1609
+
/* HPO/LOUT/Mono Mixer */
1610
+
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
1611
+
rt5670_hpo_mix, ARRAY_SIZE(rt5670_hpo_mix)),
1612
+
SND_SOC_DAPM_MIXER("LOUT MIX", RT5670_PWR_ANLG1, RT5670_PWR_LM_BIT,
1613
+
0, rt5670_lout_mix, ARRAY_SIZE(rt5670_lout_mix)),
1614
+
SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 0, 0,
1615
+
rt5670_hp_power_event, SND_SOC_DAPM_POST_PMU |
1616
+
SND_SOC_DAPM_PRE_PMD),
1617
+
SND_SOC_DAPM_SUPPLY("HP L Amp", RT5670_PWR_ANLG1,
1618
+
RT5670_PWR_HP_L_BIT, 0, NULL, 0),
1619
+
SND_SOC_DAPM_SUPPLY("HP R Amp", RT5670_PWR_ANLG1,
1620
+
RT5670_PWR_HP_R_BIT, 0, NULL, 0),
1621
+
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
1622
+
rt5670_hp_event, SND_SOC_DAPM_PRE_PMD |
1623
+
SND_SOC_DAPM_POST_PMU),
1624
+
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1625
+
&lout_l_enable_control),
1626
+
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1627
+
&lout_r_enable_control),
1628
+
SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
1629
+
1630
+
/* PDM */
1631
+
SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5670_PWR_DIG2,
1632
+
RT5670_PWR_PDM1_BIT, 0, NULL, 0),
1633
+
SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5670_PWR_DIG2,
1634
+
RT5670_PWR_PDM2_BIT, 0, NULL, 0),
1635
+
1636
+
SND_SOC_DAPM_MUX("PDM1 L Mux", RT5670_PDM_OUT_CTRL,
1637
+
RT5670_M_PDM1_L_SFT, 1, &rt5670_pdm1_l_mux),
1638
+
SND_SOC_DAPM_MUX("PDM1 R Mux", RT5670_PDM_OUT_CTRL,
1639
+
RT5670_M_PDM1_R_SFT, 1, &rt5670_pdm1_r_mux),
1640
+
SND_SOC_DAPM_MUX("PDM2 L Mux", RT5670_PDM_OUT_CTRL,
1641
+
RT5670_M_PDM2_L_SFT, 1, &rt5670_pdm2_l_mux),
1642
+
SND_SOC_DAPM_MUX("PDM2 R Mux", RT5670_PDM_OUT_CTRL,
1643
+
RT5670_M_PDM2_R_SFT, 1, &rt5670_pdm2_r_mux),
1644
+
1645
+
/* Output Lines */
1646
+
SND_SOC_DAPM_OUTPUT("HPOL"),
1647
+
SND_SOC_DAPM_OUTPUT("HPOR"),
1648
+
SND_SOC_DAPM_OUTPUT("LOUTL"),
1649
+
SND_SOC_DAPM_OUTPUT("LOUTR"),
1650
+
SND_SOC_DAPM_OUTPUT("PDM1L"),
1651
+
SND_SOC_DAPM_OUTPUT("PDM1R"),
1652
+
SND_SOC_DAPM_OUTPUT("PDM2L"),
1653
+
SND_SOC_DAPM_OUTPUT("PDM2R"),
1654
+
};
1655
+
1656
+
static const struct snd_soc_dapm_route rt5670_dapm_routes[] = {
1657
+
{ "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1658
+
{ "ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1659
+
{ "ADC Mono Left Filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1660
+
{ "ADC Mono Right Filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1661
+
{ "DAC Mono Left Filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1662
+
{ "DAC Mono Right Filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1663
+
{ "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
1664
+
1665
+
{ "I2S1", NULL, "I2S1 ASRC" },
1666
+
{ "I2S2", NULL, "I2S2 ASRC" },
1667
+
1668
+
{ "DMIC1", NULL, "DMIC L1" },
1669
+
{ "DMIC1", NULL, "DMIC R1" },
1670
+
{ "DMIC2", NULL, "DMIC L2" },
1671
+
{ "DMIC2", NULL, "DMIC R2" },
1672
+
{ "DMIC3", NULL, "DMIC L3" },
1673
+
{ "DMIC3", NULL, "DMIC R3" },
1674
+
1675
+
{ "BST1", NULL, "IN1P" },
1676
+
{ "BST1", NULL, "IN1N" },
1677
+
{ "BST1", NULL, "Mic Det Power" },
1678
+
{ "BST2", NULL, "IN2P" },
1679
+
{ "BST2", NULL, "IN2N" },
1680
+
1681
+
{ "INL VOL", NULL, "IN2P" },
1682
+
{ "INR VOL", NULL, "IN2N" },
1683
+
1684
+
{ "RECMIXL", "INL Switch", "INL VOL" },
1685
+
{ "RECMIXL", "BST2 Switch", "BST2" },
1686
+
{ "RECMIXL", "BST1 Switch", "BST1" },
1687
+
1688
+
{ "RECMIXR", "INR Switch", "INR VOL" },
1689
+
{ "RECMIXR", "BST2 Switch", "BST2" },
1690
+
{ "RECMIXR", "BST1 Switch", "BST1" },
1691
+
1692
+
{ "ADC 1", NULL, "RECMIXL" },
1693
+
{ "ADC 1", NULL, "ADC 1 power" },
1694
+
{ "ADC 1", NULL, "ADC clock" },
1695
+
{ "ADC 2", NULL, "RECMIXR" },
1696
+
{ "ADC 2", NULL, "ADC 2 power" },
1697
+
{ "ADC 2", NULL, "ADC clock" },
1698
+
1699
+
{ "DMIC L1", NULL, "DMIC CLK" },
1700
+
{ "DMIC L1", NULL, "DMIC1 Power" },
1701
+
{ "DMIC R1", NULL, "DMIC CLK" },
1702
+
{ "DMIC R1", NULL, "DMIC1 Power" },
1703
+
{ "DMIC L2", NULL, "DMIC CLK" },
1704
+
{ "DMIC L2", NULL, "DMIC2 Power" },
1705
+
{ "DMIC R2", NULL, "DMIC CLK" },
1706
+
{ "DMIC R2", NULL, "DMIC2 Power" },
1707
+
{ "DMIC L3", NULL, "DMIC CLK" },
1708
+
{ "DMIC L3", NULL, "DMIC3 Power" },
1709
+
{ "DMIC R3", NULL, "DMIC CLK" },
1710
+
{ "DMIC R3", NULL, "DMIC3 Power" },
1711
+
1712
+
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1713
+
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1714
+
{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
1715
+
1716
+
{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
1717
+
{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
1718
+
{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
1719
+
1720
+
{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1721
+
{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1722
+
{ "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
1723
+
1724
+
{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1725
+
{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1726
+
{ "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
1727
+
1728
+
{ "ADC 1_2", NULL, "ADC 1" },
1729
+
{ "ADC 1_2", NULL, "ADC 2" },
1730
+
1731
+
{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1732
+
{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1733
+
{ "Stereo1 ADC L1 Mux", "ADC", "ADC 1_2" },
1734
+
{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1735
+
1736
+
{ "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
1737
+
{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1738
+
{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1739
+
{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1740
+
1741
+
{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1742
+
{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1743
+
{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1744
+
{ "Mono ADC L1 Mux", "ADC1", "ADC 1" },
1745
+
1746
+
{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1747
+
{ "Mono ADC R1 Mux", "ADC2", "ADC 2" },
1748
+
{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1749
+
{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1750
+
1751
+
{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1752
+
{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1753
+
{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1754
+
{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1755
+
1756
+
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1757
+
{ "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
1758
+
{ "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1759
+
1760
+
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1761
+
{ "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
1762
+
{ "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1763
+
1764
+
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1765
+
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1766
+
{ "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
1767
+
{ "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
1768
+
1769
+
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1770
+
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1771
+
{ "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
1772
+
{ "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
1773
+
1774
+
{ "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
1775
+
{ "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1776
+
{ "Stereo2 ADC L1 Mux", "ADC", "ADC 1_2" },
1777
+
{ "Stereo2 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1778
+
1779
+
{ "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
1780
+
{ "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1781
+
{ "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
1782
+
{ "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1783
+
1784
+
{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux" },
1785
+
{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
1786
+
{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
1787
+
{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
1788
+
1789
+
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
1790
+
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
1791
+
1792
+
{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
1793
+
{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
1794
+
1795
+
{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
1796
+
{ "Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter" },
1797
+
{ "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1798
+
1799
+
{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
1800
+
{ "Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter" },
1801
+
{ "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1802
+
1803
+
{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1804
+
{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1805
+
{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1806
+
{ "VAD ADC Mux", "Sto2 ADC L", "Sto2 ADC MIXL" },
1807
+
1808
+
{ "VAD_ADC", NULL, "VAD ADC Mux" },
1809
+
1810
+
{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1811
+
{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1812
+
{ "IF_ADC2", NULL, "Mono ADC MIXL" },
1813
+
{ "IF_ADC2", NULL, "Mono ADC MIXR" },
1814
+
{ "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
1815
+
{ "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
1816
+
1817
+
{ "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
1818
+
{ "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF1_ADC3" },
1819
+
1820
+
{ "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
1821
+
{ "IF1 ADC1 IN2 Mux", "IF1_ADC4", "IF1_ADC4" },
1822
+
1823
+
{ "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
1824
+
{ "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
1825
+
1826
+
{ "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
1827
+
{ "IF1 ADC2 IN1 Mux", "IF1_ADC4", "IF1_ADC4" },
1828
+
1829
+
{ "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
1830
+
{ "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
1831
+
1832
+
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
1833
+
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
1834
+
{ "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXL" },
1835
+
{ "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXR" },
1836
+
{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
1837
+
{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
1838
+
1839
+
{ "RxDP Mux", "IF2 DAC", "IF2 DAC" },
1840
+
{ "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
1841
+
{ "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
1842
+
{ "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
1843
+
{ "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
1844
+
{ "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
1845
+
{ "RxDP Mux", "DAC1", "DAC MIX" },
1846
+
1847
+
{ "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
1848
+
{ "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
1849
+
{ "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
1850
+
{ "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
1851
+
1852
+
{ "DSP UL Mux", "Bypass", "TDM Data Mux" },
1853
+
{ "DSP UL Mux", NULL, "I2S DSP" },
1854
+
{ "DSP DL Mux", "Bypass", "RxDP Mux" },
1855
+
{ "DSP DL Mux", NULL, "I2S DSP" },
1856
+
1857
+
{ "TxDP_ADC_L", NULL, "DSP UL Mux" },
1858
+
{ "TxDP_ADC_R", NULL, "DSP UL Mux" },
1859
+
{ "TxDC_DAC", NULL, "DSP DL Mux" },
1860
+
1861
+
{ "TxDP_ADC", NULL, "TxDP_ADC_L" },
1862
+
{ "TxDP_ADC", NULL, "TxDP_ADC_R" },
1863
+
1864
+
{ "IF1 ADC", NULL, "I2S1" },
1865
+
{ "IF1 ADC", NULL, "IF1_ADC1" },
1866
+
{ "IF1 ADC", NULL, "IF1_ADC2" },
1867
+
{ "IF1 ADC", NULL, "IF_ADC3" },
1868
+
{ "IF1 ADC", NULL, "TxDP_ADC" },
1869
+
1870
+
{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1871
+
{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1872
+
{ "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
1873
+
{ "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
1874
+
{ "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
1875
+
{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1876
+
1877
+
{ "IF2 ADC L", NULL, "IF2 ADC Mux" },
1878
+
{ "IF2 ADC R", NULL, "IF2 ADC Mux" },
1879
+
1880
+
{ "IF2 ADC", NULL, "I2S2" },
1881
+
{ "IF2 ADC", NULL, "IF2 ADC L" },
1882
+
{ "IF2 ADC", NULL, "IF2 ADC R" },
1883
+
1884
+
{ "AIF1TX", NULL, "IF1 ADC" },
1885
+
{ "AIF2TX", NULL, "IF2 ADC" },
1886
+
1887
+
{ "IF1 DAC1", NULL, "AIF1RX" },
1888
+
{ "IF1 DAC2", NULL, "AIF1RX" },
1889
+
{ "IF2 DAC", NULL, "AIF2RX" },
1890
+
1891
+
{ "IF1 DAC1", NULL, "I2S1" },
1892
+
{ "IF1 DAC2", NULL, "I2S1" },
1893
+
{ "IF2 DAC", NULL, "I2S2" },
1894
+
1895
+
{ "IF1 DAC2 L", NULL, "IF1 DAC2" },
1896
+
{ "IF1 DAC2 R", NULL, "IF1 DAC2" },
1897
+
{ "IF1 DAC1 L", NULL, "IF1 DAC1" },
1898
+
{ "IF1 DAC1 R", NULL, "IF1 DAC1" },
1899
+
{ "IF2 DAC L", NULL, "IF2 DAC" },
1900
+
{ "IF2 DAC R", NULL, "IF2 DAC" },
1901
+
1902
+
{ "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1903
+
{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1904
+
1905
+
{ "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1906
+
{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1907
+
1908
+
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1909
+
{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1910
+
{ "DAC1 MIXL", NULL, "DAC Stereo1 Filter" },
1911
+
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1912
+
{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1913
+
{ "DAC1 MIXR", NULL, "DAC Stereo1 Filter" },
1914
+
1915
+
{ "DAC MIX", NULL, "DAC1 MIXL" },
1916
+
{ "DAC MIX", NULL, "DAC1 MIXR" },
1917
+
1918
+
{ "Audio DSP", NULL, "DAC1 MIXL" },
1919
+
{ "Audio DSP", NULL, "DAC1 MIXR" },
1920
+
1921
+
{ "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1922
+
{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1923
+
{ "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
1924
+
{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1925
+
{ "DAC L2 Volume", NULL, "DAC L2 Mux" },
1926
+
{ "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
1927
+
1928
+
{ "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1929
+
{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1930
+
{ "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
1931
+
{ "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
1932
+
{ "DAC R2 Volume", NULL, "DAC R2 Mux" },
1933
+
{ "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
1934
+
1935
+
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1936
+
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1937
+
{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1938
+
{ "Stereo DAC MIXL", NULL, "DAC Stereo1 Filter" },
1939
+
{ "Stereo DAC MIXL", NULL, "DAC L1 Power" },
1940
+
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1941
+
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1942
+
{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1943
+
{ "Stereo DAC MIXR", NULL, "DAC Stereo1 Filter" },
1944
+
{ "Stereo DAC MIXR", NULL, "DAC R1 Power" },
1945
+
1946
+
{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1947
+
{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1948
+
{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1949
+
{ "Mono DAC MIXL", NULL, "DAC Mono Left Filter" },
1950
+
{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1951
+
{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1952
+
{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1953
+
{ "Mono DAC MIXR", NULL, "DAC Mono Right Filter" },
1954
+
1955
+
{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1956
+
{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1957
+
{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1958
+
{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1959
+
{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1960
+
{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1961
+
1962
+
{ "DAC L1", NULL, "DAC L1 Power" },
1963
+
{ "DAC L1", NULL, "Stereo DAC MIXL" },
1964
+
{ "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1965
+
{ "DAC R1", NULL, "DAC R1 Power" },
1966
+
{ "DAC R1", NULL, "Stereo DAC MIXR" },
1967
+
{ "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1968
+
{ "DAC L2", NULL, "Mono DAC MIXL" },
1969
+
{ "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1970
+
{ "DAC R2", NULL, "Mono DAC MIXR" },
1971
+
{ "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1972
+
1973
+
{ "OUT MIXL", "BST1 Switch", "BST1" },
1974
+
{ "OUT MIXL", "INL Switch", "INL VOL" },
1975
+
{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1976
+
{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1977
+
1978
+
{ "OUT MIXR", "BST2 Switch", "BST2" },
1979
+
{ "OUT MIXR", "INR Switch", "INR VOL" },
1980
+
{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1981
+
{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1982
+
1983
+
{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1984
+
{ "HPOVOL MIXL", "INL Switch", "INL VOL" },
1985
+
{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1986
+
{ "HPOVOL MIXR", "INR Switch", "INR VOL" },
1987
+
1988
+
{ "DAC 2", NULL, "DAC L2" },
1989
+
{ "DAC 2", NULL, "DAC R2" },
1990
+
{ "DAC 1", NULL, "DAC L1" },
1991
+
{ "DAC 1", NULL, "DAC R1" },
1992
+
{ "HPOVOL", NULL, "HPOVOL MIXL" },
1993
+
{ "HPOVOL", NULL, "HPOVOL MIXR" },
1994
+
{ "HPO MIX", "DAC1 Switch", "DAC 1" },
1995
+
{ "HPO MIX", "HPVOL Switch", "HPOVOL" },
1996
+
1997
+
{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1998
+
{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1999
+
{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2000
+
{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2001
+
2002
+
{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2003
+
{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2004
+
{ "PDM1 L Mux", NULL, "PDM1 Power" },
2005
+
{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2006
+
{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2007
+
{ "PDM1 R Mux", NULL, "PDM1 Power" },
2008
+
{ "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2009
+
{ "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
2010
+
{ "PDM2 L Mux", NULL, "PDM2 Power" },
2011
+
{ "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2012
+
{ "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
2013
+
{ "PDM2 R Mux", NULL, "PDM2 Power" },
2014
+
2015
+
{ "HP Amp", NULL, "HPO MIX" },
2016
+
{ "HP Amp", NULL, "Mic Det Power" },
2017
+
{ "HPOL", NULL, "HP Amp" },
2018
+
{ "HPOL", NULL, "HP L Amp" },
2019
+
{ "HPOL", NULL, "Improve HP Amp Drv" },
2020
+
{ "HPOR", NULL, "HP Amp" },
2021
+
{ "HPOR", NULL, "HP R Amp" },
2022
+
{ "HPOR", NULL, "Improve HP Amp Drv" },
2023
+
2024
+
{ "LOUT Amp", NULL, "LOUT MIX" },
2025
+
{ "LOUT L Playback", "Switch", "LOUT Amp" },
2026
+
{ "LOUT R Playback", "Switch", "LOUT Amp" },
2027
+
{ "LOUTL", NULL, "LOUT L Playback" },
2028
+
{ "LOUTR", NULL, "LOUT R Playback" },
2029
+
{ "LOUTL", NULL, "Improve HP Amp Drv" },
2030
+
{ "LOUTR", NULL, "Improve HP Amp Drv" },
2031
+
2032
+
{ "PDM1L", NULL, "PDM1 L Mux" },
2033
+
{ "PDM1R", NULL, "PDM1 R Mux" },
2034
+
{ "PDM2L", NULL, "PDM2 L Mux" },
2035
+
{ "PDM2R", NULL, "PDM2 R Mux" },
2036
+
};
2037
+
2038
+
static int rt5670_hw_params(struct snd_pcm_substream *substream,
2039
+
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2040
+
{
2041
+
struct snd_soc_codec *codec = dai->codec;
2042
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2043
+
unsigned int val_len = 0, val_clk, mask_clk;
2044
+
int pre_div, bclk_ms, frame_size;
2045
+
2046
+
rt5670->lrck[dai->id] = params_rate(params);
2047
+
pre_div = rl6231_get_clk_info(rt5670->sysclk, rt5670->lrck[dai->id]);
2048
+
if (pre_div < 0) {
2049
+
dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2050
+
rt5670->lrck[dai->id], dai->id);
2051
+
return -EINVAL;
2052
+
}
2053
+
frame_size = snd_soc_params_to_frame_size(params);
2054
+
if (frame_size < 0) {
2055
+
dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2056
+
return -EINVAL;
2057
+
}
2058
+
bclk_ms = frame_size > 32;
2059
+
rt5670->bclk[dai->id] = rt5670->lrck[dai->id] * (32 << bclk_ms);
2060
+
2061
+
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2062
+
rt5670->bclk[dai->id], rt5670->lrck[dai->id]);
2063
+
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2064
+
bclk_ms, pre_div, dai->id);
2065
+
2066
+
switch (params_width(params)) {
2067
+
case 16:
2068
+
break;
2069
+
case 20:
2070
+
val_len |= RT5670_I2S_DL_20;
2071
+
break;
2072
+
case 24:
2073
+
val_len |= RT5670_I2S_DL_24;
2074
+
break;
2075
+
case 8:
2076
+
val_len |= RT5670_I2S_DL_8;
2077
+
break;
2078
+
default:
2079
+
return -EINVAL;
2080
+
}
2081
+
2082
+
switch (dai->id) {
2083
+
case RT5670_AIF1:
2084
+
mask_clk = RT5670_I2S_BCLK_MS1_MASK | RT5670_I2S_PD1_MASK;
2085
+
val_clk = bclk_ms << RT5670_I2S_BCLK_MS1_SFT |
2086
+
pre_div << RT5670_I2S_PD1_SFT;
2087
+
snd_soc_update_bits(codec, RT5670_I2S1_SDP,
2088
+
RT5670_I2S_DL_MASK, val_len);
2089
+
snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
2090
+
break;
2091
+
case RT5670_AIF2:
2092
+
mask_clk = RT5670_I2S_BCLK_MS2_MASK | RT5670_I2S_PD2_MASK;
2093
+
val_clk = bclk_ms << RT5670_I2S_BCLK_MS2_SFT |
2094
+
pre_div << RT5670_I2S_PD2_SFT;
2095
+
snd_soc_update_bits(codec, RT5670_I2S2_SDP,
2096
+
RT5670_I2S_DL_MASK, val_len);
2097
+
snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
2098
+
break;
2099
+
default:
2100
+
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2101
+
return -EINVAL;
2102
+
}
2103
+
2104
+
return 0;
2105
+
}
2106
+
2107
+
static int rt5670_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2108
+
{
2109
+
struct snd_soc_codec *codec = dai->codec;
2110
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2111
+
unsigned int reg_val = 0;
2112
+
2113
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2114
+
case SND_SOC_DAIFMT_CBM_CFM:
2115
+
rt5670->master[dai->id] = 1;
2116
+
break;
2117
+
case SND_SOC_DAIFMT_CBS_CFS:
2118
+
reg_val |= RT5670_I2S_MS_S;
2119
+
rt5670->master[dai->id] = 0;
2120
+
break;
2121
+
default:
2122
+
return -EINVAL;
2123
+
}
2124
+
2125
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2126
+
case SND_SOC_DAIFMT_NB_NF:
2127
+
break;
2128
+
case SND_SOC_DAIFMT_IB_NF:
2129
+
reg_val |= RT5670_I2S_BP_INV;
2130
+
break;
2131
+
default:
2132
+
return -EINVAL;
2133
+
}
2134
+
2135
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2136
+
case SND_SOC_DAIFMT_I2S:
2137
+
break;
2138
+
case SND_SOC_DAIFMT_LEFT_J:
2139
+
reg_val |= RT5670_I2S_DF_LEFT;
2140
+
break;
2141
+
case SND_SOC_DAIFMT_DSP_A:
2142
+
reg_val |= RT5670_I2S_DF_PCM_A;
2143
+
break;
2144
+
case SND_SOC_DAIFMT_DSP_B:
2145
+
reg_val |= RT5670_I2S_DF_PCM_B;
2146
+
break;
2147
+
default:
2148
+
return -EINVAL;
2149
+
}
2150
+
2151
+
switch (dai->id) {
2152
+
case RT5670_AIF1:
2153
+
snd_soc_update_bits(codec, RT5670_I2S1_SDP,
2154
+
RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2155
+
RT5670_I2S_DF_MASK, reg_val);
2156
+
break;
2157
+
case RT5670_AIF2:
2158
+
snd_soc_update_bits(codec, RT5670_I2S2_SDP,
2159
+
RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2160
+
RT5670_I2S_DF_MASK, reg_val);
2161
+
break;
2162
+
default:
2163
+
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2164
+
return -EINVAL;
2165
+
}
2166
+
return 0;
2167
+
}
2168
+
2169
+
static int rt5670_set_dai_sysclk(struct snd_soc_dai *dai,
2170
+
int clk_id, unsigned int freq, int dir)
2171
+
{
2172
+
struct snd_soc_codec *codec = dai->codec;
2173
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2174
+
unsigned int reg_val = 0;
2175
+
2176
+
if (freq == rt5670->sysclk && clk_id == rt5670->sysclk_src)
2177
+
return 0;
2178
+
2179
+
switch (clk_id) {
2180
+
case RT5670_SCLK_S_MCLK:
2181
+
reg_val |= RT5670_SCLK_SRC_MCLK;
2182
+
break;
2183
+
case RT5670_SCLK_S_PLL1:
2184
+
reg_val |= RT5670_SCLK_SRC_PLL1;
2185
+
break;
2186
+
case RT5670_SCLK_S_RCCLK:
2187
+
reg_val |= RT5670_SCLK_SRC_RCCLK;
2188
+
break;
2189
+
default:
2190
+
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2191
+
return -EINVAL;
2192
+
}
2193
+
snd_soc_update_bits(codec, RT5670_GLB_CLK,
2194
+
RT5670_SCLK_SRC_MASK, reg_val);
2195
+
rt5670->sysclk = freq;
2196
+
rt5670->sysclk_src = clk_id;
2197
+
2198
+
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2199
+
2200
+
return 0;
2201
+
}
2202
+
2203
+
static int rt5670_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2204
+
unsigned int freq_in, unsigned int freq_out)
2205
+
{
2206
+
struct snd_soc_codec *codec = dai->codec;
2207
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2208
+
struct rl6231_pll_code pll_code;
2209
+
int ret;
2210
+
2211
+
if (source == rt5670->pll_src && freq_in == rt5670->pll_in &&
2212
+
freq_out == rt5670->pll_out)
2213
+
return 0;
2214
+
2215
+
if (!freq_in || !freq_out) {
2216
+
dev_dbg(codec->dev, "PLL disabled\n");
2217
+
2218
+
rt5670->pll_in = 0;
2219
+
rt5670->pll_out = 0;
2220
+
snd_soc_update_bits(codec, RT5670_GLB_CLK,
2221
+
RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_MCLK);
2222
+
return 0;
2223
+
}
2224
+
2225
+
switch (source) {
2226
+
case RT5670_PLL1_S_MCLK:
2227
+
snd_soc_update_bits(codec, RT5670_GLB_CLK,
2228
+
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_MCLK);
2229
+
break;
2230
+
case RT5670_PLL1_S_BCLK1:
2231
+
case RT5670_PLL1_S_BCLK2:
2232
+
case RT5670_PLL1_S_BCLK3:
2233
+
case RT5670_PLL1_S_BCLK4:
2234
+
switch (dai->id) {
2235
+
case RT5670_AIF1:
2236
+
snd_soc_update_bits(codec, RT5670_GLB_CLK,
2237
+
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK1);
2238
+
break;
2239
+
case RT5670_AIF2:
2240
+
snd_soc_update_bits(codec, RT5670_GLB_CLK,
2241
+
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK2);
2242
+
break;
2243
+
default:
2244
+
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2245
+
return -EINVAL;
2246
+
}
2247
+
break;
2248
+
default:
2249
+
dev_err(codec->dev, "Unknown PLL source %d\n", source);
2250
+
return -EINVAL;
2251
+
}
2252
+
2253
+
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2254
+
if (ret < 0) {
2255
+
dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2256
+
return ret;
2257
+
}
2258
+
2259
+
dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2260
+
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2261
+
pll_code.n_code, pll_code.k_code);
2262
+
2263
+
snd_soc_write(codec, RT5670_PLL_CTRL1,
2264
+
pll_code.n_code << RT5670_PLL_N_SFT | pll_code.k_code);
2265
+
snd_soc_write(codec, RT5670_PLL_CTRL2,
2266
+
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5670_PLL_M_SFT |
2267
+
pll_code.m_bp << RT5670_PLL_M_BP_SFT);
2268
+
2269
+
rt5670->pll_in = freq_in;
2270
+
rt5670->pll_out = freq_out;
2271
+
rt5670->pll_src = source;
2272
+
2273
+
return 0;
2274
+
}
2275
+
2276
+
static int rt5670_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2277
+
unsigned int rx_mask, int slots, int slot_width)
2278
+
{
2279
+
struct snd_soc_codec *codec = dai->codec;
2280
+
unsigned int val = 0;
2281
+
2282
+
if (rx_mask || tx_mask)
2283
+
val |= (1 << 14);
2284
+
2285
+
switch (slots) {
2286
+
case 4:
2287
+
val |= (1 << 12);
2288
+
break;
2289
+
case 6:
2290
+
val |= (2 << 12);
2291
+
break;
2292
+
case 8:
2293
+
val |= (3 << 12);
2294
+
break;
2295
+
case 2:
2296
+
break;
2297
+
default:
2298
+
return -EINVAL;
2299
+
}
2300
+
2301
+
switch (slot_width) {
2302
+
case 20:
2303
+
val |= (1 << 10);
2304
+
break;
2305
+
case 24:
2306
+
val |= (2 << 10);
2307
+
break;
2308
+
case 32:
2309
+
val |= (3 << 10);
2310
+
break;
2311
+
case 16:
2312
+
break;
2313
+
default:
2314
+
return -EINVAL;
2315
+
}
2316
+
2317
+
snd_soc_update_bits(codec, RT5670_TDM_CTRL_1, 0x7c00, val);
2318
+
2319
+
return 0;
2320
+
}
2321
+
2322
+
static int rt5670_set_bias_level(struct snd_soc_codec *codec,
2323
+
enum snd_soc_bias_level level)
2324
+
{
2325
+
switch (level) {
2326
+
case SND_SOC_BIAS_PREPARE:
2327
+
if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
2328
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2329
+
RT5670_PWR_VREF1 | RT5670_PWR_MB |
2330
+
RT5670_PWR_BG | RT5670_PWR_VREF2,
2331
+
RT5670_PWR_VREF1 | RT5670_PWR_MB |
2332
+
RT5670_PWR_BG | RT5670_PWR_VREF2);
2333
+
mdelay(10);
2334
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2335
+
RT5670_PWR_FV1 | RT5670_PWR_FV2,
2336
+
RT5670_PWR_FV1 | RT5670_PWR_FV2);
2337
+
snd_soc_update_bits(codec, RT5670_CHARGE_PUMP,
2338
+
RT5670_OSW_L_MASK | RT5670_OSW_R_MASK,
2339
+
RT5670_OSW_L_DIS | RT5670_OSW_R_DIS);
2340
+
snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x1);
2341
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2342
+
RT5670_LDO_SEL_MASK, 0x3);
2343
+
}
2344
+
break;
2345
+
case SND_SOC_BIAS_STANDBY:
2346
+
snd_soc_write(codec, RT5670_PWR_DIG1, 0x0000);
2347
+
snd_soc_write(codec, RT5670_PWR_DIG2, 0x0001);
2348
+
snd_soc_write(codec, RT5670_PWR_VOL, 0x0000);
2349
+
snd_soc_write(codec, RT5670_PWR_MIXER, 0x0001);
2350
+
snd_soc_write(codec, RT5670_PWR_ANLG1, 0x2800);
2351
+
snd_soc_write(codec, RT5670_PWR_ANLG2, 0x0004);
2352
+
snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x0);
2353
+
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2354
+
RT5670_LDO_SEL_MASK, 0x1);
2355
+
break;
2356
+
2357
+
default:
2358
+
break;
2359
+
}
2360
+
codec->dapm.bias_level = level;
2361
+
2362
+
return 0;
2363
+
}
2364
+
2365
+
static int rt5670_probe(struct snd_soc_codec *codec)
2366
+
{
2367
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2368
+
2369
+
rt5670->codec = codec;
2370
+
2371
+
return 0;
2372
+
}
2373
+
2374
+
static int rt5670_remove(struct snd_soc_codec *codec)
2375
+
{
2376
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2377
+
2378
+
regmap_write(rt5670->regmap, RT5670_RESET, 0);
2379
+
return 0;
2380
+
}
2381
+
2382
+
#ifdef CONFIG_PM
2383
+
static int rt5670_suspend(struct snd_soc_codec *codec)
2384
+
{
2385
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2386
+
2387
+
regcache_cache_only(rt5670->regmap, true);
2388
+
regcache_mark_dirty(rt5670->regmap);
2389
+
return 0;
2390
+
}
2391
+
2392
+
static int rt5670_resume(struct snd_soc_codec *codec)
2393
+
{
2394
+
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2395
+
2396
+
regcache_cache_only(rt5670->regmap, false);
2397
+
regcache_sync(rt5670->regmap);
2398
+
2399
+
return 0;
2400
+
}
2401
+
#else
2402
+
#define rt5670_suspend NULL
2403
+
#define rt5670_resume NULL
2404
+
#endif
2405
+
2406
+
#define RT5670_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2407
+
#define RT5670_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2408
+
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2409
+
2410
+
struct snd_soc_dai_ops rt5670_aif_dai_ops = {
2411
+
.hw_params = rt5670_hw_params,
2412
+
.set_fmt = rt5670_set_dai_fmt,
2413
+
.set_sysclk = rt5670_set_dai_sysclk,
2414
+
.set_tdm_slot = rt5670_set_tdm_slot,
2415
+
.set_pll = rt5670_set_dai_pll,
2416
+
};
2417
+
2418
+
struct snd_soc_dai_driver rt5670_dai[] = {
2419
+
{
2420
+
.name = "rt5670-aif1",
2421
+
.id = RT5670_AIF1,
2422
+
.playback = {
2423
+
.stream_name = "AIF1 Playback",
2424
+
.channels_min = 1,
2425
+
.channels_max = 2,
2426
+
.rates = RT5670_STEREO_RATES,
2427
+
.formats = RT5670_FORMATS,
2428
+
},
2429
+
.capture = {
2430
+
.stream_name = "AIF1 Capture",
2431
+
.channels_min = 1,
2432
+
.channels_max = 2,
2433
+
.rates = RT5670_STEREO_RATES,
2434
+
.formats = RT5670_FORMATS,
2435
+
},
2436
+
.ops = &rt5670_aif_dai_ops,
2437
+
},
2438
+
{
2439
+
.name = "rt5670-aif2",
2440
+
.id = RT5670_AIF2,
2441
+
.playback = {
2442
+
.stream_name = "AIF2 Playback",
2443
+
.channels_min = 1,
2444
+
.channels_max = 2,
2445
+
.rates = RT5670_STEREO_RATES,
2446
+
.formats = RT5670_FORMATS,
2447
+
},
2448
+
.capture = {
2449
+
.stream_name = "AIF2 Capture",
2450
+
.channels_min = 1,
2451
+
.channels_max = 2,
2452
+
.rates = RT5670_STEREO_RATES,
2453
+
.formats = RT5670_FORMATS,
2454
+
},
2455
+
.ops = &rt5670_aif_dai_ops,
2456
+
},
2457
+
};
2458
+
2459
+
static struct snd_soc_codec_driver soc_codec_dev_rt5670 = {
2460
+
.probe = rt5670_probe,
2461
+
.remove = rt5670_remove,
2462
+
.suspend = rt5670_suspend,
2463
+
.resume = rt5670_resume,
2464
+
.set_bias_level = rt5670_set_bias_level,
2465
+
.idle_bias_off = true,
2466
+
.controls = rt5670_snd_controls,
2467
+
.num_controls = ARRAY_SIZE(rt5670_snd_controls),
2468
+
.dapm_widgets = rt5670_dapm_widgets,
2469
+
.num_dapm_widgets = ARRAY_SIZE(rt5670_dapm_widgets),
2470
+
.dapm_routes = rt5670_dapm_routes,
2471
+
.num_dapm_routes = ARRAY_SIZE(rt5670_dapm_routes),
2472
+
};
2473
+
2474
+
static const struct regmap_config rt5670_regmap = {
2475
+
.reg_bits = 8,
2476
+
.val_bits = 16,
2477
+
.max_register = RT5670_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5670_ranges) *
2478
+
RT5670_PR_SPACING),
2479
+
.volatile_reg = rt5670_volatile_register,
2480
+
.readable_reg = rt5670_readable_register,
2481
+
.cache_type = REGCACHE_RBTREE,
2482
+
.reg_defaults = rt5670_reg,
2483
+
.num_reg_defaults = ARRAY_SIZE(rt5670_reg),
2484
+
.ranges = rt5670_ranges,
2485
+
.num_ranges = ARRAY_SIZE(rt5670_ranges),
2486
+
};
2487
+
2488
+
static const struct i2c_device_id rt5670_i2c_id[] = {
2489
+
{ "rt5670", 0 },
2490
+
{ }
2491
+
};
2492
+
MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);
2493
+
2494
+
static int rt5670_i2c_probe(struct i2c_client *i2c,
2495
+
const struct i2c_device_id *id)
2496
+
{
2497
+
struct rt5670_platform_data *pdata = dev_get_platdata(&i2c->dev);
2498
+
struct rt5670_priv *rt5670;
2499
+
int ret;
2500
+
unsigned int val;
2501
+
2502
+
rt5670 = devm_kzalloc(&i2c->dev,
2503
+
sizeof(struct rt5670_priv),
2504
+
GFP_KERNEL);
2505
+
if (NULL == rt5670)
2506
+
return -ENOMEM;
2507
+
2508
+
i2c_set_clientdata(i2c, rt5670);
2509
+
2510
+
if (pdata)
2511
+
rt5670->pdata = *pdata;
2512
+
2513
+
rt5670->regmap = devm_regmap_init_i2c(i2c, &rt5670_regmap);
2514
+
if (IS_ERR(rt5670->regmap)) {
2515
+
ret = PTR_ERR(rt5670->regmap);
2516
+
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2517
+
ret);
2518
+
return ret;
2519
+
}
2520
+
2521
+
regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val);
2522
+
if (val != RT5670_DEVICE_ID) {
2523
+
dev_err(&i2c->dev,
2524
+
"Device with ID register %x is not rt5670/72\n", val);
2525
+
return -ENODEV;
2526
+
}
2527
+
2528
+
regmap_write(rt5670->regmap, RT5670_RESET, 0);
2529
+
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
2530
+
RT5670_PWR_HP_L | RT5670_PWR_HP_R |
2531
+
RT5670_PWR_VREF2, RT5670_PWR_VREF2);
2532
+
msleep(100);
2533
+
2534
+
regmap_write(rt5670->regmap, RT5670_RESET, 0);
2535
+
2536
+
ret = regmap_register_patch(rt5670->regmap, init_list,
2537
+
ARRAY_SIZE(init_list));
2538
+
if (ret != 0)
2539
+
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2540
+
2541
+
if (rt5670->pdata.in2_diff)
2542
+
regmap_update_bits(rt5670->regmap, RT5670_IN2,
2543
+
RT5670_IN_DF2, RT5670_IN_DF2);
2544
+
2545
+
if (i2c->irq) {
2546
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2547
+
RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
2548
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
2549
+
RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
2550
+
2551
+
}
2552
+
2553
+
if (rt5670->pdata.jd_mode) {
2554
+
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
2555
+
RT5670_PWR_MB, RT5670_PWR_MB);
2556
+
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2,
2557
+
RT5670_PWR_JD1, RT5670_PWR_JD1);
2558
+
regmap_update_bits(rt5670->regmap, RT5670_IRQ_CTRL1,
2559
+
RT5670_JD1_1_EN_MASK, RT5670_JD1_1_EN);
2560
+
regmap_update_bits(rt5670->regmap, RT5670_JD_CTRL3,
2561
+
RT5670_JD_TRI_CBJ_SEL_MASK |
2562
+
RT5670_JD_TRI_HPO_SEL_MASK,
2563
+
RT5670_JD_CBJ_JD1_1 | RT5670_JD_HPO_JD1_1);
2564
+
switch (rt5670->pdata.jd_mode) {
2565
+
case 1:
2566
+
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
2567
+
RT5670_JD1_MODE_MASK,
2568
+
RT5670_JD1_MODE_0);
2569
+
break;
2570
+
case 2:
2571
+
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
2572
+
RT5670_JD1_MODE_MASK,
2573
+
RT5670_JD1_MODE_1);
2574
+
break;
2575
+
case 3:
2576
+
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
2577
+
RT5670_JD1_MODE_MASK,
2578
+
RT5670_JD1_MODE_2);
2579
+
break;
2580
+
default:
2581
+
break;
2582
+
}
2583
+
}
2584
+
2585
+
if (rt5670->pdata.dmic_en) {
2586
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2587
+
RT5670_GP2_PIN_MASK,
2588
+
RT5670_GP2_PIN_DMIC1_SCL);
2589
+
2590
+
switch (rt5670->pdata.dmic1_data_pin) {
2591
+
case RT5670_DMIC_DATA_IN2P:
2592
+
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2593
+
RT5670_DMIC_1_DP_MASK,
2594
+
RT5670_DMIC_1_DP_IN2P);
2595
+
break;
2596
+
2597
+
case RT5670_DMIC_DATA_GPIO6:
2598
+
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2599
+
RT5670_DMIC_1_DP_MASK,
2600
+
RT5670_DMIC_1_DP_GPIO6);
2601
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2602
+
RT5670_GP6_PIN_MASK,
2603
+
RT5670_GP6_PIN_DMIC1_SDA);
2604
+
break;
2605
+
2606
+
case RT5670_DMIC_DATA_GPIO7:
2607
+
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2608
+
RT5670_DMIC_1_DP_MASK,
2609
+
RT5670_DMIC_1_DP_GPIO7);
2610
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2611
+
RT5670_GP7_PIN_MASK,
2612
+
RT5670_GP7_PIN_DMIC1_SDA);
2613
+
break;
2614
+
2615
+
default:
2616
+
break;
2617
+
}
2618
+
2619
+
switch (rt5670->pdata.dmic2_data_pin) {
2620
+
case RT5670_DMIC_DATA_IN3N:
2621
+
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2622
+
RT5670_DMIC_2_DP_MASK,
2623
+
RT5670_DMIC_2_DP_IN3N);
2624
+
break;
2625
+
2626
+
case RT5670_DMIC_DATA_GPIO8:
2627
+
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2628
+
RT5670_DMIC_2_DP_MASK,
2629
+
RT5670_DMIC_2_DP_GPIO8);
2630
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2631
+
RT5670_GP8_PIN_MASK,
2632
+
RT5670_GP8_PIN_DMIC2_SDA);
2633
+
break;
2634
+
2635
+
default:
2636
+
break;
2637
+
}
2638
+
2639
+
switch (rt5670->pdata.dmic3_data_pin) {
2640
+
case RT5670_DMIC_DATA_GPIO5:
2641
+
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL2,
2642
+
RT5670_DMIC_3_DP_MASK,
2643
+
RT5670_DMIC_3_DP_GPIO5);
2644
+
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2645
+
RT5670_GP5_PIN_MASK,
2646
+
RT5670_GP5_PIN_DMIC3_SDA);
2647
+
break;
2648
+
2649
+
case RT5670_DMIC_DATA_GPIO9:
2650
+
case RT5670_DMIC_DATA_GPIO10:
2651
+
dev_err(&i2c->dev,
2652
+
"Always use GPIO5 as DMIC3 data pin\n");
2653
+
break;
2654
+
2655
+
default:
2656
+
break;
2657
+
}
2658
+
2659
+
}
2660
+
2661
+
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5670,
2662
+
rt5670_dai, ARRAY_SIZE(rt5670_dai));
2663
+
if (ret < 0)
2664
+
goto err;
2665
+
2666
+
return 0;
2667
+
err:
2668
+
return ret;
2669
+
}
2670
+
2671
+
static int rt5670_i2c_remove(struct i2c_client *i2c)
2672
+
{
2673
+
snd_soc_unregister_codec(&i2c->dev);
2674
+
2675
+
return 0;
2676
+
}
2677
+
2678
+
struct i2c_driver rt5670_i2c_driver = {
2679
+
.driver = {
2680
+
.name = "rt5670",
2681
+
.owner = THIS_MODULE,
2682
+
},
2683
+
.probe = rt5670_i2c_probe,
2684
+
.remove = rt5670_i2c_remove,
2685
+
.id_table = rt5670_i2c_id,
2686
+
};
2687
+
2688
+
module_i2c_driver(rt5670_i2c_driver);
2689
+
2690
+
MODULE_DESCRIPTION("ASoC RT5670 driver");
2691
+
MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2692
+
MODULE_LICENSE("GPL v2");
+2000
sound/soc/codecs/rt5670.h
+2000
sound/soc/codecs/rt5670.h
···
1
+
/*
2
+
* rt5670.h -- RT5670 ALSA SoC audio driver
3
+
*
4
+
* Copyright 2014 Realtek Microelectronics
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#ifndef __RT5670_H__
13
+
#define __RT5670_H__
14
+
15
+
#include <sound/rt5670.h>
16
+
17
+
/* Info */
18
+
#define RT5670_RESET 0x00
19
+
#define RT5670_VENDOR_ID 0xfd
20
+
#define RT5670_VENDOR_ID1 0xfe
21
+
#define RT5670_VENDOR_ID2 0xff
22
+
/* I/O - Output */
23
+
#define RT5670_HP_VOL 0x02
24
+
#define RT5670_LOUT1 0x03
25
+
/* I/O - Input */
26
+
#define RT5670_CJ_CTRL1 0x0a
27
+
#define RT5670_CJ_CTRL2 0x0b
28
+
#define RT5670_CJ_CTRL3 0x0c
29
+
#define RT5670_IN2 0x0e
30
+
#define RT5670_INL1_INR1_VOL 0x0f
31
+
/* I/O - ADC/DAC/DMIC */
32
+
#define RT5670_DAC1_DIG_VOL 0x19
33
+
#define RT5670_DAC2_DIG_VOL 0x1a
34
+
#define RT5670_DAC_CTRL 0x1b
35
+
#define RT5670_STO1_ADC_DIG_VOL 0x1c
36
+
#define RT5670_MONO_ADC_DIG_VOL 0x1d
37
+
#define RT5670_ADC_BST_VOL1 0x1e
38
+
#define RT5670_STO2_ADC_DIG_VOL 0x1f
39
+
/* Mixer - D-D */
40
+
#define RT5670_ADC_BST_VOL2 0x20
41
+
#define RT5670_STO2_ADC_MIXER 0x26
42
+
#define RT5670_STO1_ADC_MIXER 0x27
43
+
#define RT5670_MONO_ADC_MIXER 0x28
44
+
#define RT5670_AD_DA_MIXER 0x29
45
+
#define RT5670_STO_DAC_MIXER 0x2a
46
+
#define RT5670_DD_MIXER 0x2b
47
+
#define RT5670_DIG_MIXER 0x2c
48
+
#define RT5670_DSP_PATH1 0x2d
49
+
#define RT5670_DSP_PATH2 0x2e
50
+
#define RT5670_DIG_INF1_DATA 0x2f
51
+
#define RT5670_DIG_INF2_DATA 0x30
52
+
/* Mixer - PDM */
53
+
#define RT5670_PDM_OUT_CTRL 0x31
54
+
#define RT5670_PDM_DATA_CTRL1 0x32
55
+
#define RT5670_PDM1_DATA_CTRL2 0x33
56
+
#define RT5670_PDM1_DATA_CTRL3 0x34
57
+
#define RT5670_PDM1_DATA_CTRL4 0x35
58
+
#define RT5670_PDM2_DATA_CTRL2 0x36
59
+
#define RT5670_PDM2_DATA_CTRL3 0x37
60
+
#define RT5670_PDM2_DATA_CTRL4 0x38
61
+
/* Mixer - ADC */
62
+
#define RT5670_REC_L1_MIXER 0x3b
63
+
#define RT5670_REC_L2_MIXER 0x3c
64
+
#define RT5670_REC_R1_MIXER 0x3d
65
+
#define RT5670_REC_R2_MIXER 0x3e
66
+
/* Mixer - DAC */
67
+
#define RT5670_HPO_MIXER 0x45
68
+
#define RT5670_MONO_MIXER 0x4c
69
+
#define RT5670_OUT_L1_MIXER 0x4f
70
+
#define RT5670_OUT_R1_MIXER 0x52
71
+
#define RT5670_LOUT_MIXER 0x53
72
+
/* Power */
73
+
#define RT5670_PWR_DIG1 0x61
74
+
#define RT5670_PWR_DIG2 0x62
75
+
#define RT5670_PWR_ANLG1 0x63
76
+
#define RT5670_PWR_ANLG2 0x64
77
+
#define RT5670_PWR_MIXER 0x65
78
+
#define RT5670_PWR_VOL 0x66
79
+
/* Private Register Control */
80
+
#define RT5670_PRIV_INDEX 0x6a
81
+
#define RT5670_PRIV_DATA 0x6c
82
+
/* Format - ADC/DAC */
83
+
#define RT5670_I2S4_SDP 0x6f
84
+
#define RT5670_I2S1_SDP 0x70
85
+
#define RT5670_I2S2_SDP 0x71
86
+
#define RT5670_I2S3_SDP 0x72
87
+
#define RT5670_ADDA_CLK1 0x73
88
+
#define RT5670_ADDA_CLK2 0x74
89
+
#define RT5670_DMIC_CTRL1 0x75
90
+
#define RT5670_DMIC_CTRL2 0x76
91
+
/* Format - TDM Control */
92
+
#define RT5670_TDM_CTRL_1 0x77
93
+
#define RT5670_TDM_CTRL_2 0x78
94
+
#define RT5670_TDM_CTRL_3 0x79
95
+
96
+
/* Function - Analog */
97
+
#define RT5670_DSP_CLK 0x7f
98
+
#define RT5670_GLB_CLK 0x80
99
+
#define RT5670_PLL_CTRL1 0x81
100
+
#define RT5670_PLL_CTRL2 0x82
101
+
#define RT5670_ASRC_1 0x83
102
+
#define RT5670_ASRC_2 0x84
103
+
#define RT5670_ASRC_3 0x85
104
+
#define RT5670_ASRC_4 0x86
105
+
#define RT5670_ASRC_5 0x87
106
+
#define RT5670_ASRC_7 0x89
107
+
#define RT5670_ASRC_8 0x8a
108
+
#define RT5670_ASRC_9 0x8b
109
+
#define RT5670_ASRC_10 0x8c
110
+
#define RT5670_ASRC_11 0x8d
111
+
#define RT5670_DEPOP_M1 0x8e
112
+
#define RT5670_DEPOP_M2 0x8f
113
+
#define RT5670_DEPOP_M3 0x90
114
+
#define RT5670_CHARGE_PUMP 0x91
115
+
#define RT5670_MICBIAS 0x93
116
+
#define RT5670_A_JD_CTRL1 0x94
117
+
#define RT5670_A_JD_CTRL2 0x95
118
+
#define RT5670_ASRC_12 0x97
119
+
#define RT5670_ASRC_13 0x98
120
+
#define RT5670_ASRC_14 0x99
121
+
#define RT5670_VAD_CTRL1 0x9a
122
+
#define RT5670_VAD_CTRL2 0x9b
123
+
#define RT5670_VAD_CTRL3 0x9c
124
+
#define RT5670_VAD_CTRL4 0x9d
125
+
#define RT5670_VAD_CTRL5 0x9e
126
+
/* Function - Digital */
127
+
#define RT5670_ADC_EQ_CTRL1 0xae
128
+
#define RT5670_ADC_EQ_CTRL2 0xaf
129
+
#define RT5670_EQ_CTRL1 0xb0
130
+
#define RT5670_EQ_CTRL2 0xb1
131
+
#define RT5670_ALC_DRC_CTRL1 0xb2
132
+
#define RT5670_ALC_DRC_CTRL2 0xb3
133
+
#define RT5670_ALC_CTRL_1 0xb4
134
+
#define RT5670_ALC_CTRL_2 0xb5
135
+
#define RT5670_ALC_CTRL_3 0xb6
136
+
#define RT5670_ALC_CTRL_4 0xb7
137
+
#define RT5670_JD_CTRL 0xbb
138
+
#define RT5670_IRQ_CTRL1 0xbd
139
+
#define RT5670_IRQ_CTRL2 0xbe
140
+
#define RT5670_INT_IRQ_ST 0xbf
141
+
#define RT5670_GPIO_CTRL1 0xc0
142
+
#define RT5670_GPIO_CTRL2 0xc1
143
+
#define RT5670_GPIO_CTRL3 0xc2
144
+
#define RT5670_SCRABBLE_FUN 0xcd
145
+
#define RT5670_SCRABBLE_CTRL 0xce
146
+
#define RT5670_BASE_BACK 0xcf
147
+
#define RT5670_MP3_PLUS1 0xd0
148
+
#define RT5670_MP3_PLUS2 0xd1
149
+
#define RT5670_ADJ_HPF1 0xd3
150
+
#define RT5670_ADJ_HPF2 0xd4
151
+
#define RT5670_HP_CALIB_AMP_DET 0xd6
152
+
#define RT5670_SV_ZCD1 0xd9
153
+
#define RT5670_SV_ZCD2 0xda
154
+
#define RT5670_IL_CMD 0xdb
155
+
#define RT5670_IL_CMD2 0xdc
156
+
#define RT5670_IL_CMD3 0xdd
157
+
#define RT5670_DRC_HL_CTRL1 0xe6
158
+
#define RT5670_DRC_HL_CTRL2 0xe7
159
+
#define RT5670_ADC_MONO_HP_CTRL1 0xec
160
+
#define RT5670_ADC_MONO_HP_CTRL2 0xed
161
+
#define RT5670_ADC_STO2_HP_CTRL1 0xee
162
+
#define RT5670_ADC_STO2_HP_CTRL2 0xef
163
+
#define RT5670_JD_CTRL3 0xf8
164
+
#define RT5670_JD_CTRL4 0xf9
165
+
/* General Control */
166
+
#define RT5670_DIG_MISC 0xfa
167
+
#define RT5670_GEN_CTRL2 0xfb
168
+
#define RT5670_GEN_CTRL3 0xfc
169
+
170
+
171
+
/* Index of Codec Private Register definition */
172
+
#define RT5670_DIG_VOL 0x00
173
+
#define RT5670_PR_ALC_CTRL_1 0x01
174
+
#define RT5670_PR_ALC_CTRL_2 0x02
175
+
#define RT5670_PR_ALC_CTRL_3 0x03
176
+
#define RT5670_PR_ALC_CTRL_4 0x04
177
+
#define RT5670_PR_ALC_CTRL_5 0x05
178
+
#define RT5670_PR_ALC_CTRL_6 0x06
179
+
#define RT5670_BIAS_CUR1 0x12
180
+
#define RT5670_BIAS_CUR3 0x14
181
+
#define RT5670_CLSD_INT_REG1 0x1c
182
+
#define RT5670_MAMP_INT_REG2 0x37
183
+
#define RT5670_CHOP_DAC_ADC 0x3d
184
+
#define RT5670_MIXER_INT_REG 0x3f
185
+
#define RT5670_3D_SPK 0x63
186
+
#define RT5670_WND_1 0x6c
187
+
#define RT5670_WND_2 0x6d
188
+
#define RT5670_WND_3 0x6e
189
+
#define RT5670_WND_4 0x6f
190
+
#define RT5670_WND_5 0x70
191
+
#define RT5670_WND_8 0x73
192
+
#define RT5670_DIP_SPK_INF 0x75
193
+
#define RT5670_HP_DCC_INT1 0x77
194
+
#define RT5670_EQ_BW_LOP 0xa0
195
+
#define RT5670_EQ_GN_LOP 0xa1
196
+
#define RT5670_EQ_FC_BP1 0xa2
197
+
#define RT5670_EQ_BW_BP1 0xa3
198
+
#define RT5670_EQ_GN_BP1 0xa4
199
+
#define RT5670_EQ_FC_BP2 0xa5
200
+
#define RT5670_EQ_BW_BP2 0xa6
201
+
#define RT5670_EQ_GN_BP2 0xa7
202
+
#define RT5670_EQ_FC_BP3 0xa8
203
+
#define RT5670_EQ_BW_BP3 0xa9
204
+
#define RT5670_EQ_GN_BP3 0xaa
205
+
#define RT5670_EQ_FC_BP4 0xab
206
+
#define RT5670_EQ_BW_BP4 0xac
207
+
#define RT5670_EQ_GN_BP4 0xad
208
+
#define RT5670_EQ_FC_HIP1 0xae
209
+
#define RT5670_EQ_GN_HIP1 0xaf
210
+
#define RT5670_EQ_FC_HIP2 0xb0
211
+
#define RT5670_EQ_BW_HIP2 0xb1
212
+
#define RT5670_EQ_GN_HIP2 0xb2
213
+
#define RT5670_EQ_PRE_VOL 0xb3
214
+
#define RT5670_EQ_PST_VOL 0xb4
215
+
216
+
217
+
/* global definition */
218
+
#define RT5670_L_MUTE (0x1 << 15)
219
+
#define RT5670_L_MUTE_SFT 15
220
+
#define RT5670_VOL_L_MUTE (0x1 << 14)
221
+
#define RT5670_VOL_L_SFT 14
222
+
#define RT5670_R_MUTE (0x1 << 7)
223
+
#define RT5670_R_MUTE_SFT 7
224
+
#define RT5670_VOL_R_MUTE (0x1 << 6)
225
+
#define RT5670_VOL_R_SFT 6
226
+
#define RT5670_L_VOL_MASK (0x3f << 8)
227
+
#define RT5670_L_VOL_SFT 8
228
+
#define RT5670_R_VOL_MASK (0x3f)
229
+
#define RT5670_R_VOL_SFT 0
230
+
231
+
/* Combo Jack Control 1 (0x0a) */
232
+
#define RT5670_CBJ_BST1_MASK (0xf << 12)
233
+
#define RT5670_CBJ_BST1_SFT (12)
234
+
#define RT5670_CBJ_JD_HP_EN (0x1 << 9)
235
+
#define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
236
+
#define RT5670_CBJ_BST1_EN (0x1 << 2)
237
+
238
+
/* Combo Jack Control 1 (0x0b) */
239
+
#define RT5670_CBJ_MN_JD (0x1 << 12)
240
+
#define RT5670_CAPLESS_EN (0x1 << 11)
241
+
#define RT5670_CBJ_DET_MODE (0x1 << 7)
242
+
243
+
/* IN2 Control (0x0e) */
244
+
#define RT5670_BST_MASK1 (0xf<<12)
245
+
#define RT5670_BST_SFT1 12
246
+
#define RT5670_BST_MASK2 (0xf<<8)
247
+
#define RT5670_BST_SFT2 8
248
+
#define RT5670_IN_DF1 (0x1 << 7)
249
+
#define RT5670_IN_SFT1 7
250
+
#define RT5670_IN_DF2 (0x1 << 6)
251
+
#define RT5670_IN_SFT2 6
252
+
253
+
/* INL and INR Volume Control (0x0f) */
254
+
#define RT5670_INL_SEL_MASK (0x1 << 15)
255
+
#define RT5670_INL_SEL_SFT 15
256
+
#define RT5670_INL_SEL_IN4P (0x0 << 15)
257
+
#define RT5670_INL_SEL_MONOP (0x1 << 15)
258
+
#define RT5670_INL_VOL_MASK (0x1f << 8)
259
+
#define RT5670_INL_VOL_SFT 8
260
+
#define RT5670_INR_SEL_MASK (0x1 << 7)
261
+
#define RT5670_INR_SEL_SFT 7
262
+
#define RT5670_INR_SEL_IN4N (0x0 << 7)
263
+
#define RT5670_INR_SEL_MONON (0x1 << 7)
264
+
#define RT5670_INR_VOL_MASK (0x1f)
265
+
#define RT5670_INR_VOL_SFT 0
266
+
267
+
/* Sidetone Control (0x18) */
268
+
#define RT5670_ST_SEL_MASK (0x7 << 9)
269
+
#define RT5670_ST_SEL_SFT 9
270
+
#define RT5670_M_ST_DACR2 (0x1 << 8)
271
+
#define RT5670_M_ST_DACR2_SFT 8
272
+
#define RT5670_M_ST_DACL2 (0x1 << 7)
273
+
#define RT5670_M_ST_DACL2_SFT 7
274
+
#define RT5670_ST_EN (0x1 << 6)
275
+
#define RT5670_ST_EN_SFT 6
276
+
277
+
/* DAC1 Digital Volume (0x19) */
278
+
#define RT5670_DAC_L1_VOL_MASK (0xff << 8)
279
+
#define RT5670_DAC_L1_VOL_SFT 8
280
+
#define RT5670_DAC_R1_VOL_MASK (0xff)
281
+
#define RT5670_DAC_R1_VOL_SFT 0
282
+
283
+
/* DAC2 Digital Volume (0x1a) */
284
+
#define RT5670_DAC_L2_VOL_MASK (0xff << 8)
285
+
#define RT5670_DAC_L2_VOL_SFT 8
286
+
#define RT5670_DAC_R2_VOL_MASK (0xff)
287
+
#define RT5670_DAC_R2_VOL_SFT 0
288
+
289
+
/* DAC2 Control (0x1b) */
290
+
#define RT5670_M_DAC_L2_VOL (0x1 << 13)
291
+
#define RT5670_M_DAC_L2_VOL_SFT 13
292
+
#define RT5670_M_DAC_R2_VOL (0x1 << 12)
293
+
#define RT5670_M_DAC_R2_VOL_SFT 12
294
+
#define RT5670_DAC2_L_SEL_MASK (0x7 << 4)
295
+
#define RT5670_DAC2_L_SEL_SFT 4
296
+
#define RT5670_DAC2_R_SEL_MASK (0x7 << 0)
297
+
#define RT5670_DAC2_R_SEL_SFT 0
298
+
299
+
/* ADC Digital Volume Control (0x1c) */
300
+
#define RT5670_ADC_L_VOL_MASK (0x7f << 8)
301
+
#define RT5670_ADC_L_VOL_SFT 8
302
+
#define RT5670_ADC_R_VOL_MASK (0x7f)
303
+
#define RT5670_ADC_R_VOL_SFT 0
304
+
305
+
/* Mono ADC Digital Volume Control (0x1d) */
306
+
#define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
307
+
#define RT5670_MONO_ADC_L_VOL_SFT 8
308
+
#define RT5670_MONO_ADC_R_VOL_MASK (0x7f)
309
+
#define RT5670_MONO_ADC_R_VOL_SFT 0
310
+
311
+
/* ADC Boost Volume Control (0x1e) */
312
+
#define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
313
+
#define RT5670_STO1_ADC_L_BST_SFT 14
314
+
#define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
315
+
#define RT5670_STO1_ADC_R_BST_SFT 12
316
+
#define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
317
+
#define RT5670_STO1_ADC_COMP_SFT 10
318
+
#define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
319
+
#define RT5670_STO2_ADC_L_BST_SFT 8
320
+
#define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6)
321
+
#define RT5670_STO2_ADC_R_BST_SFT 6
322
+
#define RT5670_STO2_ADC_COMP_MASK (0x3 << 4)
323
+
#define RT5670_STO2_ADC_COMP_SFT 4
324
+
325
+
/* Stereo2 ADC Mixer Control (0x26) */
326
+
#define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
327
+
#define RT5670_STO2_ADC_SRC_SFT 15
328
+
329
+
/* Stereo ADC Mixer Control (0x26 0x27) */
330
+
#define RT5670_M_ADC_L1 (0x1 << 14)
331
+
#define RT5670_M_ADC_L1_SFT 14
332
+
#define RT5670_M_ADC_L2 (0x1 << 13)
333
+
#define RT5670_M_ADC_L2_SFT 13
334
+
#define RT5670_ADC_1_SRC_MASK (0x1 << 12)
335
+
#define RT5670_ADC_1_SRC_SFT 12
336
+
#define RT5670_ADC_1_SRC_ADC (0x1 << 12)
337
+
#define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
338
+
#define RT5670_ADC_2_SRC_MASK (0x1 << 11)
339
+
#define RT5670_ADC_2_SRC_SFT 11
340
+
#define RT5670_ADC_SRC_MASK (0x1 << 10)
341
+
#define RT5670_ADC_SRC_SFT 10
342
+
#define RT5670_DMIC_SRC_MASK (0x3 << 8)
343
+
#define RT5670_DMIC_SRC_SFT 8
344
+
#define RT5670_M_ADC_R1 (0x1 << 6)
345
+
#define RT5670_M_ADC_R1_SFT 6
346
+
#define RT5670_M_ADC_R2 (0x1 << 5)
347
+
#define RT5670_M_ADC_R2_SFT 5
348
+
#define RT5670_DMIC3_SRC_MASK (0x1 << 1)
349
+
#define RT5670_DMIC3_SRC_SFT 0
350
+
351
+
/* Mono ADC Mixer Control (0x28) */
352
+
#define RT5670_M_MONO_ADC_L1 (0x1 << 14)
353
+
#define RT5670_M_MONO_ADC_L1_SFT 14
354
+
#define RT5670_M_MONO_ADC_L2 (0x1 << 13)
355
+
#define RT5670_M_MONO_ADC_L2_SFT 13
356
+
#define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
357
+
#define RT5670_MONO_ADC_L1_SRC_SFT 12
358
+
#define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
359
+
#define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
360
+
#define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
361
+
#define RT5670_MONO_ADC_L2_SRC_SFT 11
362
+
#define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
363
+
#define RT5670_MONO_ADC_L_SRC_SFT 10
364
+
#define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
365
+
#define RT5670_MONO_DMIC_L_SRC_SFT 8
366
+
#define RT5670_M_MONO_ADC_R1 (0x1 << 6)
367
+
#define RT5670_M_MONO_ADC_R1_SFT 6
368
+
#define RT5670_M_MONO_ADC_R2 (0x1 << 5)
369
+
#define RT5670_M_MONO_ADC_R2_SFT 5
370
+
#define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
371
+
#define RT5670_MONO_ADC_R1_SRC_SFT 4
372
+
#define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
373
+
#define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
374
+
#define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
375
+
#define RT5670_MONO_ADC_R2_SRC_SFT 3
376
+
#define RT5670_MONO_DMIC_R_SRC_MASK (0x3)
377
+
#define RT5670_MONO_DMIC_R_SRC_SFT 0
378
+
379
+
/* ADC Mixer to DAC Mixer Control (0x29) */
380
+
#define RT5670_M_ADCMIX_L (0x1 << 15)
381
+
#define RT5670_M_ADCMIX_L_SFT 15
382
+
#define RT5670_M_DAC1_L (0x1 << 14)
383
+
#define RT5670_M_DAC1_L_SFT 14
384
+
#define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
385
+
#define RT5670_DAC1_R_SEL_SFT 10
386
+
#define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
387
+
#define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
388
+
#define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
389
+
#define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
390
+
#define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
391
+
#define RT5670_DAC1_L_SEL_SFT 8
392
+
#define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
393
+
#define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
394
+
#define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
395
+
#define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
396
+
#define RT5670_M_ADCMIX_R (0x1 << 7)
397
+
#define RT5670_M_ADCMIX_R_SFT 7
398
+
#define RT5670_M_DAC1_R (0x1 << 6)
399
+
#define RT5670_M_DAC1_R_SFT 6
400
+
401
+
/* Stereo DAC Mixer Control (0x2a) */
402
+
#define RT5670_M_DAC_L1 (0x1 << 14)
403
+
#define RT5670_M_DAC_L1_SFT 14
404
+
#define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
405
+
#define RT5670_DAC_L1_STO_L_VOL_SFT 13
406
+
#define RT5670_M_DAC_L2 (0x1 << 12)
407
+
#define RT5670_M_DAC_L2_SFT 12
408
+
#define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
409
+
#define RT5670_DAC_L2_STO_L_VOL_SFT 11
410
+
#define RT5670_M_DAC_R1_STO_L (0x1 << 9)
411
+
#define RT5670_M_DAC_R1_STO_L_SFT 9
412
+
#define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
413
+
#define RT5670_DAC_R1_STO_L_VOL_SFT 8
414
+
#define RT5670_M_DAC_R1 (0x1 << 6)
415
+
#define RT5670_M_DAC_R1_SFT 6
416
+
#define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
417
+
#define RT5670_DAC_R1_STO_R_VOL_SFT 5
418
+
#define RT5670_M_DAC_R2 (0x1 << 4)
419
+
#define RT5670_M_DAC_R2_SFT 4
420
+
#define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
421
+
#define RT5670_DAC_R2_STO_R_VOL_SFT 3
422
+
#define RT5670_M_DAC_L1_STO_R (0x1 << 1)
423
+
#define RT5670_M_DAC_L1_STO_R_SFT 1
424
+
#define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
425
+
#define RT5670_DAC_L1_STO_R_VOL_SFT 0
426
+
427
+
/* Mono DAC Mixer Control (0x2b) */
428
+
#define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
429
+
#define RT5670_M_DAC_L1_MONO_L_SFT 14
430
+
#define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
431
+
#define RT5670_DAC_L1_MONO_L_VOL_SFT 13
432
+
#define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
433
+
#define RT5670_M_DAC_L2_MONO_L_SFT 12
434
+
#define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
435
+
#define RT5670_DAC_L2_MONO_L_VOL_SFT 11
436
+
#define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
437
+
#define RT5670_M_DAC_R2_MONO_L_SFT 10
438
+
#define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
439
+
#define RT5670_DAC_R2_MONO_L_VOL_SFT 9
440
+
#define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
441
+
#define RT5670_M_DAC_R1_MONO_R_SFT 6
442
+
#define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
443
+
#define RT5670_DAC_R1_MONO_R_VOL_SFT 5
444
+
#define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
445
+
#define RT5670_M_DAC_R2_MONO_R_SFT 4
446
+
#define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
447
+
#define RT5670_DAC_R2_MONO_R_VOL_SFT 3
448
+
#define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
449
+
#define RT5670_M_DAC_L2_MONO_R_SFT 2
450
+
#define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
451
+
#define RT5670_DAC_L2_MONO_R_VOL_SFT 1
452
+
453
+
/* Digital Mixer Control (0x2c) */
454
+
#define RT5670_M_STO_L_DAC_L (0x1 << 15)
455
+
#define RT5670_M_STO_L_DAC_L_SFT 15
456
+
#define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
457
+
#define RT5670_STO_L_DAC_L_VOL_SFT 14
458
+
#define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
459
+
#define RT5670_M_DAC_L2_DAC_L_SFT 13
460
+
#define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
461
+
#define RT5670_DAC_L2_DAC_L_VOL_SFT 12
462
+
#define RT5670_M_STO_R_DAC_R (0x1 << 11)
463
+
#define RT5670_M_STO_R_DAC_R_SFT 11
464
+
#define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
465
+
#define RT5670_STO_R_DAC_R_VOL_SFT 10
466
+
#define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
467
+
#define RT5670_M_DAC_R2_DAC_R_SFT 9
468
+
#define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
469
+
#define RT5670_DAC_R2_DAC_R_VOL_SFT 8
470
+
#define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
471
+
#define RT5670_M_DAC_R2_DAC_L_SFT 7
472
+
#define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
473
+
#define RT5670_DAC_R2_DAC_L_VOL_SFT 6
474
+
#define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
475
+
#define RT5670_M_DAC_L2_DAC_R_SFT 5
476
+
#define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
477
+
#define RT5670_DAC_L2_DAC_R_VOL_SFT 4
478
+
479
+
/* DSP Path Control 1 (0x2d) */
480
+
#define RT5670_RXDP_SEL_MASK (0x7 << 13)
481
+
#define RT5670_RXDP_SEL_SFT 13
482
+
#define RT5670_RXDP_SRC_MASK (0x3 << 11)
483
+
#define RT5670_RXDP_SRC_SFT 11
484
+
#define RT5670_RXDP_SRC_NOR (0x0 << 11)
485
+
#define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
486
+
#define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
487
+
#define RT5670_TXDP_SRC_MASK (0x3 << 4)
488
+
#define RT5670_TXDP_SRC_SFT 4
489
+
#define RT5670_TXDP_SRC_NOR (0x0 << 4)
490
+
#define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
491
+
#define RT5670_TXDP_SRC_DIV3 (0x2 << 4)
492
+
#define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2)
493
+
#define RT5670_TXDP_SLOT_SEL_SFT 2
494
+
#define RT5670_DSP_UL_SEL (0x1 << 1)
495
+
#define RT5670_DSP_UL_SFT 1
496
+
#define RT5670_DSP_DL_SEL 0x1
497
+
#define RT5670_DSP_DL_SFT 0
498
+
499
+
/* DSP Path Control 2 (0x2e) */
500
+
#define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
501
+
#define RT5670_TXDP_L_VOL_SFT 8
502
+
#define RT5670_TXDP_R_VOL_MASK (0x7f)
503
+
#define RT5670_TXDP_R_VOL_SFT 0
504
+
505
+
/* Digital Interface Data Control (0x2f) */
506
+
#define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
507
+
#define RT5670_IF1_ADC2_IN_SFT 15
508
+
#define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
509
+
#define RT5670_IF2_ADC_IN_SFT 12
510
+
#define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
511
+
#define RT5670_IF2_DAC_SEL_SFT 10
512
+
#define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
513
+
#define RT5670_IF2_ADC_SEL_SFT 8
514
+
515
+
/* Digital Interface Data Control (0x30) */
516
+
#define RT5670_IF4_ADC_IN_MASK (0x3 << 4)
517
+
#define RT5670_IF4_ADC_IN_SFT 4
518
+
519
+
/* PDM Output Control (0x31) */
520
+
#define RT5670_PDM1_L_MASK (0x1 << 15)
521
+
#define RT5670_PDM1_L_SFT 15
522
+
#define RT5670_M_PDM1_L (0x1 << 14)
523
+
#define RT5670_M_PDM1_L_SFT 14
524
+
#define RT5670_PDM1_R_MASK (0x1 << 13)
525
+
#define RT5670_PDM1_R_SFT 13
526
+
#define RT5670_M_PDM1_R (0x1 << 12)
527
+
#define RT5670_M_PDM1_R_SFT 12
528
+
#define RT5670_PDM2_L_MASK (0x1 << 11)
529
+
#define RT5670_PDM2_L_SFT 11
530
+
#define RT5670_M_PDM2_L (0x1 << 10)
531
+
#define RT5670_M_PDM2_L_SFT 10
532
+
#define RT5670_PDM2_R_MASK (0x1 << 9)
533
+
#define RT5670_PDM2_R_SFT 9
534
+
#define RT5670_M_PDM2_R (0x1 << 8)
535
+
#define RT5670_M_PDM2_R_SFT 8
536
+
#define RT5670_PDM2_BUSY (0x1 << 7)
537
+
#define RT5670_PDM1_BUSY (0x1 << 6)
538
+
#define RT5670_PDM_PATTERN (0x1 << 5)
539
+
#define RT5670_PDM_GAIN (0x1 << 4)
540
+
#define RT5670_PDM_DIV_MASK (0x3)
541
+
542
+
/* REC Left Mixer Control 1 (0x3b) */
543
+
#define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
544
+
#define RT5670_G_HP_L_RM_L_SFT 13
545
+
#define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
546
+
#define RT5670_G_IN_L_RM_L_SFT 10
547
+
#define RT5670_G_BST4_RM_L_MASK (0x7 << 7)
548
+
#define RT5670_G_BST4_RM_L_SFT 7
549
+
#define RT5670_G_BST3_RM_L_MASK (0x7 << 4)
550
+
#define RT5670_G_BST3_RM_L_SFT 4
551
+
#define RT5670_G_BST2_RM_L_MASK (0x7 << 1)
552
+
#define RT5670_G_BST2_RM_L_SFT 1
553
+
554
+
/* REC Left Mixer Control 2 (0x3c) */
555
+
#define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
556
+
#define RT5670_G_BST1_RM_L_SFT 13
557
+
#define RT5670_M_IN_L_RM_L (0x1 << 5)
558
+
#define RT5670_M_IN_L_RM_L_SFT 5
559
+
#define RT5670_M_BST2_RM_L (0x1 << 3)
560
+
#define RT5670_M_BST2_RM_L_SFT 3
561
+
#define RT5670_M_BST1_RM_L (0x1 << 1)
562
+
#define RT5670_M_BST1_RM_L_SFT 1
563
+
564
+
/* REC Right Mixer Control 1 (0x3d) */
565
+
#define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
566
+
#define RT5670_G_HP_R_RM_R_SFT 13
567
+
#define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
568
+
#define RT5670_G_IN_R_RM_R_SFT 10
569
+
#define RT5670_G_BST4_RM_R_MASK (0x7 << 7)
570
+
#define RT5670_G_BST4_RM_R_SFT 7
571
+
#define RT5670_G_BST3_RM_R_MASK (0x7 << 4)
572
+
#define RT5670_G_BST3_RM_R_SFT 4
573
+
#define RT5670_G_BST2_RM_R_MASK (0x7 << 1)
574
+
#define RT5670_G_BST2_RM_R_SFT 1
575
+
576
+
/* REC Right Mixer Control 2 (0x3e) */
577
+
#define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
578
+
#define RT5670_G_BST1_RM_R_SFT 13
579
+
#define RT5670_M_IN_R_RM_R (0x1 << 5)
580
+
#define RT5670_M_IN_R_RM_R_SFT 5
581
+
#define RT5670_M_BST2_RM_R (0x1 << 3)
582
+
#define RT5670_M_BST2_RM_R_SFT 3
583
+
#define RT5670_M_BST1_RM_R (0x1 << 1)
584
+
#define RT5670_M_BST1_RM_R_SFT 1
585
+
586
+
/* HPMIX Control (0x45) */
587
+
#define RT5670_M_DAC2_HM (0x1 << 15)
588
+
#define RT5670_M_DAC2_HM_SFT 15
589
+
#define RT5670_M_HPVOL_HM (0x1 << 14)
590
+
#define RT5670_M_HPVOL_HM_SFT 14
591
+
#define RT5670_M_DAC1_HM (0x1 << 13)
592
+
#define RT5670_M_DAC1_HM_SFT 13
593
+
#define RT5670_G_HPOMIX_MASK (0x1 << 12)
594
+
#define RT5670_G_HPOMIX_SFT 12
595
+
#define RT5670_M_INR1_HMR (0x1 << 3)
596
+
#define RT5670_M_INR1_HMR_SFT 3
597
+
#define RT5670_M_DACR1_HMR (0x1 << 2)
598
+
#define RT5670_M_DACR1_HMR_SFT 2
599
+
#define RT5670_M_INL1_HML (0x1 << 1)
600
+
#define RT5670_M_INL1_HML_SFT 1
601
+
#define RT5670_M_DACL1_HML (0x1)
602
+
#define RT5670_M_DACL1_HML_SFT 0
603
+
604
+
/* Mono Output Mixer Control (0x4c) */
605
+
#define RT5670_M_DAC_R2_MA (0x1 << 15)
606
+
#define RT5670_M_DAC_R2_MA_SFT 15
607
+
#define RT5670_M_DAC_L2_MA (0x1 << 14)
608
+
#define RT5670_M_DAC_L2_MA_SFT 14
609
+
#define RT5670_M_OV_R_MM (0x1 << 13)
610
+
#define RT5670_M_OV_R_MM_SFT 13
611
+
#define RT5670_M_OV_L_MM (0x1 << 12)
612
+
#define RT5670_M_OV_L_MM_SFT 12
613
+
#define RT5670_G_MONOMIX_MASK (0x1 << 10)
614
+
#define RT5670_G_MONOMIX_SFT 10
615
+
#define RT5670_M_DAC_R2_MM (0x1 << 9)
616
+
#define RT5670_M_DAC_R2_MM_SFT 9
617
+
#define RT5670_M_DAC_L2_MM (0x1 << 8)
618
+
#define RT5670_M_DAC_L2_MM_SFT 8
619
+
#define RT5670_M_BST4_MM (0x1 << 7)
620
+
#define RT5670_M_BST4_MM_SFT 7
621
+
622
+
/* Output Left Mixer Control 1 (0x4d) */
623
+
#define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
624
+
#define RT5670_G_BST3_OM_L_SFT 13
625
+
#define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
626
+
#define RT5670_G_BST2_OM_L_SFT 10
627
+
#define RT5670_G_BST1_OM_L_MASK (0x7 << 7)
628
+
#define RT5670_G_BST1_OM_L_SFT 7
629
+
#define RT5670_G_IN_L_OM_L_MASK (0x7 << 4)
630
+
#define RT5670_G_IN_L_OM_L_SFT 4
631
+
#define RT5670_G_RM_L_OM_L_MASK (0x7 << 1)
632
+
#define RT5670_G_RM_L_OM_L_SFT 1
633
+
634
+
/* Output Left Mixer Control 2 (0x4e) */
635
+
#define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
636
+
#define RT5670_G_DAC_R2_OM_L_SFT 13
637
+
#define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
638
+
#define RT5670_G_DAC_L2_OM_L_SFT 10
639
+
#define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7)
640
+
#define RT5670_G_DAC_L1_OM_L_SFT 7
641
+
642
+
/* Output Left Mixer Control 3 (0x4f) */
643
+
#define RT5670_M_BST1_OM_L (0x1 << 5)
644
+
#define RT5670_M_BST1_OM_L_SFT 5
645
+
#define RT5670_M_IN_L_OM_L (0x1 << 4)
646
+
#define RT5670_M_IN_L_OM_L_SFT 4
647
+
#define RT5670_M_DAC_L2_OM_L (0x1 << 1)
648
+
#define RT5670_M_DAC_L2_OM_L_SFT 1
649
+
#define RT5670_M_DAC_L1_OM_L (0x1)
650
+
#define RT5670_M_DAC_L1_OM_L_SFT 0
651
+
652
+
/* Output Right Mixer Control 1 (0x50) */
653
+
#define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
654
+
#define RT5670_G_BST4_OM_R_SFT 13
655
+
#define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
656
+
#define RT5670_G_BST2_OM_R_SFT 10
657
+
#define RT5670_G_BST1_OM_R_MASK (0x7 << 7)
658
+
#define RT5670_G_BST1_OM_R_SFT 7
659
+
#define RT5670_G_IN_R_OM_R_MASK (0x7 << 4)
660
+
#define RT5670_G_IN_R_OM_R_SFT 4
661
+
#define RT5670_G_RM_R_OM_R_MASK (0x7 << 1)
662
+
#define RT5670_G_RM_R_OM_R_SFT 1
663
+
664
+
/* Output Right Mixer Control 2 (0x51) */
665
+
#define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
666
+
#define RT5670_G_DAC_L2_OM_R_SFT 13
667
+
#define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
668
+
#define RT5670_G_DAC_R2_OM_R_SFT 10
669
+
#define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7)
670
+
#define RT5670_G_DAC_R1_OM_R_SFT 7
671
+
672
+
/* Output Right Mixer Control 3 (0x52) */
673
+
#define RT5670_M_BST2_OM_R (0x1 << 6)
674
+
#define RT5670_M_BST2_OM_R_SFT 6
675
+
#define RT5670_M_IN_R_OM_R (0x1 << 4)
676
+
#define RT5670_M_IN_R_OM_R_SFT 4
677
+
#define RT5670_M_DAC_R2_OM_R (0x1 << 1)
678
+
#define RT5670_M_DAC_R2_OM_R_SFT 1
679
+
#define RT5670_M_DAC_R1_OM_R (0x1)
680
+
#define RT5670_M_DAC_R1_OM_R_SFT 0
681
+
682
+
/* LOUT Mixer Control (0x53) */
683
+
#define RT5670_M_DAC_L1_LM (0x1 << 15)
684
+
#define RT5670_M_DAC_L1_LM_SFT 15
685
+
#define RT5670_M_DAC_R1_LM (0x1 << 14)
686
+
#define RT5670_M_DAC_R1_LM_SFT 14
687
+
#define RT5670_M_OV_L_LM (0x1 << 13)
688
+
#define RT5670_M_OV_L_LM_SFT 13
689
+
#define RT5670_M_OV_R_LM (0x1 << 12)
690
+
#define RT5670_M_OV_R_LM_SFT 12
691
+
#define RT5670_G_LOUTMIX_MASK (0x1 << 11)
692
+
#define RT5670_G_LOUTMIX_SFT 11
693
+
694
+
/* Power Management for Digital 1 (0x61) */
695
+
#define RT5670_PWR_I2S1 (0x1 << 15)
696
+
#define RT5670_PWR_I2S1_BIT 15
697
+
#define RT5670_PWR_I2S2 (0x1 << 14)
698
+
#define RT5670_PWR_I2S2_BIT 14
699
+
#define RT5670_PWR_DAC_L1 (0x1 << 12)
700
+
#define RT5670_PWR_DAC_L1_BIT 12
701
+
#define RT5670_PWR_DAC_R1 (0x1 << 11)
702
+
#define RT5670_PWR_DAC_R1_BIT 11
703
+
#define RT5670_PWR_DAC_L2 (0x1 << 7)
704
+
#define RT5670_PWR_DAC_L2_BIT 7
705
+
#define RT5670_PWR_DAC_R2 (0x1 << 6)
706
+
#define RT5670_PWR_DAC_R2_BIT 6
707
+
#define RT5670_PWR_ADC_L (0x1 << 2)
708
+
#define RT5670_PWR_ADC_L_BIT 2
709
+
#define RT5670_PWR_ADC_R (0x1 << 1)
710
+
#define RT5670_PWR_ADC_R_BIT 1
711
+
#define RT5670_PWR_CLS_D (0x1)
712
+
#define RT5670_PWR_CLS_D_BIT 0
713
+
714
+
/* Power Management for Digital 2 (0x62) */
715
+
#define RT5670_PWR_ADC_S1F (0x1 << 15)
716
+
#define RT5670_PWR_ADC_S1F_BIT 15
717
+
#define RT5670_PWR_ADC_MF_L (0x1 << 14)
718
+
#define RT5670_PWR_ADC_MF_L_BIT 14
719
+
#define RT5670_PWR_ADC_MF_R (0x1 << 13)
720
+
#define RT5670_PWR_ADC_MF_R_BIT 13
721
+
#define RT5670_PWR_I2S_DSP (0x1 << 12)
722
+
#define RT5670_PWR_I2S_DSP_BIT 12
723
+
#define RT5670_PWR_DAC_S1F (0x1 << 11)
724
+
#define RT5670_PWR_DAC_S1F_BIT 11
725
+
#define RT5670_PWR_DAC_MF_L (0x1 << 10)
726
+
#define RT5670_PWR_DAC_MF_L_BIT 10
727
+
#define RT5670_PWR_DAC_MF_R (0x1 << 9)
728
+
#define RT5670_PWR_DAC_MF_R_BIT 9
729
+
#define RT5670_PWR_ADC_S2F (0x1 << 8)
730
+
#define RT5670_PWR_ADC_S2F_BIT 8
731
+
#define RT5670_PWR_PDM1 (0x1 << 7)
732
+
#define RT5670_PWR_PDM1_BIT 7
733
+
#define RT5670_PWR_PDM2 (0x1 << 6)
734
+
#define RT5670_PWR_PDM2_BIT 6
735
+
736
+
/* Power Management for Analog 1 (0x63) */
737
+
#define RT5670_PWR_VREF1 (0x1 << 15)
738
+
#define RT5670_PWR_VREF1_BIT 15
739
+
#define RT5670_PWR_FV1 (0x1 << 14)
740
+
#define RT5670_PWR_FV1_BIT 14
741
+
#define RT5670_PWR_MB (0x1 << 13)
742
+
#define RT5670_PWR_MB_BIT 13
743
+
#define RT5670_PWR_LM (0x1 << 12)
744
+
#define RT5670_PWR_LM_BIT 12
745
+
#define RT5670_PWR_BG (0x1 << 11)
746
+
#define RT5670_PWR_BG_BIT 11
747
+
#define RT5670_PWR_HP_L (0x1 << 7)
748
+
#define RT5670_PWR_HP_L_BIT 7
749
+
#define RT5670_PWR_HP_R (0x1 << 6)
750
+
#define RT5670_PWR_HP_R_BIT 6
751
+
#define RT5670_PWR_HA (0x1 << 5)
752
+
#define RT5670_PWR_HA_BIT 5
753
+
#define RT5670_PWR_VREF2 (0x1 << 4)
754
+
#define RT5670_PWR_VREF2_BIT 4
755
+
#define RT5670_PWR_FV2 (0x1 << 3)
756
+
#define RT5670_PWR_FV2_BIT 3
757
+
#define RT5670_LDO_SEL_MASK (0x3)
758
+
#define RT5670_LDO_SEL_SFT 0
759
+
760
+
/* Power Management for Analog 2 (0x64) */
761
+
#define RT5670_PWR_BST1 (0x1 << 15)
762
+
#define RT5670_PWR_BST1_BIT 15
763
+
#define RT5670_PWR_BST2 (0x1 << 13)
764
+
#define RT5670_PWR_BST2_BIT 13
765
+
#define RT5670_PWR_MB1 (0x1 << 11)
766
+
#define RT5670_PWR_MB1_BIT 11
767
+
#define RT5670_PWR_MB2 (0x1 << 10)
768
+
#define RT5670_PWR_MB2_BIT 10
769
+
#define RT5670_PWR_PLL (0x1 << 9)
770
+
#define RT5670_PWR_PLL_BIT 9
771
+
#define RT5670_PWR_BST1_P (0x1 << 6)
772
+
#define RT5670_PWR_BST1_P_BIT 6
773
+
#define RT5670_PWR_BST2_P (0x1 << 4)
774
+
#define RT5670_PWR_BST2_P_BIT 4
775
+
#define RT5670_PWR_JD1 (0x1 << 2)
776
+
#define RT5670_PWR_JD1_BIT 2
777
+
#define RT5670_PWR_JD (0x1 << 1)
778
+
#define RT5670_PWR_JD_BIT 1
779
+
780
+
/* Power Management for Mixer (0x65) */
781
+
#define RT5670_PWR_OM_L (0x1 << 15)
782
+
#define RT5670_PWR_OM_L_BIT 15
783
+
#define RT5670_PWR_OM_R (0x1 << 14)
784
+
#define RT5670_PWR_OM_R_BIT 14
785
+
#define RT5670_PWR_RM_L (0x1 << 11)
786
+
#define RT5670_PWR_RM_L_BIT 11
787
+
#define RT5670_PWR_RM_R (0x1 << 10)
788
+
#define RT5670_PWR_RM_R_BIT 10
789
+
790
+
/* Power Management for Volume (0x66) */
791
+
#define RT5670_PWR_HV_L (0x1 << 11)
792
+
#define RT5670_PWR_HV_L_BIT 11
793
+
#define RT5670_PWR_HV_R (0x1 << 10)
794
+
#define RT5670_PWR_HV_R_BIT 10
795
+
#define RT5670_PWR_IN_L (0x1 << 9)
796
+
#define RT5670_PWR_IN_L_BIT 9
797
+
#define RT5670_PWR_IN_R (0x1 << 8)
798
+
#define RT5670_PWR_IN_R_BIT 8
799
+
#define RT5670_PWR_MIC_DET (0x1 << 5)
800
+
#define RT5670_PWR_MIC_DET_BIT 5
801
+
802
+
/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
803
+
#define RT5670_I2S_MS_MASK (0x1 << 15)
804
+
#define RT5670_I2S_MS_SFT 15
805
+
#define RT5670_I2S_MS_M (0x0 << 15)
806
+
#define RT5670_I2S_MS_S (0x1 << 15)
807
+
#define RT5670_I2S_IF_MASK (0x7 << 12)
808
+
#define RT5670_I2S_IF_SFT 12
809
+
#define RT5670_I2S_O_CP_MASK (0x3 << 10)
810
+
#define RT5670_I2S_O_CP_SFT 10
811
+
#define RT5670_I2S_O_CP_OFF (0x0 << 10)
812
+
#define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
813
+
#define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
814
+
#define RT5670_I2S_I_CP_MASK (0x3 << 8)
815
+
#define RT5670_I2S_I_CP_SFT 8
816
+
#define RT5670_I2S_I_CP_OFF (0x0 << 8)
817
+
#define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
818
+
#define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
819
+
#define RT5670_I2S_BP_MASK (0x1 << 7)
820
+
#define RT5670_I2S_BP_SFT 7
821
+
#define RT5670_I2S_BP_NOR (0x0 << 7)
822
+
#define RT5670_I2S_BP_INV (0x1 << 7)
823
+
#define RT5670_I2S_DL_MASK (0x3 << 2)
824
+
#define RT5670_I2S_DL_SFT 2
825
+
#define RT5670_I2S_DL_16 (0x0 << 2)
826
+
#define RT5670_I2S_DL_20 (0x1 << 2)
827
+
#define RT5670_I2S_DL_24 (0x2 << 2)
828
+
#define RT5670_I2S_DL_8 (0x3 << 2)
829
+
#define RT5670_I2S_DF_MASK (0x3)
830
+
#define RT5670_I2S_DF_SFT 0
831
+
#define RT5670_I2S_DF_I2S (0x0)
832
+
#define RT5670_I2S_DF_LEFT (0x1)
833
+
#define RT5670_I2S_DF_PCM_A (0x2)
834
+
#define RT5670_I2S_DF_PCM_B (0x3)
835
+
836
+
/* I2S2 Audio Serial Data Port Control (0x71) */
837
+
#define RT5670_I2S2_SDI_MASK (0x1 << 6)
838
+
#define RT5670_I2S2_SDI_SFT 6
839
+
#define RT5670_I2S2_SDI_I2S1 (0x0 << 6)
840
+
#define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
841
+
842
+
/* ADC/DAC Clock Control 1 (0x73) */
843
+
#define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
844
+
#define RT5670_I2S_BCLK_MS1_SFT 15
845
+
#define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
846
+
#define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
847
+
#define RT5670_I2S_PD1_MASK (0x7 << 12)
848
+
#define RT5670_I2S_PD1_SFT 12
849
+
#define RT5670_I2S_PD1_1 (0x0 << 12)
850
+
#define RT5670_I2S_PD1_2 (0x1 << 12)
851
+
#define RT5670_I2S_PD1_3 (0x2 << 12)
852
+
#define RT5670_I2S_PD1_4 (0x3 << 12)
853
+
#define RT5670_I2S_PD1_6 (0x4 << 12)
854
+
#define RT5670_I2S_PD1_8 (0x5 << 12)
855
+
#define RT5670_I2S_PD1_12 (0x6 << 12)
856
+
#define RT5670_I2S_PD1_16 (0x7 << 12)
857
+
#define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
858
+
#define RT5670_I2S_BCLK_MS2_SFT 11
859
+
#define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
860
+
#define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
861
+
#define RT5670_I2S_PD2_MASK (0x7 << 8)
862
+
#define RT5670_I2S_PD2_SFT 8
863
+
#define RT5670_I2S_PD2_1 (0x0 << 8)
864
+
#define RT5670_I2S_PD2_2 (0x1 << 8)
865
+
#define RT5670_I2S_PD2_3 (0x2 << 8)
866
+
#define RT5670_I2S_PD2_4 (0x3 << 8)
867
+
#define RT5670_I2S_PD2_6 (0x4 << 8)
868
+
#define RT5670_I2S_PD2_8 (0x5 << 8)
869
+
#define RT5670_I2S_PD2_12 (0x6 << 8)
870
+
#define RT5670_I2S_PD2_16 (0x7 << 8)
871
+
#define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
872
+
#define RT5670_I2S_BCLK_MS3_SFT 7
873
+
#define RT5670_I2S_BCLK_MS3_32 (0x0 << 7)
874
+
#define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
875
+
#define RT5670_I2S_PD3_MASK (0x7 << 4)
876
+
#define RT5670_I2S_PD3_SFT 4
877
+
#define RT5670_I2S_PD3_1 (0x0 << 4)
878
+
#define RT5670_I2S_PD3_2 (0x1 << 4)
879
+
#define RT5670_I2S_PD3_3 (0x2 << 4)
880
+
#define RT5670_I2S_PD3_4 (0x3 << 4)
881
+
#define RT5670_I2S_PD3_6 (0x4 << 4)
882
+
#define RT5670_I2S_PD3_8 (0x5 << 4)
883
+
#define RT5670_I2S_PD3_12 (0x6 << 4)
884
+
#define RT5670_I2S_PD3_16 (0x7 << 4)
885
+
#define RT5670_DAC_OSR_MASK (0x3 << 2)
886
+
#define RT5670_DAC_OSR_SFT 2
887
+
#define RT5670_DAC_OSR_128 (0x0 << 2)
888
+
#define RT5670_DAC_OSR_64 (0x1 << 2)
889
+
#define RT5670_DAC_OSR_32 (0x2 << 2)
890
+
#define RT5670_DAC_OSR_16 (0x3 << 2)
891
+
#define RT5670_ADC_OSR_MASK (0x3)
892
+
#define RT5670_ADC_OSR_SFT 0
893
+
#define RT5670_ADC_OSR_128 (0x0)
894
+
#define RT5670_ADC_OSR_64 (0x1)
895
+
#define RT5670_ADC_OSR_32 (0x2)
896
+
#define RT5670_ADC_OSR_16 (0x3)
897
+
898
+
/* ADC/DAC Clock Control 2 (0x74) */
899
+
#define RT5670_DAC_L_OSR_MASK (0x3 << 14)
900
+
#define RT5670_DAC_L_OSR_SFT 14
901
+
#define RT5670_DAC_L_OSR_128 (0x0 << 14)
902
+
#define RT5670_DAC_L_OSR_64 (0x1 << 14)
903
+
#define RT5670_DAC_L_OSR_32 (0x2 << 14)
904
+
#define RT5670_DAC_L_OSR_16 (0x3 << 14)
905
+
#define RT5670_ADC_R_OSR_MASK (0x3 << 12)
906
+
#define RT5670_ADC_R_OSR_SFT 12
907
+
#define RT5670_ADC_R_OSR_128 (0x0 << 12)
908
+
#define RT5670_ADC_R_OSR_64 (0x1 << 12)
909
+
#define RT5670_ADC_R_OSR_32 (0x2 << 12)
910
+
#define RT5670_ADC_R_OSR_16 (0x3 << 12)
911
+
#define RT5670_DAHPF_EN (0x1 << 11)
912
+
#define RT5670_DAHPF_EN_SFT 11
913
+
#define RT5670_ADHPF_EN (0x1 << 10)
914
+
#define RT5670_ADHPF_EN_SFT 10
915
+
916
+
/* Digital Microphone Control (0x75) */
917
+
#define RT5670_DMIC_1_EN_MASK (0x1 << 15)
918
+
#define RT5670_DMIC_1_EN_SFT 15
919
+
#define RT5670_DMIC_1_DIS (0x0 << 15)
920
+
#define RT5670_DMIC_1_EN (0x1 << 15)
921
+
#define RT5670_DMIC_2_EN_MASK (0x1 << 14)
922
+
#define RT5670_DMIC_2_EN_SFT 14
923
+
#define RT5670_DMIC_2_DIS (0x0 << 14)
924
+
#define RT5670_DMIC_2_EN (0x1 << 14)
925
+
#define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
926
+
#define RT5670_DMIC_1L_LH_SFT 13
927
+
#define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
928
+
#define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
929
+
#define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
930
+
#define RT5670_DMIC_1R_LH_SFT 12
931
+
#define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
932
+
#define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
933
+
#define RT5670_DMIC_2_DP_MASK (0x1 << 10)
934
+
#define RT5670_DMIC_2_DP_SFT 10
935
+
#define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
936
+
#define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
937
+
#define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
938
+
#define RT5670_DMIC_2L_LH_SFT 9
939
+
#define RT5670_DMIC_2L_LH_FALLING (0x0 << 9)
940
+
#define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
941
+
#define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
942
+
#define RT5670_DMIC_2R_LH_SFT 8
943
+
#define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
944
+
#define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
945
+
#define RT5670_DMIC_CLK_MASK (0x7 << 5)
946
+
#define RT5670_DMIC_CLK_SFT 5
947
+
#define RT5670_DMIC_3_EN_MASK (0x1 << 4)
948
+
#define RT5670_DMIC_3_EN_SFT 4
949
+
#define RT5670_DMIC_3_DIS (0x0 << 4)
950
+
#define RT5670_DMIC_3_EN (0x1 << 4)
951
+
#define RT5670_DMIC_1_DP_MASK (0x3 << 0)
952
+
#define RT5670_DMIC_1_DP_SFT 0
953
+
#define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0)
954
+
#define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
955
+
#define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0)
956
+
957
+
/* Digital Microphone Control2 (0x76) */
958
+
#define RT5670_DMIC_3_DP_MASK (0x3 << 6)
959
+
#define RT5670_DMIC_3_DP_SFT 6
960
+
#define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6)
961
+
#define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
962
+
#define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6)
963
+
964
+
/* Global Clock Control (0x80) */
965
+
#define RT5670_SCLK_SRC_MASK (0x3 << 14)
966
+
#define RT5670_SCLK_SRC_SFT 14
967
+
#define RT5670_SCLK_SRC_MCLK (0x0 << 14)
968
+
#define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
969
+
#define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
970
+
#define RT5670_PLL1_SRC_MASK (0x3 << 12)
971
+
#define RT5670_PLL1_SRC_SFT 12
972
+
#define RT5670_PLL1_SRC_MCLK (0x0 << 12)
973
+
#define RT5670_PLL1_SRC_BCLK1 (0x1 << 12)
974
+
#define RT5670_PLL1_SRC_BCLK2 (0x2 << 12)
975
+
#define RT5670_PLL1_SRC_BCLK3 (0x3 << 12)
976
+
#define RT5670_PLL1_PD_MASK (0x1 << 3)
977
+
#define RT5670_PLL1_PD_SFT 3
978
+
#define RT5670_PLL1_PD_1 (0x0 << 3)
979
+
#define RT5670_PLL1_PD_2 (0x1 << 3)
980
+
981
+
#define RT5670_PLL_INP_MAX 40000000
982
+
#define RT5670_PLL_INP_MIN 256000
983
+
/* PLL M/N/K Code Control 1 (0x81) */
984
+
#define RT5670_PLL_N_MAX 0x1ff
985
+
#define RT5670_PLL_N_MASK (RT5670_PLL_N_MAX << 7)
986
+
#define RT5670_PLL_N_SFT 7
987
+
#define RT5670_PLL_K_MAX 0x1f
988
+
#define RT5670_PLL_K_MASK (RT5670_PLL_K_MAX)
989
+
#define RT5670_PLL_K_SFT 0
990
+
991
+
/* PLL M/N/K Code Control 2 (0x82) */
992
+
#define RT5670_PLL_M_MAX 0xf
993
+
#define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12)
994
+
#define RT5670_PLL_M_SFT 12
995
+
#define RT5670_PLL_M_BP (0x1 << 11)
996
+
#define RT5670_PLL_M_BP_SFT 11
997
+
998
+
/* ASRC Control 1 (0x83) */
999
+
#define RT5670_STO_T_MASK (0x1 << 15)
1000
+
#define RT5670_STO_T_SFT 15
1001
+
#define RT5670_STO_T_SCLK (0x0 << 15)
1002
+
#define RT5670_STO_T_LRCK1 (0x1 << 15)
1003
+
#define RT5670_M1_T_MASK (0x1 << 14)
1004
+
#define RT5670_M1_T_SFT 14
1005
+
#define RT5670_M1_T_I2S2 (0x0 << 14)
1006
+
#define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1007
+
#define RT5670_I2S2_F_MASK (0x1 << 12)
1008
+
#define RT5670_I2S2_F_SFT 12
1009
+
#define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
1010
+
#define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1011
+
#define RT5670_DMIC_1_M_MASK (0x1 << 9)
1012
+
#define RT5670_DMIC_1_M_SFT 9
1013
+
#define RT5670_DMIC_1_M_NOR (0x0 << 9)
1014
+
#define RT5670_DMIC_1_M_ASYN (0x1 << 9)
1015
+
#define RT5670_DMIC_2_M_MASK (0x1 << 8)
1016
+
#define RT5670_DMIC_2_M_SFT 8
1017
+
#define RT5670_DMIC_2_M_NOR (0x0 << 8)
1018
+
#define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1019
+
1020
+
/* ASRC Control 2 (0x84) */
1021
+
#define RT5670_MDA_L_M_MASK (0x1 << 15)
1022
+
#define RT5670_MDA_L_M_SFT 15
1023
+
#define RT5670_MDA_L_M_NOR (0x0 << 15)
1024
+
#define RT5670_MDA_L_M_ASYN (0x1 << 15)
1025
+
#define RT5670_MDA_R_M_MASK (0x1 << 14)
1026
+
#define RT5670_MDA_R_M_SFT 14
1027
+
#define RT5670_MDA_R_M_NOR (0x0 << 14)
1028
+
#define RT5670_MDA_R_M_ASYN (0x1 << 14)
1029
+
#define RT5670_MAD_L_M_MASK (0x1 << 13)
1030
+
#define RT5670_MAD_L_M_SFT 13
1031
+
#define RT5670_MAD_L_M_NOR (0x0 << 13)
1032
+
#define RT5670_MAD_L_M_ASYN (0x1 << 13)
1033
+
#define RT5670_MAD_R_M_MASK (0x1 << 12)
1034
+
#define RT5670_MAD_R_M_SFT 12
1035
+
#define RT5670_MAD_R_M_NOR (0x0 << 12)
1036
+
#define RT5670_MAD_R_M_ASYN (0x1 << 12)
1037
+
#define RT5670_ADC_M_MASK (0x1 << 11)
1038
+
#define RT5670_ADC_M_SFT 11
1039
+
#define RT5670_ADC_M_NOR (0x0 << 11)
1040
+
#define RT5670_ADC_M_ASYN (0x1 << 11)
1041
+
#define RT5670_STO_DAC_M_MASK (0x1 << 5)
1042
+
#define RT5670_STO_DAC_M_SFT 5
1043
+
#define RT5670_STO_DAC_M_NOR (0x0 << 5)
1044
+
#define RT5670_STO_DAC_M_ASYN (0x1 << 5)
1045
+
#define RT5670_I2S1_R_D_MASK (0x1 << 4)
1046
+
#define RT5670_I2S1_R_D_SFT 4
1047
+
#define RT5670_I2S1_R_D_DIS (0x0 << 4)
1048
+
#define RT5670_I2S1_R_D_EN (0x1 << 4)
1049
+
#define RT5670_I2S2_R_D_MASK (0x1 << 3)
1050
+
#define RT5670_I2S2_R_D_SFT 3
1051
+
#define RT5670_I2S2_R_D_DIS (0x0 << 3)
1052
+
#define RT5670_I2S2_R_D_EN (0x1 << 3)
1053
+
#define RT5670_PRE_SCLK_MASK (0x3)
1054
+
#define RT5670_PRE_SCLK_SFT 0
1055
+
#define RT5670_PRE_SCLK_512 (0x0)
1056
+
#define RT5670_PRE_SCLK_1024 (0x1)
1057
+
#define RT5670_PRE_SCLK_2048 (0x2)
1058
+
1059
+
/* ASRC Control 3 (0x85) */
1060
+
#define RT5670_I2S1_RATE_MASK (0xf << 12)
1061
+
#define RT5670_I2S1_RATE_SFT 12
1062
+
#define RT5670_I2S2_RATE_MASK (0xf << 8)
1063
+
#define RT5670_I2S2_RATE_SFT 8
1064
+
1065
+
/* ASRC Control 4 (0x89) */
1066
+
#define RT5670_I2S1_PD_MASK (0x7 << 12)
1067
+
#define RT5670_I2S1_PD_SFT 12
1068
+
#define RT5670_I2S2_PD_MASK (0x7 << 8)
1069
+
#define RT5670_I2S2_PD_SFT 8
1070
+
1071
+
/* HPOUT Over Current Detection (0x8b) */
1072
+
#define RT5670_HP_OVCD_MASK (0x1 << 10)
1073
+
#define RT5670_HP_OVCD_SFT 10
1074
+
#define RT5670_HP_OVCD_DIS (0x0 << 10)
1075
+
#define RT5670_HP_OVCD_EN (0x1 << 10)
1076
+
#define RT5670_HP_OC_TH_MASK (0x3 << 8)
1077
+
#define RT5670_HP_OC_TH_SFT 8
1078
+
#define RT5670_HP_OC_TH_90 (0x0 << 8)
1079
+
#define RT5670_HP_OC_TH_105 (0x1 << 8)
1080
+
#define RT5670_HP_OC_TH_120 (0x2 << 8)
1081
+
#define RT5670_HP_OC_TH_135 (0x3 << 8)
1082
+
1083
+
/* Class D Over Current Control (0x8c) */
1084
+
#define RT5670_CLSD_OC_MASK (0x1 << 9)
1085
+
#define RT5670_CLSD_OC_SFT 9
1086
+
#define RT5670_CLSD_OC_PU (0x0 << 9)
1087
+
#define RT5670_CLSD_OC_PD (0x1 << 9)
1088
+
#define RT5670_AUTO_PD_MASK (0x1 << 8)
1089
+
#define RT5670_AUTO_PD_SFT 8
1090
+
#define RT5670_AUTO_PD_DIS (0x0 << 8)
1091
+
#define RT5670_AUTO_PD_EN (0x1 << 8)
1092
+
#define RT5670_CLSD_OC_TH_MASK (0x3f)
1093
+
#define RT5670_CLSD_OC_TH_SFT 0
1094
+
1095
+
/* Class D Output Control (0x8d) */
1096
+
#define RT5670_CLSD_RATIO_MASK (0xf << 12)
1097
+
#define RT5670_CLSD_RATIO_SFT 12
1098
+
#define RT5670_CLSD_OM_MASK (0x1 << 11)
1099
+
#define RT5670_CLSD_OM_SFT 11
1100
+
#define RT5670_CLSD_OM_MONO (0x0 << 11)
1101
+
#define RT5670_CLSD_OM_STO (0x1 << 11)
1102
+
#define RT5670_CLSD_SCH_MASK (0x1 << 10)
1103
+
#define RT5670_CLSD_SCH_SFT 10
1104
+
#define RT5670_CLSD_SCH_L (0x0 << 10)
1105
+
#define RT5670_CLSD_SCH_S (0x1 << 10)
1106
+
1107
+
/* Depop Mode Control 1 (0x8e) */
1108
+
#define RT5670_SMT_TRIG_MASK (0x1 << 15)
1109
+
#define RT5670_SMT_TRIG_SFT 15
1110
+
#define RT5670_SMT_TRIG_DIS (0x0 << 15)
1111
+
#define RT5670_SMT_TRIG_EN (0x1 << 15)
1112
+
#define RT5670_HP_L_SMT_MASK (0x1 << 9)
1113
+
#define RT5670_HP_L_SMT_SFT 9
1114
+
#define RT5670_HP_L_SMT_DIS (0x0 << 9)
1115
+
#define RT5670_HP_L_SMT_EN (0x1 << 9)
1116
+
#define RT5670_HP_R_SMT_MASK (0x1 << 8)
1117
+
#define RT5670_HP_R_SMT_SFT 8
1118
+
#define RT5670_HP_R_SMT_DIS (0x0 << 8)
1119
+
#define RT5670_HP_R_SMT_EN (0x1 << 8)
1120
+
#define RT5670_HP_CD_PD_MASK (0x1 << 7)
1121
+
#define RT5670_HP_CD_PD_SFT 7
1122
+
#define RT5670_HP_CD_PD_DIS (0x0 << 7)
1123
+
#define RT5670_HP_CD_PD_EN (0x1 << 7)
1124
+
#define RT5670_RSTN_MASK (0x1 << 6)
1125
+
#define RT5670_RSTN_SFT 6
1126
+
#define RT5670_RSTN_DIS (0x0 << 6)
1127
+
#define RT5670_RSTN_EN (0x1 << 6)
1128
+
#define RT5670_RSTP_MASK (0x1 << 5)
1129
+
#define RT5670_RSTP_SFT 5
1130
+
#define RT5670_RSTP_DIS (0x0 << 5)
1131
+
#define RT5670_RSTP_EN (0x1 << 5)
1132
+
#define RT5670_HP_CO_MASK (0x1 << 4)
1133
+
#define RT5670_HP_CO_SFT 4
1134
+
#define RT5670_HP_CO_DIS (0x0 << 4)
1135
+
#define RT5670_HP_CO_EN (0x1 << 4)
1136
+
#define RT5670_HP_CP_MASK (0x1 << 3)
1137
+
#define RT5670_HP_CP_SFT 3
1138
+
#define RT5670_HP_CP_PD (0x0 << 3)
1139
+
#define RT5670_HP_CP_PU (0x1 << 3)
1140
+
#define RT5670_HP_SG_MASK (0x1 << 2)
1141
+
#define RT5670_HP_SG_SFT 2
1142
+
#define RT5670_HP_SG_DIS (0x0 << 2)
1143
+
#define RT5670_HP_SG_EN (0x1 << 2)
1144
+
#define RT5670_HP_DP_MASK (0x1 << 1)
1145
+
#define RT5670_HP_DP_SFT 1
1146
+
#define RT5670_HP_DP_PD (0x0 << 1)
1147
+
#define RT5670_HP_DP_PU (0x1 << 1)
1148
+
#define RT5670_HP_CB_MASK (0x1)
1149
+
#define RT5670_HP_CB_SFT 0
1150
+
#define RT5670_HP_CB_PD (0x0)
1151
+
#define RT5670_HP_CB_PU (0x1)
1152
+
1153
+
/* Depop Mode Control 2 (0x8f) */
1154
+
#define RT5670_DEPOP_MASK (0x1 << 13)
1155
+
#define RT5670_DEPOP_SFT 13
1156
+
#define RT5670_DEPOP_AUTO (0x0 << 13)
1157
+
#define RT5670_DEPOP_MAN (0x1 << 13)
1158
+
#define RT5670_RAMP_MASK (0x1 << 12)
1159
+
#define RT5670_RAMP_SFT 12
1160
+
#define RT5670_RAMP_DIS (0x0 << 12)
1161
+
#define RT5670_RAMP_EN (0x1 << 12)
1162
+
#define RT5670_BPS_MASK (0x1 << 11)
1163
+
#define RT5670_BPS_SFT 11
1164
+
#define RT5670_BPS_DIS (0x0 << 11)
1165
+
#define RT5670_BPS_EN (0x1 << 11)
1166
+
#define RT5670_FAST_UPDN_MASK (0x1 << 10)
1167
+
#define RT5670_FAST_UPDN_SFT 10
1168
+
#define RT5670_FAST_UPDN_DIS (0x0 << 10)
1169
+
#define RT5670_FAST_UPDN_EN (0x1 << 10)
1170
+
#define RT5670_MRES_MASK (0x3 << 8)
1171
+
#define RT5670_MRES_SFT 8
1172
+
#define RT5670_MRES_15MO (0x0 << 8)
1173
+
#define RT5670_MRES_25MO (0x1 << 8)
1174
+
#define RT5670_MRES_35MO (0x2 << 8)
1175
+
#define RT5670_MRES_45MO (0x3 << 8)
1176
+
#define RT5670_VLO_MASK (0x1 << 7)
1177
+
#define RT5670_VLO_SFT 7
1178
+
#define RT5670_VLO_3V (0x0 << 7)
1179
+
#define RT5670_VLO_32V (0x1 << 7)
1180
+
#define RT5670_DIG_DP_MASK (0x1 << 6)
1181
+
#define RT5670_DIG_DP_SFT 6
1182
+
#define RT5670_DIG_DP_DIS (0x0 << 6)
1183
+
#define RT5670_DIG_DP_EN (0x1 << 6)
1184
+
#define RT5670_DP_TH_MASK (0x3 << 4)
1185
+
#define RT5670_DP_TH_SFT 4
1186
+
1187
+
/* Depop Mode Control 3 (0x90) */
1188
+
#define RT5670_CP_SYS_MASK (0x7 << 12)
1189
+
#define RT5670_CP_SYS_SFT 12
1190
+
#define RT5670_CP_FQ1_MASK (0x7 << 8)
1191
+
#define RT5670_CP_FQ1_SFT 8
1192
+
#define RT5670_CP_FQ2_MASK (0x7 << 4)
1193
+
#define RT5670_CP_FQ2_SFT 4
1194
+
#define RT5670_CP_FQ3_MASK (0x7)
1195
+
#define RT5670_CP_FQ3_SFT 0
1196
+
#define RT5670_CP_FQ_1_5_KHZ 0
1197
+
#define RT5670_CP_FQ_3_KHZ 1
1198
+
#define RT5670_CP_FQ_6_KHZ 2
1199
+
#define RT5670_CP_FQ_12_KHZ 3
1200
+
#define RT5670_CP_FQ_24_KHZ 4
1201
+
#define RT5670_CP_FQ_48_KHZ 5
1202
+
#define RT5670_CP_FQ_96_KHZ 6
1203
+
#define RT5670_CP_FQ_192_KHZ 7
1204
+
1205
+
/* HPOUT charge pump (0x91) */
1206
+
#define RT5670_OSW_L_MASK (0x1 << 11)
1207
+
#define RT5670_OSW_L_SFT 11
1208
+
#define RT5670_OSW_L_DIS (0x0 << 11)
1209
+
#define RT5670_OSW_L_EN (0x1 << 11)
1210
+
#define RT5670_OSW_R_MASK (0x1 << 10)
1211
+
#define RT5670_OSW_R_SFT 10
1212
+
#define RT5670_OSW_R_DIS (0x0 << 10)
1213
+
#define RT5670_OSW_R_EN (0x1 << 10)
1214
+
#define RT5670_PM_HP_MASK (0x3 << 8)
1215
+
#define RT5670_PM_HP_SFT 8
1216
+
#define RT5670_PM_HP_LV (0x0 << 8)
1217
+
#define RT5670_PM_HP_MV (0x1 << 8)
1218
+
#define RT5670_PM_HP_HV (0x2 << 8)
1219
+
#define RT5670_IB_HP_MASK (0x3 << 6)
1220
+
#define RT5670_IB_HP_SFT 6
1221
+
#define RT5670_IB_HP_125IL (0x0 << 6)
1222
+
#define RT5670_IB_HP_25IL (0x1 << 6)
1223
+
#define RT5670_IB_HP_5IL (0x2 << 6)
1224
+
#define RT5670_IB_HP_1IL (0x3 << 6)
1225
+
1226
+
/* PV detection and SPK gain control (0x92) */
1227
+
#define RT5670_PVDD_DET_MASK (0x1 << 15)
1228
+
#define RT5670_PVDD_DET_SFT 15
1229
+
#define RT5670_PVDD_DET_DIS (0x0 << 15)
1230
+
#define RT5670_PVDD_DET_EN (0x1 << 15)
1231
+
#define RT5670_SPK_AG_MASK (0x1 << 14)
1232
+
#define RT5670_SPK_AG_SFT 14
1233
+
#define RT5670_SPK_AG_DIS (0x0 << 14)
1234
+
#define RT5670_SPK_AG_EN (0x1 << 14)
1235
+
1236
+
/* Micbias Control (0x93) */
1237
+
#define RT5670_MIC1_BS_MASK (0x1 << 15)
1238
+
#define RT5670_MIC1_BS_SFT 15
1239
+
#define RT5670_MIC1_BS_9AV (0x0 << 15)
1240
+
#define RT5670_MIC1_BS_75AV (0x1 << 15)
1241
+
#define RT5670_MIC2_BS_MASK (0x1 << 14)
1242
+
#define RT5670_MIC2_BS_SFT 14
1243
+
#define RT5670_MIC2_BS_9AV (0x0 << 14)
1244
+
#define RT5670_MIC2_BS_75AV (0x1 << 14)
1245
+
#define RT5670_MIC1_CLK_MASK (0x1 << 13)
1246
+
#define RT5670_MIC1_CLK_SFT 13
1247
+
#define RT5670_MIC1_CLK_DIS (0x0 << 13)
1248
+
#define RT5670_MIC1_CLK_EN (0x1 << 13)
1249
+
#define RT5670_MIC2_CLK_MASK (0x1 << 12)
1250
+
#define RT5670_MIC2_CLK_SFT 12
1251
+
#define RT5670_MIC2_CLK_DIS (0x0 << 12)
1252
+
#define RT5670_MIC2_CLK_EN (0x1 << 12)
1253
+
#define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1254
+
#define RT5670_MIC1_OVCD_SFT 11
1255
+
#define RT5670_MIC1_OVCD_DIS (0x0 << 11)
1256
+
#define RT5670_MIC1_OVCD_EN (0x1 << 11)
1257
+
#define RT5670_MIC1_OVTH_MASK (0x3 << 9)
1258
+
#define RT5670_MIC1_OVTH_SFT 9
1259
+
#define RT5670_MIC1_OVTH_600UA (0x0 << 9)
1260
+
#define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
1261
+
#define RT5670_MIC1_OVTH_2000UA (0x2 << 9)
1262
+
#define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1263
+
#define RT5670_MIC2_OVCD_SFT 8
1264
+
#define RT5670_MIC2_OVCD_DIS (0x0 << 8)
1265
+
#define RT5670_MIC2_OVCD_EN (0x1 << 8)
1266
+
#define RT5670_MIC2_OVTH_MASK (0x3 << 6)
1267
+
#define RT5670_MIC2_OVTH_SFT 6
1268
+
#define RT5670_MIC2_OVTH_600UA (0x0 << 6)
1269
+
#define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
1270
+
#define RT5670_MIC2_OVTH_2000UA (0x2 << 6)
1271
+
#define RT5670_PWR_MB_MASK (0x1 << 5)
1272
+
#define RT5670_PWR_MB_SFT 5
1273
+
#define RT5670_PWR_MB_PD (0x0 << 5)
1274
+
#define RT5670_PWR_MB_PU (0x1 << 5)
1275
+
#define RT5670_PWR_CLK25M_MASK (0x1 << 4)
1276
+
#define RT5670_PWR_CLK25M_SFT 4
1277
+
#define RT5670_PWR_CLK25M_PD (0x0 << 4)
1278
+
#define RT5670_PWR_CLK25M_PU (0x1 << 4)
1279
+
1280
+
/* Analog JD Control 1 (0x94) */
1281
+
#define RT5670_JD1_MODE_MASK (0x3 << 0)
1282
+
#define RT5670_JD1_MODE_0 (0x0 << 0)
1283
+
#define RT5670_JD1_MODE_1 (0x1 << 0)
1284
+
#define RT5670_JD1_MODE_2 (0x2 << 0)
1285
+
1286
+
/* VAD Control 4 (0x9d) */
1287
+
#define RT5670_VAD_SEL_MASK (0x3 << 8)
1288
+
#define RT5670_VAD_SEL_SFT 8
1289
+
1290
+
/* EQ Control 1 (0xb0) */
1291
+
#define RT5670_EQ_SRC_MASK (0x1 << 15)
1292
+
#define RT5670_EQ_SRC_SFT 15
1293
+
#define RT5670_EQ_SRC_DAC (0x0 << 15)
1294
+
#define RT5670_EQ_SRC_ADC (0x1 << 15)
1295
+
#define RT5670_EQ_UPD (0x1 << 14)
1296
+
#define RT5670_EQ_UPD_BIT 14
1297
+
#define RT5670_EQ_CD_MASK (0x1 << 13)
1298
+
#define RT5670_EQ_CD_SFT 13
1299
+
#define RT5670_EQ_CD_DIS (0x0 << 13)
1300
+
#define RT5670_EQ_CD_EN (0x1 << 13)
1301
+
#define RT5670_EQ_DITH_MASK (0x3 << 8)
1302
+
#define RT5670_EQ_DITH_SFT 8
1303
+
#define RT5670_EQ_DITH_NOR (0x0 << 8)
1304
+
#define RT5670_EQ_DITH_LSB (0x1 << 8)
1305
+
#define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
1306
+
#define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
1307
+
1308
+
/* EQ Control 2 (0xb1) */
1309
+
#define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1310
+
#define RT5670_EQ_HPF1_M_SFT 8
1311
+
#define RT5670_EQ_HPF1_M_HI (0x0 << 8)
1312
+
#define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1313
+
#define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
1314
+
#define RT5670_EQ_LPF1_M_SFT 7
1315
+
#define RT5670_EQ_LPF1_M_LO (0x0 << 7)
1316
+
#define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
1317
+
#define RT5670_EQ_HPF2_MASK (0x1 << 6)
1318
+
#define RT5670_EQ_HPF2_SFT 6
1319
+
#define RT5670_EQ_HPF2_DIS (0x0 << 6)
1320
+
#define RT5670_EQ_HPF2_EN (0x1 << 6)
1321
+
#define RT5670_EQ_HPF1_MASK (0x1 << 5)
1322
+
#define RT5670_EQ_HPF1_SFT 5
1323
+
#define RT5670_EQ_HPF1_DIS (0x0 << 5)
1324
+
#define RT5670_EQ_HPF1_EN (0x1 << 5)
1325
+
#define RT5670_EQ_BPF4_MASK (0x1 << 4)
1326
+
#define RT5670_EQ_BPF4_SFT 4
1327
+
#define RT5670_EQ_BPF4_DIS (0x0 << 4)
1328
+
#define RT5670_EQ_BPF4_EN (0x1 << 4)
1329
+
#define RT5670_EQ_BPF3_MASK (0x1 << 3)
1330
+
#define RT5670_EQ_BPF3_SFT 3
1331
+
#define RT5670_EQ_BPF3_DIS (0x0 << 3)
1332
+
#define RT5670_EQ_BPF3_EN (0x1 << 3)
1333
+
#define RT5670_EQ_BPF2_MASK (0x1 << 2)
1334
+
#define RT5670_EQ_BPF2_SFT 2
1335
+
#define RT5670_EQ_BPF2_DIS (0x0 << 2)
1336
+
#define RT5670_EQ_BPF2_EN (0x1 << 2)
1337
+
#define RT5670_EQ_BPF1_MASK (0x1 << 1)
1338
+
#define RT5670_EQ_BPF1_SFT 1
1339
+
#define RT5670_EQ_BPF1_DIS (0x0 << 1)
1340
+
#define RT5670_EQ_BPF1_EN (0x1 << 1)
1341
+
#define RT5670_EQ_LPF_MASK (0x1)
1342
+
#define RT5670_EQ_LPF_SFT 0
1343
+
#define RT5670_EQ_LPF_DIS (0x0)
1344
+
#define RT5670_EQ_LPF_EN (0x1)
1345
+
#define RT5670_EQ_CTRL_MASK (0x7f)
1346
+
1347
+
/* Memory Test (0xb2) */
1348
+
#define RT5670_MT_MASK (0x1 << 15)
1349
+
#define RT5670_MT_SFT 15
1350
+
#define RT5670_MT_DIS (0x0 << 15)
1351
+
#define RT5670_MT_EN (0x1 << 15)
1352
+
1353
+
/* DRC/AGC Control 1 (0xb4) */
1354
+
#define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1355
+
#define RT5670_DRC_AGC_P_SFT 15
1356
+
#define RT5670_DRC_AGC_P_DAC (0x0 << 15)
1357
+
#define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1358
+
#define RT5670_DRC_AGC_MASK (0x1 << 14)
1359
+
#define RT5670_DRC_AGC_SFT 14
1360
+
#define RT5670_DRC_AGC_DIS (0x0 << 14)
1361
+
#define RT5670_DRC_AGC_EN (0x1 << 14)
1362
+
#define RT5670_DRC_AGC_UPD (0x1 << 13)
1363
+
#define RT5670_DRC_AGC_UPD_BIT 13
1364
+
#define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
1365
+
#define RT5670_DRC_AGC_AR_SFT 8
1366
+
#define RT5670_DRC_AGC_R_MASK (0x7 << 5)
1367
+
#define RT5670_DRC_AGC_R_SFT 5
1368
+
#define RT5670_DRC_AGC_R_48K (0x1 << 5)
1369
+
#define RT5670_DRC_AGC_R_96K (0x2 << 5)
1370
+
#define RT5670_DRC_AGC_R_192K (0x3 << 5)
1371
+
#define RT5670_DRC_AGC_R_441K (0x5 << 5)
1372
+
#define RT5670_DRC_AGC_R_882K (0x6 << 5)
1373
+
#define RT5670_DRC_AGC_R_1764K (0x7 << 5)
1374
+
#define RT5670_DRC_AGC_RC_MASK (0x1f)
1375
+
#define RT5670_DRC_AGC_RC_SFT 0
1376
+
1377
+
/* DRC/AGC Control 2 (0xb5) */
1378
+
#define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
1379
+
#define RT5670_DRC_AGC_POB_SFT 8
1380
+
#define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
1381
+
#define RT5670_DRC_AGC_CP_SFT 7
1382
+
#define RT5670_DRC_AGC_CP_DIS (0x0 << 7)
1383
+
#define RT5670_DRC_AGC_CP_EN (0x1 << 7)
1384
+
#define RT5670_DRC_AGC_CPR_MASK (0x3 << 5)
1385
+
#define RT5670_DRC_AGC_CPR_SFT 5
1386
+
#define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5)
1387
+
#define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
1388
+
#define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5)
1389
+
#define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5)
1390
+
#define RT5670_DRC_AGC_PRB_MASK (0x1f)
1391
+
#define RT5670_DRC_AGC_PRB_SFT 0
1392
+
1393
+
/* DRC/AGC Control 3 (0xb6) */
1394
+
#define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
1395
+
#define RT5670_DRC_AGC_NGB_SFT 12
1396
+
#define RT5670_DRC_AGC_TAR_MASK (0x1f << 7)
1397
+
#define RT5670_DRC_AGC_TAR_SFT 7
1398
+
#define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
1399
+
#define RT5670_DRC_AGC_NG_SFT 6
1400
+
#define RT5670_DRC_AGC_NG_DIS (0x0 << 6)
1401
+
#define RT5670_DRC_AGC_NG_EN (0x1 << 6)
1402
+
#define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
1403
+
#define RT5670_DRC_AGC_NGH_SFT 5
1404
+
#define RT5670_DRC_AGC_NGH_DIS (0x0 << 5)
1405
+
#define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
1406
+
#define RT5670_DRC_AGC_NGT_MASK (0x1f)
1407
+
#define RT5670_DRC_AGC_NGT_SFT 0
1408
+
1409
+
/* Jack Detect Control (0xbb) */
1410
+
#define RT5670_JD_MASK (0x7 << 13)
1411
+
#define RT5670_JD_SFT 13
1412
+
#define RT5670_JD_DIS (0x0 << 13)
1413
+
#define RT5670_JD_GPIO1 (0x1 << 13)
1414
+
#define RT5670_JD_JD1_IN4P (0x2 << 13)
1415
+
#define RT5670_JD_JD2_IN4N (0x3 << 13)
1416
+
#define RT5670_JD_GPIO2 (0x4 << 13)
1417
+
#define RT5670_JD_GPIO3 (0x5 << 13)
1418
+
#define RT5670_JD_GPIO4 (0x6 << 13)
1419
+
#define RT5670_JD_HP_MASK (0x1 << 11)
1420
+
#define RT5670_JD_HP_SFT 11
1421
+
#define RT5670_JD_HP_DIS (0x0 << 11)
1422
+
#define RT5670_JD_HP_EN (0x1 << 11)
1423
+
#define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1424
+
#define RT5670_JD_HP_TRG_SFT 10
1425
+
#define RT5670_JD_HP_TRG_LO (0x0 << 10)
1426
+
#define RT5670_JD_HP_TRG_HI (0x1 << 10)
1427
+
#define RT5670_JD_SPL_MASK (0x1 << 9)
1428
+
#define RT5670_JD_SPL_SFT 9
1429
+
#define RT5670_JD_SPL_DIS (0x0 << 9)
1430
+
#define RT5670_JD_SPL_EN (0x1 << 9)
1431
+
#define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1432
+
#define RT5670_JD_SPL_TRG_SFT 8
1433
+
#define RT5670_JD_SPL_TRG_LO (0x0 << 8)
1434
+
#define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1435
+
#define RT5670_JD_SPR_MASK (0x1 << 7)
1436
+
#define RT5670_JD_SPR_SFT 7
1437
+
#define RT5670_JD_SPR_DIS (0x0 << 7)
1438
+
#define RT5670_JD_SPR_EN (0x1 << 7)
1439
+
#define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
1440
+
#define RT5670_JD_SPR_TRG_SFT 6
1441
+
#define RT5670_JD_SPR_TRG_LO (0x0 << 6)
1442
+
#define RT5670_JD_SPR_TRG_HI (0x1 << 6)
1443
+
#define RT5670_JD_MO_MASK (0x1 << 5)
1444
+
#define RT5670_JD_MO_SFT 5
1445
+
#define RT5670_JD_MO_DIS (0x0 << 5)
1446
+
#define RT5670_JD_MO_EN (0x1 << 5)
1447
+
#define RT5670_JD_MO_TRG_MASK (0x1 << 4)
1448
+
#define RT5670_JD_MO_TRG_SFT 4
1449
+
#define RT5670_JD_MO_TRG_LO (0x0 << 4)
1450
+
#define RT5670_JD_MO_TRG_HI (0x1 << 4)
1451
+
#define RT5670_JD_LO_MASK (0x1 << 3)
1452
+
#define RT5670_JD_LO_SFT 3
1453
+
#define RT5670_JD_LO_DIS (0x0 << 3)
1454
+
#define RT5670_JD_LO_EN (0x1 << 3)
1455
+
#define RT5670_JD_LO_TRG_MASK (0x1 << 2)
1456
+
#define RT5670_JD_LO_TRG_SFT 2
1457
+
#define RT5670_JD_LO_TRG_LO (0x0 << 2)
1458
+
#define RT5670_JD_LO_TRG_HI (0x1 << 2)
1459
+
#define RT5670_JD1_IN4P_MASK (0x1 << 1)
1460
+
#define RT5670_JD1_IN4P_SFT 1
1461
+
#define RT5670_JD1_IN4P_DIS (0x0 << 1)
1462
+
#define RT5670_JD1_IN4P_EN (0x1 << 1)
1463
+
#define RT5670_JD2_IN4N_MASK (0x1)
1464
+
#define RT5670_JD2_IN4N_SFT 0
1465
+
#define RT5670_JD2_IN4N_DIS (0x0)
1466
+
#define RT5670_JD2_IN4N_EN (0x1)
1467
+
1468
+
/* IRQ Control 1 (0xbd) */
1469
+
#define RT5670_IRQ_JD_MASK (0x1 << 15)
1470
+
#define RT5670_IRQ_JD_SFT 15
1471
+
#define RT5670_IRQ_JD_BP (0x0 << 15)
1472
+
#define RT5670_IRQ_JD_NOR (0x1 << 15)
1473
+
#define RT5670_IRQ_OT_MASK (0x1 << 14)
1474
+
#define RT5670_IRQ_OT_SFT 14
1475
+
#define RT5670_IRQ_OT_BP (0x0 << 14)
1476
+
#define RT5670_IRQ_OT_NOR (0x1 << 14)
1477
+
#define RT5670_JD_STKY_MASK (0x1 << 13)
1478
+
#define RT5670_JD_STKY_SFT 13
1479
+
#define RT5670_JD_STKY_DIS (0x0 << 13)
1480
+
#define RT5670_JD_STKY_EN (0x1 << 13)
1481
+
#define RT5670_OT_STKY_MASK (0x1 << 12)
1482
+
#define RT5670_OT_STKY_SFT 12
1483
+
#define RT5670_OT_STKY_DIS (0x0 << 12)
1484
+
#define RT5670_OT_STKY_EN (0x1 << 12)
1485
+
#define RT5670_JD_P_MASK (0x1 << 11)
1486
+
#define RT5670_JD_P_SFT 11
1487
+
#define RT5670_JD_P_NOR (0x0 << 11)
1488
+
#define RT5670_JD_P_INV (0x1 << 11)
1489
+
#define RT5670_OT_P_MASK (0x1 << 10)
1490
+
#define RT5670_OT_P_SFT 10
1491
+
#define RT5670_OT_P_NOR (0x0 << 10)
1492
+
#define RT5670_OT_P_INV (0x1 << 10)
1493
+
#define RT5670_JD1_1_EN_MASK (0x1 << 9)
1494
+
#define RT5670_JD1_1_EN_SFT 9
1495
+
#define RT5670_JD1_1_DIS (0x0 << 9)
1496
+
#define RT5670_JD1_1_EN (0x1 << 9)
1497
+
1498
+
/* IRQ Control 2 (0xbe) */
1499
+
#define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1500
+
#define RT5670_IRQ_MB1_OC_SFT 15
1501
+
#define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
1502
+
#define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1503
+
#define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1504
+
#define RT5670_IRQ_MB2_OC_SFT 14
1505
+
#define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
1506
+
#define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1507
+
#define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1508
+
#define RT5670_MB1_OC_STKY_SFT 11
1509
+
#define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
1510
+
#define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1511
+
#define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1512
+
#define RT5670_MB2_OC_STKY_SFT 10
1513
+
#define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
1514
+
#define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1515
+
#define RT5670_MB1_OC_P_MASK (0x1 << 7)
1516
+
#define RT5670_MB1_OC_P_SFT 7
1517
+
#define RT5670_MB1_OC_P_NOR (0x0 << 7)
1518
+
#define RT5670_MB1_OC_P_INV (0x1 << 7)
1519
+
#define RT5670_MB2_OC_P_MASK (0x1 << 6)
1520
+
#define RT5670_MB2_OC_P_SFT 6
1521
+
#define RT5670_MB2_OC_P_NOR (0x0 << 6)
1522
+
#define RT5670_MB2_OC_P_INV (0x1 << 6)
1523
+
#define RT5670_MB1_OC_CLR (0x1 << 3)
1524
+
#define RT5670_MB1_OC_CLR_SFT 3
1525
+
#define RT5670_MB2_OC_CLR (0x1 << 2)
1526
+
#define RT5670_MB2_OC_CLR_SFT 2
1527
+
1528
+
/* GPIO Control 1 (0xc0) */
1529
+
#define RT5670_GP1_PIN_MASK (0x1 << 15)
1530
+
#define RT5670_GP1_PIN_SFT 15
1531
+
#define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
1532
+
#define RT5670_GP1_PIN_IRQ (0x1 << 15)
1533
+
#define RT5670_GP2_PIN_MASK (0x1 << 14)
1534
+
#define RT5670_GP2_PIN_SFT 14
1535
+
#define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
1536
+
#define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1537
+
#define RT5670_GP3_PIN_MASK (0x3 << 12)
1538
+
#define RT5670_GP3_PIN_SFT 12
1539
+
#define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
1540
+
#define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1541
+
#define RT5670_GP3_PIN_IRQ (0x2 << 12)
1542
+
#define RT5670_GP4_PIN_MASK (0x1 << 11)
1543
+
#define RT5670_GP4_PIN_SFT 11
1544
+
#define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
1545
+
#define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1546
+
#define RT5670_DP_SIG_MASK (0x1 << 10)
1547
+
#define RT5670_DP_SIG_SFT 10
1548
+
#define RT5670_DP_SIG_TEST (0x0 << 10)
1549
+
#define RT5670_DP_SIG_AP (0x1 << 10)
1550
+
#define RT5670_GPIO_M_MASK (0x1 << 9)
1551
+
#define RT5670_GPIO_M_SFT 9
1552
+
#define RT5670_GPIO_M_FLT (0x0 << 9)
1553
+
#define RT5670_GPIO_M_PH (0x1 << 9)
1554
+
#define RT5670_I2S2_PIN_MASK (0x1 << 8)
1555
+
#define RT5670_I2S2_PIN_SFT 8
1556
+
#define RT5670_I2S2_PIN_I2S (0x0 << 8)
1557
+
#define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1558
+
#define RT5670_GP5_PIN_MASK (0x1 << 7)
1559
+
#define RT5670_GP5_PIN_SFT 7
1560
+
#define RT5670_GP5_PIN_GPIO5 (0x0 << 7)
1561
+
#define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
1562
+
#define RT5670_GP6_PIN_MASK (0x1 << 6)
1563
+
#define RT5670_GP6_PIN_SFT 6
1564
+
#define RT5670_GP6_PIN_GPIO6 (0x0 << 6)
1565
+
#define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
1566
+
#define RT5670_GP7_PIN_MASK (0x3 << 4)
1567
+
#define RT5670_GP7_PIN_SFT 4
1568
+
#define RT5670_GP7_PIN_GPIO7 (0x0 << 4)
1569
+
#define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
1570
+
#define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4)
1571
+
#define RT5670_GP8_PIN_MASK (0x1 << 3)
1572
+
#define RT5670_GP8_PIN_SFT 3
1573
+
#define RT5670_GP8_PIN_GPIO8 (0x0 << 3)
1574
+
#define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
1575
+
#define RT5670_GP9_PIN_MASK (0x1 << 2)
1576
+
#define RT5670_GP9_PIN_SFT 2
1577
+
#define RT5670_GP9_PIN_GPIO9 (0x0 << 2)
1578
+
#define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
1579
+
#define RT5670_GP10_PIN_MASK (0x3)
1580
+
#define RT5670_GP10_PIN_SFT 0
1581
+
#define RT5670_GP10_PIN_GPIO9 (0x0)
1582
+
#define RT5670_GP10_PIN_DMIC3_SDA (0x1)
1583
+
#define RT5670_GP10_PIN_PDM_ADT2 (0x2)
1584
+
1585
+
/* GPIO Control 2 (0xc1) */
1586
+
#define RT5670_GP4_PF_MASK (0x1 << 11)
1587
+
#define RT5670_GP4_PF_SFT 11
1588
+
#define RT5670_GP4_PF_IN (0x0 << 11)
1589
+
#define RT5670_GP4_PF_OUT (0x1 << 11)
1590
+
#define RT5670_GP4_OUT_MASK (0x1 << 10)
1591
+
#define RT5670_GP4_OUT_SFT 10
1592
+
#define RT5670_GP4_OUT_LO (0x0 << 10)
1593
+
#define RT5670_GP4_OUT_HI (0x1 << 10)
1594
+
#define RT5670_GP4_P_MASK (0x1 << 9)
1595
+
#define RT5670_GP4_P_SFT 9
1596
+
#define RT5670_GP4_P_NOR (0x0 << 9)
1597
+
#define RT5670_GP4_P_INV (0x1 << 9)
1598
+
#define RT5670_GP3_PF_MASK (0x1 << 8)
1599
+
#define RT5670_GP3_PF_SFT 8
1600
+
#define RT5670_GP3_PF_IN (0x0 << 8)
1601
+
#define RT5670_GP3_PF_OUT (0x1 << 8)
1602
+
#define RT5670_GP3_OUT_MASK (0x1 << 7)
1603
+
#define RT5670_GP3_OUT_SFT 7
1604
+
#define RT5670_GP3_OUT_LO (0x0 << 7)
1605
+
#define RT5670_GP3_OUT_HI (0x1 << 7)
1606
+
#define RT5670_GP3_P_MASK (0x1 << 6)
1607
+
#define RT5670_GP3_P_SFT 6
1608
+
#define RT5670_GP3_P_NOR (0x0 << 6)
1609
+
#define RT5670_GP3_P_INV (0x1 << 6)
1610
+
#define RT5670_GP2_PF_MASK (0x1 << 5)
1611
+
#define RT5670_GP2_PF_SFT 5
1612
+
#define RT5670_GP2_PF_IN (0x0 << 5)
1613
+
#define RT5670_GP2_PF_OUT (0x1 << 5)
1614
+
#define RT5670_GP2_OUT_MASK (0x1 << 4)
1615
+
#define RT5670_GP2_OUT_SFT 4
1616
+
#define RT5670_GP2_OUT_LO (0x0 << 4)
1617
+
#define RT5670_GP2_OUT_HI (0x1 << 4)
1618
+
#define RT5670_GP2_P_MASK (0x1 << 3)
1619
+
#define RT5670_GP2_P_SFT 3
1620
+
#define RT5670_GP2_P_NOR (0x0 << 3)
1621
+
#define RT5670_GP2_P_INV (0x1 << 3)
1622
+
#define RT5670_GP1_PF_MASK (0x1 << 2)
1623
+
#define RT5670_GP1_PF_SFT 2
1624
+
#define RT5670_GP1_PF_IN (0x0 << 2)
1625
+
#define RT5670_GP1_PF_OUT (0x1 << 2)
1626
+
#define RT5670_GP1_OUT_MASK (0x1 << 1)
1627
+
#define RT5670_GP1_OUT_SFT 1
1628
+
#define RT5670_GP1_OUT_LO (0x0 << 1)
1629
+
#define RT5670_GP1_OUT_HI (0x1 << 1)
1630
+
#define RT5670_GP1_P_MASK (0x1)
1631
+
#define RT5670_GP1_P_SFT 0
1632
+
#define RT5670_GP1_P_NOR (0x0)
1633
+
#define RT5670_GP1_P_INV (0x1)
1634
+
1635
+
/* Scramble Function (0xcd) */
1636
+
#define RT5670_SCB_KEY_MASK (0xff)
1637
+
#define RT5670_SCB_KEY_SFT 0
1638
+
1639
+
/* Scramble Control (0xce) */
1640
+
#define RT5670_SCB_SWAP_MASK (0x1 << 15)
1641
+
#define RT5670_SCB_SWAP_SFT 15
1642
+
#define RT5670_SCB_SWAP_DIS (0x0 << 15)
1643
+
#define RT5670_SCB_SWAP_EN (0x1 << 15)
1644
+
#define RT5670_SCB_MASK (0x1 << 14)
1645
+
#define RT5670_SCB_SFT 14
1646
+
#define RT5670_SCB_DIS (0x0 << 14)
1647
+
#define RT5670_SCB_EN (0x1 << 14)
1648
+
1649
+
/* Baseback Control (0xcf) */
1650
+
#define RT5670_BB_MASK (0x1 << 15)
1651
+
#define RT5670_BB_SFT 15
1652
+
#define RT5670_BB_DIS (0x0 << 15)
1653
+
#define RT5670_BB_EN (0x1 << 15)
1654
+
#define RT5670_BB_CT_MASK (0x7 << 12)
1655
+
#define RT5670_BB_CT_SFT 12
1656
+
#define RT5670_BB_CT_A (0x0 << 12)
1657
+
#define RT5670_BB_CT_B (0x1 << 12)
1658
+
#define RT5670_BB_CT_C (0x2 << 12)
1659
+
#define RT5670_BB_CT_D (0x3 << 12)
1660
+
#define RT5670_M_BB_L_MASK (0x1 << 9)
1661
+
#define RT5670_M_BB_L_SFT 9
1662
+
#define RT5670_M_BB_R_MASK (0x1 << 8)
1663
+
#define RT5670_M_BB_R_SFT 8
1664
+
#define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
1665
+
#define RT5670_M_BB_HPF_L_SFT 7
1666
+
#define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
1667
+
#define RT5670_M_BB_HPF_R_SFT 6
1668
+
#define RT5670_G_BB_BST_MASK (0x3f)
1669
+
#define RT5670_G_BB_BST_SFT 0
1670
+
1671
+
/* MP3 Plus Control 1 (0xd0) */
1672
+
#define RT5670_M_MP3_L_MASK (0x1 << 15)
1673
+
#define RT5670_M_MP3_L_SFT 15
1674
+
#define RT5670_M_MP3_R_MASK (0x1 << 14)
1675
+
#define RT5670_M_MP3_R_SFT 14
1676
+
#define RT5670_M_MP3_MASK (0x1 << 13)
1677
+
#define RT5670_M_MP3_SFT 13
1678
+
#define RT5670_M_MP3_DIS (0x0 << 13)
1679
+
#define RT5670_M_MP3_EN (0x1 << 13)
1680
+
#define RT5670_EG_MP3_MASK (0x1f << 8)
1681
+
#define RT5670_EG_MP3_SFT 8
1682
+
#define RT5670_MP3_HLP_MASK (0x1 << 7)
1683
+
#define RT5670_MP3_HLP_SFT 7
1684
+
#define RT5670_MP3_HLP_DIS (0x0 << 7)
1685
+
#define RT5670_MP3_HLP_EN (0x1 << 7)
1686
+
#define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
1687
+
#define RT5670_M_MP3_ORG_L_SFT 6
1688
+
#define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
1689
+
#define RT5670_M_MP3_ORG_R_SFT 5
1690
+
1691
+
/* MP3 Plus Control 2 (0xd1) */
1692
+
#define RT5670_MP3_WT_MASK (0x1 << 13)
1693
+
#define RT5670_MP3_WT_SFT 13
1694
+
#define RT5670_MP3_WT_1_4 (0x0 << 13)
1695
+
#define RT5670_MP3_WT_1_2 (0x1 << 13)
1696
+
#define RT5670_OG_MP3_MASK (0x1f << 8)
1697
+
#define RT5670_OG_MP3_SFT 8
1698
+
#define RT5670_HG_MP3_MASK (0x3f)
1699
+
#define RT5670_HG_MP3_SFT 0
1700
+
1701
+
/* 3D HP Control 1 (0xd2) */
1702
+
#define RT5670_3D_CF_MASK (0x1 << 15)
1703
+
#define RT5670_3D_CF_SFT 15
1704
+
#define RT5670_3D_CF_DIS (0x0 << 15)
1705
+
#define RT5670_3D_CF_EN (0x1 << 15)
1706
+
#define RT5670_3D_HP_MASK (0x1 << 14)
1707
+
#define RT5670_3D_HP_SFT 14
1708
+
#define RT5670_3D_HP_DIS (0x0 << 14)
1709
+
#define RT5670_3D_HP_EN (0x1 << 14)
1710
+
#define RT5670_3D_BT_MASK (0x1 << 13)
1711
+
#define RT5670_3D_BT_SFT 13
1712
+
#define RT5670_3D_BT_DIS (0x0 << 13)
1713
+
#define RT5670_3D_BT_EN (0x1 << 13)
1714
+
#define RT5670_3D_1F_MIX_MASK (0x3 << 11)
1715
+
#define RT5670_3D_1F_MIX_SFT 11
1716
+
#define RT5670_3D_HP_M_MASK (0x1 << 10)
1717
+
#define RT5670_3D_HP_M_SFT 10
1718
+
#define RT5670_3D_HP_M_SUR (0x0 << 10)
1719
+
#define RT5670_3D_HP_M_FRO (0x1 << 10)
1720
+
#define RT5670_M_3D_HRTF_MASK (0x1 << 9)
1721
+
#define RT5670_M_3D_HRTF_SFT 9
1722
+
#define RT5670_M_3D_D2H_MASK (0x1 << 8)
1723
+
#define RT5670_M_3D_D2H_SFT 8
1724
+
#define RT5670_M_3D_D2R_MASK (0x1 << 7)
1725
+
#define RT5670_M_3D_D2R_SFT 7
1726
+
#define RT5670_M_3D_REVB_MASK (0x1 << 6)
1727
+
#define RT5670_M_3D_REVB_SFT 6
1728
+
1729
+
/* Adjustable high pass filter control 1 (0xd3) */
1730
+
#define RT5670_2ND_HPF_MASK (0x1 << 15)
1731
+
#define RT5670_2ND_HPF_SFT 15
1732
+
#define RT5670_2ND_HPF_DIS (0x0 << 15)
1733
+
#define RT5670_2ND_HPF_EN (0x1 << 15)
1734
+
#define RT5670_HPF_CF_L_MASK (0x7 << 12)
1735
+
#define RT5670_HPF_CF_L_SFT 12
1736
+
#define RT5670_1ST_HPF_MASK (0x1 << 11)
1737
+
#define RT5670_1ST_HPF_SFT 11
1738
+
#define RT5670_1ST_HPF_DIS (0x0 << 11)
1739
+
#define RT5670_1ST_HPF_EN (0x1 << 11)
1740
+
#define RT5670_HPF_CF_R_MASK (0x7 << 8)
1741
+
#define RT5670_HPF_CF_R_SFT 8
1742
+
#define RT5670_ZD_T_MASK (0x3 << 6)
1743
+
#define RT5670_ZD_T_SFT 6
1744
+
#define RT5670_ZD_F_MASK (0x3 << 4)
1745
+
#define RT5670_ZD_F_SFT 4
1746
+
#define RT5670_ZD_F_IM (0x0 << 4)
1747
+
#define RT5670_ZD_F_ZC_IM (0x1 << 4)
1748
+
#define RT5670_ZD_F_ZC_IOD (0x2 << 4)
1749
+
#define RT5670_ZD_F_UN (0x3 << 4)
1750
+
1751
+
/* HP calibration control and Amp detection (0xd6) */
1752
+
#define RT5670_SI_DAC_MASK (0x1 << 11)
1753
+
#define RT5670_SI_DAC_SFT 11
1754
+
#define RT5670_SI_DAC_AUTO (0x0 << 11)
1755
+
#define RT5670_SI_DAC_TEST (0x1 << 11)
1756
+
#define RT5670_DC_CAL_M_MASK (0x1 << 10)
1757
+
#define RT5670_DC_CAL_M_SFT 10
1758
+
#define RT5670_DC_CAL_M_CAL (0x0 << 10)
1759
+
#define RT5670_DC_CAL_M_NOR (0x1 << 10)
1760
+
#define RT5670_DC_CAL_MASK (0x1 << 9)
1761
+
#define RT5670_DC_CAL_SFT 9
1762
+
#define RT5670_DC_CAL_DIS (0x0 << 9)
1763
+
#define RT5670_DC_CAL_EN (0x1 << 9)
1764
+
#define RT5670_HPD_RCV_MASK (0x7 << 6)
1765
+
#define RT5670_HPD_RCV_SFT 6
1766
+
#define RT5670_HPD_PS_MASK (0x1 << 5)
1767
+
#define RT5670_HPD_PS_SFT 5
1768
+
#define RT5670_HPD_PS_DIS (0x0 << 5)
1769
+
#define RT5670_HPD_PS_EN (0x1 << 5)
1770
+
#define RT5670_CAL_M_MASK (0x1 << 4)
1771
+
#define RT5670_CAL_M_SFT 4
1772
+
#define RT5670_CAL_M_DEP (0x0 << 4)
1773
+
#define RT5670_CAL_M_CAL (0x1 << 4)
1774
+
#define RT5670_CAL_MASK (0x1 << 3)
1775
+
#define RT5670_CAL_SFT 3
1776
+
#define RT5670_CAL_DIS (0x0 << 3)
1777
+
#define RT5670_CAL_EN (0x1 << 3)
1778
+
#define RT5670_CAL_TEST_MASK (0x1 << 2)
1779
+
#define RT5670_CAL_TEST_SFT 2
1780
+
#define RT5670_CAL_TEST_DIS (0x0 << 2)
1781
+
#define RT5670_CAL_TEST_EN (0x1 << 2)
1782
+
#define RT5670_CAL_P_MASK (0x3)
1783
+
#define RT5670_CAL_P_SFT 0
1784
+
#define RT5670_CAL_P_NONE (0x0)
1785
+
#define RT5670_CAL_P_CAL (0x1)
1786
+
#define RT5670_CAL_P_DAC_CAL (0x2)
1787
+
1788
+
/* Soft volume and zero cross control 1 (0xd9) */
1789
+
#define RT5670_SV_MASK (0x1 << 15)
1790
+
#define RT5670_SV_SFT 15
1791
+
#define RT5670_SV_DIS (0x0 << 15)
1792
+
#define RT5670_SV_EN (0x1 << 15)
1793
+
#define RT5670_SPO_SV_MASK (0x1 << 14)
1794
+
#define RT5670_SPO_SV_SFT 14
1795
+
#define RT5670_SPO_SV_DIS (0x0 << 14)
1796
+
#define RT5670_SPO_SV_EN (0x1 << 14)
1797
+
#define RT5670_OUT_SV_MASK (0x1 << 13)
1798
+
#define RT5670_OUT_SV_SFT 13
1799
+
#define RT5670_OUT_SV_DIS (0x0 << 13)
1800
+
#define RT5670_OUT_SV_EN (0x1 << 13)
1801
+
#define RT5670_HP_SV_MASK (0x1 << 12)
1802
+
#define RT5670_HP_SV_SFT 12
1803
+
#define RT5670_HP_SV_DIS (0x0 << 12)
1804
+
#define RT5670_HP_SV_EN (0x1 << 12)
1805
+
#define RT5670_ZCD_DIG_MASK (0x1 << 11)
1806
+
#define RT5670_ZCD_DIG_SFT 11
1807
+
#define RT5670_ZCD_DIG_DIS (0x0 << 11)
1808
+
#define RT5670_ZCD_DIG_EN (0x1 << 11)
1809
+
#define RT5670_ZCD_MASK (0x1 << 10)
1810
+
#define RT5670_ZCD_SFT 10
1811
+
#define RT5670_ZCD_PD (0x0 << 10)
1812
+
#define RT5670_ZCD_PU (0x1 << 10)
1813
+
#define RT5670_M_ZCD_MASK (0x3f << 4)
1814
+
#define RT5670_M_ZCD_SFT 4
1815
+
#define RT5670_M_ZCD_RM_L (0x1 << 9)
1816
+
#define RT5670_M_ZCD_RM_R (0x1 << 8)
1817
+
#define RT5670_M_ZCD_SM_L (0x1 << 7)
1818
+
#define RT5670_M_ZCD_SM_R (0x1 << 6)
1819
+
#define RT5670_M_ZCD_OM_L (0x1 << 5)
1820
+
#define RT5670_M_ZCD_OM_R (0x1 << 4)
1821
+
#define RT5670_SV_DLY_MASK (0xf)
1822
+
#define RT5670_SV_DLY_SFT 0
1823
+
1824
+
/* Soft volume and zero cross control 2 (0xda) */
1825
+
#define RT5670_ZCD_HP_MASK (0x1 << 15)
1826
+
#define RT5670_ZCD_HP_SFT 15
1827
+
#define RT5670_ZCD_HP_DIS (0x0 << 15)
1828
+
#define RT5670_ZCD_HP_EN (0x1 << 15)
1829
+
1830
+
1831
+
/* Codec Private Register definition */
1832
+
/* 3D Speaker Control (0x63) */
1833
+
#define RT5670_3D_SPK_MASK (0x1 << 15)
1834
+
#define RT5670_3D_SPK_SFT 15
1835
+
#define RT5670_3D_SPK_DIS (0x0 << 15)
1836
+
#define RT5670_3D_SPK_EN (0x1 << 15)
1837
+
#define RT5670_3D_SPK_M_MASK (0x3 << 13)
1838
+
#define RT5670_3D_SPK_M_SFT 13
1839
+
#define RT5670_3D_SPK_CG_MASK (0x1f << 8)
1840
+
#define RT5670_3D_SPK_CG_SFT 8
1841
+
#define RT5670_3D_SPK_SG_MASK (0x1f)
1842
+
#define RT5670_3D_SPK_SG_SFT 0
1843
+
1844
+
/* Wind Noise Detection Control 1 (0x6c) */
1845
+
#define RT5670_WND_MASK (0x1 << 15)
1846
+
#define RT5670_WND_SFT 15
1847
+
#define RT5670_WND_DIS (0x0 << 15)
1848
+
#define RT5670_WND_EN (0x1 << 15)
1849
+
1850
+
/* Wind Noise Detection Control 2 (0x6d) */
1851
+
#define RT5670_WND_FC_NW_MASK (0x3f << 10)
1852
+
#define RT5670_WND_FC_NW_SFT 10
1853
+
#define RT5670_WND_FC_WK_MASK (0x3f << 4)
1854
+
#define RT5670_WND_FC_WK_SFT 4
1855
+
1856
+
/* Wind Noise Detection Control 3 (0x6e) */
1857
+
#define RT5670_HPF_FC_MASK (0x3f << 6)
1858
+
#define RT5670_HPF_FC_SFT 6
1859
+
#define RT5670_WND_FC_ST_MASK (0x3f)
1860
+
#define RT5670_WND_FC_ST_SFT 0
1861
+
1862
+
/* Wind Noise Detection Control 4 (0x6f) */
1863
+
#define RT5670_WND_TH_LO_MASK (0x3ff)
1864
+
#define RT5670_WND_TH_LO_SFT 0
1865
+
1866
+
/* Wind Noise Detection Control 5 (0x70) */
1867
+
#define RT5670_WND_TH_HI_MASK (0x3ff)
1868
+
#define RT5670_WND_TH_HI_SFT 0
1869
+
1870
+
/* Wind Noise Detection Control 8 (0x73) */
1871
+
#define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1872
+
#define RT5670_WND_WIND_SFT 13
1873
+
#define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1874
+
#define RT5670_WND_STRONG_SFT 12
1875
+
enum {
1876
+
RT5670_NO_WIND,
1877
+
RT5670_BREEZE,
1878
+
RT5670_STORM,
1879
+
};
1880
+
1881
+
/* Dipole Speaker Interface (0x75) */
1882
+
#define RT5670_DP_ATT_MASK (0x3 << 14)
1883
+
#define RT5670_DP_ATT_SFT 14
1884
+
#define RT5670_DP_SPK_MASK (0x1 << 10)
1885
+
#define RT5670_DP_SPK_SFT 10
1886
+
#define RT5670_DP_SPK_DIS (0x0 << 10)
1887
+
#define RT5670_DP_SPK_EN (0x1 << 10)
1888
+
1889
+
/* EQ Pre Volume Control (0xb3) */
1890
+
#define RT5670_EQ_PRE_VOL_MASK (0xffff)
1891
+
#define RT5670_EQ_PRE_VOL_SFT 0
1892
+
1893
+
/* EQ Post Volume Control (0xb4) */
1894
+
#define RT5670_EQ_PST_VOL_MASK (0xffff)
1895
+
#define RT5670_EQ_PST_VOL_SFT 0
1896
+
1897
+
/* Jack Detect Control 3 (0xf8) */
1898
+
#define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
1899
+
#define RT5670_JD_CBJ_EN (0x1 << 7)
1900
+
#define RT5670_JD_CBJ_POL (0x1 << 6)
1901
+
#define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
1902
+
#define RT5670_JD_TRI_CBJ_SEL_SFT (3)
1903
+
#define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3)
1904
+
#define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
1905
+
#define RT5670_JD_CBJ_JD1_2 (0x2 << 3)
1906
+
#define RT5670_JD_CBJ_JD2 (0x3 << 3)
1907
+
#define RT5670_JD_CBJ_JD3 (0x4 << 3)
1908
+
#define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3)
1909
+
#define RT5670_JD_CBJ_MX0B_12 (0x6 << 3)
1910
+
#define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3)
1911
+
#define RT5670_JD_TRI_HPO_SEL_SFT (0)
1912
+
#define RT5670_JD_HPO_GPIO_JD1 (0x0)
1913
+
#define RT5670_JD_HPO_JD1_1 (0x1)
1914
+
#define RT5670_JD_HPO_JD1_2 (0x2)
1915
+
#define RT5670_JD_HPO_JD2 (0x3)
1916
+
#define RT5670_JD_HPO_JD3 (0x4)
1917
+
#define RT5670_JD_HPO_GPIO_JD2 (0x5)
1918
+
#define RT5670_JD_HPO_MX0B_12 (0x6)
1919
+
1920
+
/* Digital Misc Control (0xfa) */
1921
+
#define RT5670_RST_DSP (0x1 << 13)
1922
+
#define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1923
+
#define RT5670_IF1_ADC1_IN1_SFT 12
1924
+
#define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1925
+
#define RT5670_IF1_ADC1_IN2_SFT 11
1926
+
#define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1927
+
#define RT5670_IF1_ADC2_IN1_SFT 10
1928
+
1929
+
/* General Control2 (0xfb) */
1930
+
#define RT5670_RXDC_SRC_MASK (0x1 << 7)
1931
+
#define RT5670_RXDC_SRC_STO (0x0 << 7)
1932
+
#define RT5670_RXDC_SRC_MONO (0x1 << 7)
1933
+
#define RT5670_RXDC_SRC_SFT (7)
1934
+
#define RT5670_RXDP2_SEL_MASK (0x1 << 3)
1935
+
#define RT5670_RXDP2_SEL_IF2 (0x0 << 3)
1936
+
#define RT5670_RXDP2_SEL_ADC (0x1 << 3)
1937
+
#define RT5670_RXDP2_SEL_SFT (3)
1938
+
1939
+
/* System Clock Source */
1940
+
enum {
1941
+
RT5670_SCLK_S_MCLK,
1942
+
RT5670_SCLK_S_PLL1,
1943
+
RT5670_SCLK_S_RCCLK,
1944
+
};
1945
+
1946
+
/* PLL1 Source */
1947
+
enum {
1948
+
RT5670_PLL1_S_MCLK,
1949
+
RT5670_PLL1_S_BCLK1,
1950
+
RT5670_PLL1_S_BCLK2,
1951
+
RT5670_PLL1_S_BCLK3,
1952
+
RT5670_PLL1_S_BCLK4,
1953
+
};
1954
+
1955
+
enum {
1956
+
RT5670_AIF1,
1957
+
RT5670_AIF2,
1958
+
RT5670_AIF3,
1959
+
RT5670_AIF4,
1960
+
RT5670_AIFS,
1961
+
};
1962
+
1963
+
enum {
1964
+
RT5670_DMIC_DATA_GPIO6,
1965
+
RT5670_DMIC_DATA_IN2P,
1966
+
RT5670_DMIC_DATA_GPIO7,
1967
+
};
1968
+
1969
+
enum {
1970
+
RT5670_DMIC_DATA_GPIO8,
1971
+
RT5670_DMIC_DATA_IN3N,
1972
+
};
1973
+
1974
+
enum {
1975
+
RT5670_DMIC_DATA_GPIO9,
1976
+
RT5670_DMIC_DATA_GPIO10,
1977
+
RT5670_DMIC_DATA_GPIO5,
1978
+
};
1979
+
1980
+
struct rt5670_priv {
1981
+
struct snd_soc_codec *codec;
1982
+
struct rt5670_platform_data pdata;
1983
+
struct regmap *regmap;
1984
+
1985
+
int sysclk;
1986
+
int sysclk_src;
1987
+
int lrck[RT5670_AIFS];
1988
+
int bclk[RT5670_AIFS];
1989
+
int master[RT5670_AIFS];
1990
+
1991
+
int pll_src;
1992
+
int pll_in;
1993
+
int pll_out;
1994
+
1995
+
int dsp_sw; /* expected parameter setting */
1996
+
int dsp_rate;
1997
+
int jack_type;
1998
+
};
1999
+
2000
+
#endif /* __RT5670_H__ */