drm/radeon/ci_dpm: Move 'si_*()'s prototypes to shared header

Fixes the following W=1 kernel build warning(s):

drivers/gpu/drm/radeon/si_dpm.c:3802:4: warning: no previous prototype for ‘si_get_ddr3_mclk_frequency_ratio’ [-Wmissing-prototypes]
3802 | u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/radeon/si_dpm.c:3815:4: warning: no previous prototype for ‘si_get_mclk_frequency_ratio’ [-Wmissing-prototypes]
3815 | u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/radeon/si_dpm.c:3897:6: warning: no previous prototype for ‘si_trim_voltage_table_to_fit_state_table’ [-Wmissing-prototypes]
3897 | void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Cc: Alex Deucher <[e-mail]>
Cc: "Christian König" <[e-mail]>
Cc: David Airlie <[e-mail]>
Cc: Daniel Vetter <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Signed-off-by: Lee Jones <[e-mail]>
Signed-off-by: Alex Deucher <[e-mail]>

drivers/gpu/drm/radeon/ci_dpm.c

···
 #include "radeon.h"
 #include "radeon_asic.h"
 #include "radeon_ucode.h"
+#include "si_dpm.h"
 
 #define MC_CG_ARB_FREQ_F0           0x0a
 #define MC_CG_ARB_FREQ_F1           0x0b
···
 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 				       u32 arb_freq_src, u32 arb_freq_dest);
-extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
-extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
-extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
-						     u32 max_voltage_steps,
-						     struct atom_voltage_table *voltage_table);
 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 					 struct atom_voltage_table_entry *voltage_table,
 					 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);

drivers/gpu/drm/radeon/si_dpm.h

···
 #define SISLANDS_CGULVPARAMETER_DFLT                    0x00040035
 #define SISLANDS_CGULVCONTROL_DFLT                      0x1f007550
 
+u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
+u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
+void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
+					      u32 max_voltage_steps,
+					      struct atom_voltage_table *voltage_table);
 
 #endif