drm/radeon: use lower_32_bits where appropriate

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Replace occurrences of "v & 0xffffffff" with lower_32_bits(v)
when it's next to an upper_32_bits(v). Also remove unnecessary
"upper_32_bits(v) & 0xffffffff" code snippets.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Christian König and committed by

Alex Deucher 12 years ago 5e167cdb 4c0dae57

+27 -27

7 changed files

expand all

drivers

gpu

drm

radeon

cik.c

cik_sdma.c

ni.c

r600.c

si.c

si_dma.c

uvd_v2_2.c

+2 -2

drivers/gpu/drm/radeon/cik.c

··· 3698 3698 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3699 3699 3700 3700 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 3701 - radeon_ring_write(ring, addr & 0xffffffff); 3701 + radeon_ring_write(ring, lower_32_bits(addr)); 3702 3702 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); 3703 3703 3704 3704 return true; ··· 3818 3818 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3819 3819 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); 3820 3820 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3821 - radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 3821 + radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 3822 3822 radeon_ring_write(ring, next_rptr); 3823 3823 } 3824 3824

+13 -13

drivers/gpu/drm/radeon/cik_sdma.c

··· 141 141 next_rptr += 4; 142 142 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 143 143 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 144 - radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 144 + radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 145 145 radeon_ring_write(ring, 1); /* number of DWs to follow */ 146 146 radeon_ring_write(ring, next_rptr); 147 147 } ··· 151 151 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 152 152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 153 153 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 154 - radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 154 + radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 155 155 radeon_ring_write(ring, ib->length_dw); 156 156 157 157 } ··· 203 203 204 204 /* write the fence */ 205 205 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 206 - radeon_ring_write(ring, addr & 0xffffffff); 207 - radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 206 + radeon_ring_write(ring, lower_32_bits(addr)); 207 + radeon_ring_write(ring, upper_32_bits(addr)); 208 208 radeon_ring_write(ring, fence->seq); 209 209 /* generate an interrupt */ 210 210 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); ··· 233 233 234 234 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 235 235 radeon_ring_write(ring, addr & 0xfffffff8); 236 - radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 236 + radeon_ring_write(ring, upper_32_bits(addr)); 237 237 238 238 return true; 239 239 } ··· 551 551 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 552 552 radeon_ring_write(ring, cur_size_in_bytes); 553 553 radeon_ring_write(ring, 0); /* src/dst endian swap */ 554 - radeon_ring_write(ring, src_offset & 0xffffffff); 555 - radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff); 556 - radeon_ring_write(ring, dst_offset & 0xffffffff); 557 - radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff); 554 + radeon_ring_write(ring, lower_32_bits(src_offset)); 555 + radeon_ring_write(ring, upper_32_bits(src_offset)); 556 + radeon_ring_write(ring, lower_32_bits(dst_offset)); 557 + radeon_ring_write(ring, upper_32_bits(dst_offset)); 558 558 src_offset += cur_size_in_bytes; 559 559 dst_offset += cur_size_in_bytes; 560 560 } ··· 605 605 } 606 606 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 607 607 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 608 - radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff); 608 + radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); 609 609 radeon_ring_write(ring, 1); /* number of DWs to follow */ 610 610 radeon_ring_write(ring, 0xDEADBEEF); 611 611 radeon_ring_unlock_commit(rdev, ring); ··· 660 660 661 661 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 662 662 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 663 - ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff; 663 + ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr); 664 664 ib.ptr[3] = 1; 665 665 ib.ptr[4] = 0xDEADBEEF; 666 666 ib.length_dw = 5; ··· 752 752 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 753 753 ib->ptr[ib->length_dw++] = bytes; 754 754 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 755 - ib->ptr[ib->length_dw++] = src & 0xffffffff; 755 + ib->ptr[ib->length_dw++] = lower_32_bits(src); 756 756 ib->ptr[ib->length_dw++] = upper_32_bits(src); 757 - ib->ptr[ib->length_dw++] = pe & 0xffffffff; 757 + ib->ptr[ib->length_dw++] = lower_32_bits(pe); 758 758 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 759 759 760 760 pe += bytes;

+1 -1

drivers/gpu/drm/radeon/ni.c

··· 1346 1346 /* EVENT_WRITE_EOP - flush caches, send int */ 1347 1347 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1348 1348 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 1349 - radeon_ring_write(ring, addr & 0xffffffff); 1349 + radeon_ring_write(ring, lower_32_bits(addr)); 1350 1350 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1351 1351 radeon_ring_write(ring, fence->seq); 1352 1352 radeon_ring_write(ring, 0);

+4 -4

drivers/gpu/drm/radeon/r600.c

··· 2724 2724 /* EVENT_WRITE_EOP - flush caches, send int */ 2725 2725 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2726 2726 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2727 - radeon_ring_write(ring, addr & 0xffffffff); 2727 + radeon_ring_write(ring, lower_32_bits(addr)); 2728 2728 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2729 2729 radeon_ring_write(ring, fence->seq); 2730 2730 radeon_ring_write(ring, 0); ··· 2763 2763 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2764 2764 2765 2765 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2766 - radeon_ring_write(ring, addr & 0xffffffff); 2766 + radeon_ring_write(ring, lower_32_bits(addr)); 2767 2767 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2768 2768 2769 2769 return true; ··· 2824 2824 if (size_in_bytes == 0) 2825 2825 tmp |= PACKET3_CP_DMA_CP_SYNC; 2826 2826 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 2827 - radeon_ring_write(ring, src_offset & 0xffffffff); 2827 + radeon_ring_write(ring, lower_32_bits(src_offset)); 2828 2828 radeon_ring_write(ring, tmp); 2829 - radeon_ring_write(ring, dst_offset & 0xffffffff); 2829 + radeon_ring_write(ring, lower_32_bits(dst_offset)); 2830 2830 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 2831 2831 radeon_ring_write(ring, cur_size_in_bytes); 2832 2832 src_offset += cur_size_in_bytes;

+2 -2

drivers/gpu/drm/radeon/si.c

··· 3186 3186 /* EVENT_WRITE_EOP - flush caches, send int */ 3187 3187 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3188 3188 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 3189 - radeon_ring_write(ring, addr & 0xffffffff); 3189 + radeon_ring_write(ring, lower_32_bits(addr)); 3190 3190 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 3191 3191 radeon_ring_write(ring, fence->seq); 3192 3192 radeon_ring_write(ring, 0); ··· 3219 3219 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3220 3220 radeon_ring_write(ring, (1 << 8)); 3221 3221 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3222 - radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 3222 + radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 3223 3223 radeon_ring_write(ring, next_rptr); 3224 3224 } 3225 3225

+4 -4

drivers/gpu/drm/radeon/si_dma.c

··· 88 88 89 89 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, 90 90 1, 0, 0, bytes); 91 - ib->ptr[ib->length_dw++] = pe & 0xffffffff; 92 - ib->ptr[ib->length_dw++] = src & 0xffffffff; 91 + ib->ptr[ib->length_dw++] = lower_32_bits(pe); 92 + ib->ptr[ib->length_dw++] = lower_32_bits(src); 93 93 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 94 94 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; 95 95 ··· 220 220 cur_size_in_bytes = 0xFFFFF; 221 221 size_in_bytes -= cur_size_in_bytes; 222 222 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); 223 - radeon_ring_write(ring, dst_offset & 0xffffffff); 224 - radeon_ring_write(ring, src_offset & 0xffffffff); 223 + radeon_ring_write(ring, lower_32_bits(dst_offset)); 224 + radeon_ring_write(ring, lower_32_bits(src_offset)); 225 225 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 226 226 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 227 227 src_offset += cur_size_in_bytes;

+1 -1

drivers/gpu/drm/radeon/uvd_v2_2.c

··· 45 45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 46 46 radeon_ring_write(ring, fence->seq); 47 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 48 - radeon_ring_write(ring, addr & 0xffffffff); 48 + radeon_ring_write(ring, lower_32_bits(addr)); 49 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 50 50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 51 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));