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drm/i915: gt-fy sseu debugfs

Ahead of moving the sseu debugfs logic under gt/, update the functions
to use intel_gt where possible to make the move cleaner.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-9-daniele.ceraolospurio@intel.com

authored by

Daniele Ceraolo Spurio and committed by
Chris Wilson 5df79ff1 0b6613c6

+51 -44
+51 -44
drivers/gpu/drm/i915/i915_debugfs.c
··· 1578 1578 return 0; 1579 1579 } 1580 1580 1581 - static void 1582 - intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice, 1583 - u8 *to_mask) 1581 + DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, 1582 + i915_cache_sharing_get, i915_cache_sharing_set, 1583 + "%llu\n"); 1584 + 1585 + static void sseu_copy_subslices(const struct sseu_dev_info *sseu, 1586 + int slice, u8 *to_mask) 1584 1587 { 1585 1588 int offset = slice * sseu->ss_stride; 1586 1589 1587 1590 memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); 1588 1591 } 1589 1592 1590 - DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, 1591 - i915_cache_sharing_get, i915_cache_sharing_set, 1592 - "%llu\n"); 1593 - 1594 - static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, 1593 + static void cherryview_sseu_device_status(struct intel_gt *gt, 1595 1594 struct sseu_dev_info *sseu) 1596 1595 { 1597 1596 #define SS_MAX 2 1597 + struct intel_uncore *uncore = gt->uncore; 1598 1598 const int ss_max = SS_MAX; 1599 1599 u32 sig1[SS_MAX], sig2[SS_MAX]; 1600 1600 int ss; 1601 1601 1602 - sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); 1603 - sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); 1604 - sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); 1605 - sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); 1602 + sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1); 1603 + sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1); 1604 + sig2[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG2); 1605 + sig2[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG2); 1606 1606 1607 1607 for (ss = 0; ss < ss_max; ss++) { 1608 1608 unsigned int eu_cnt; ··· 1624 1624 #undef SS_MAX 1625 1625 } 1626 1626 1627 - static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, 1627 + static void gen10_sseu_device_status(struct intel_gt *gt, 1628 1628 struct sseu_dev_info *sseu) 1629 1629 { 1630 1630 #define SS_MAX 6 1631 - const struct intel_gt_info *info = &dev_priv->gt.info; 1631 + struct intel_uncore *uncore = gt->uncore; 1632 + const struct intel_gt_info *info = &gt->info; 1632 1633 u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; 1633 1634 int s, ss; 1634 1635 ··· 1640 1639 * although this seems wrong because it would leave many 1641 1640 * subslices without ACK. 1642 1641 */ 1643 - s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) & 1642 + s_reg[s] = intel_uncore_read(uncore, GEN10_SLICE_PGCTL_ACK(s)) & 1644 1643 GEN10_PGCTL_VALID_SS_MASK(s); 1645 - eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s)); 1646 - eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s)); 1644 + eu_reg[2 * s] = intel_uncore_read(uncore, 1645 + GEN10_SS01_EU_PGCTL_ACK(s)); 1646 + eu_reg[2 * s + 1] = intel_uncore_read(uncore, 1647 + GEN10_SS23_EU_PGCTL_ACK(s)); 1647 1648 } 1648 1649 1649 1650 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | ··· 1663 1660 continue; 1664 1661 1665 1662 sseu->slice_mask |= BIT(s); 1666 - intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask); 1663 + sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask); 1667 1664 1668 1665 for (ss = 0; ss < info->sseu.max_subslices; ss++) { 1669 1666 unsigned int eu_cnt; ··· 1684 1681 #undef SS_MAX 1685 1682 } 1686 1683 1687 - static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 1684 + static void gen9_sseu_device_status(struct intel_gt *gt, 1688 1685 struct sseu_dev_info *sseu) 1689 1686 { 1690 1687 #define SS_MAX 3 1691 - const struct intel_gt_info *info = &dev_priv->gt.info; 1688 + struct intel_uncore *uncore = gt->uncore; 1689 + const struct intel_gt_info *info = &gt->info; 1692 1690 u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; 1693 1691 int s, ss; 1694 1692 1695 1693 for (s = 0; s < info->sseu.max_slices; s++) { 1696 - s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); 1697 - eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); 1698 - eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); 1694 + s_reg[s] = intel_uncore_read(uncore, GEN9_SLICE_PGCTL_ACK(s)); 1695 + eu_reg[2 * s] = 1696 + intel_uncore_read(uncore, GEN9_SS01_EU_PGCTL_ACK(s)); 1697 + eu_reg[2 * s + 1] = 1698 + intel_uncore_read(uncore, GEN9_SS23_EU_PGCTL_ACK(s)); 1699 1699 } 1700 1700 1701 1701 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | ··· 1717 1711 1718 1712 sseu->slice_mask |= BIT(s); 1719 1713 1720 - if (IS_GEN9_BC(dev_priv)) 1721 - intel_sseu_copy_subslices(&info->sseu, s, 1722 - sseu->subslice_mask); 1714 + if (IS_GEN9_BC(gt->i915)) 1715 + sseu_copy_subslices(&info->sseu, s, 1716 + sseu->subslice_mask); 1723 1717 1724 1718 for (ss = 0; ss < info->sseu.max_subslices; ss++) { 1725 1719 unsigned int eu_cnt; 1726 1720 u8 ss_idx = s * info->sseu.ss_stride + 1727 1721 ss / BITS_PER_BYTE; 1728 1722 1729 - if (IS_GEN9_LP(dev_priv)) { 1723 + if (IS_GEN9_LP(gt->i915)) { 1730 1724 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) 1731 1725 /* skip disabled subslice */ 1732 1726 continue; ··· 1746 1740 #undef SS_MAX 1747 1741 } 1748 1742 1749 - static void bdw_sseu_device_status(struct drm_i915_private *dev_priv, 1743 + static void bdw_sseu_device_status(struct intel_gt *gt, 1750 1744 struct sseu_dev_info *sseu) 1751 1745 { 1752 - const struct intel_gt_info *info = &dev_priv->gt.info; 1753 - u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); 1746 + const struct intel_gt_info *info = &gt->info; 1747 + u32 slice_info = intel_uncore_read(gt->uncore, GEN8_GT_SLICE_INFO); 1754 1748 int s; 1755 1749 1756 1750 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; ··· 1758 1752 if (sseu->slice_mask) { 1759 1753 sseu->eu_per_subslice = info->sseu.eu_per_subslice; 1760 1754 for (s = 0; s < fls(sseu->slice_mask); s++) 1761 - intel_sseu_copy_subslices(&info->sseu, s, 1762 - sseu->subslice_mask); 1755 + sseu_copy_subslices(&info->sseu, s, 1756 + sseu->subslice_mask); 1763 1757 sseu->eu_total = sseu->eu_per_subslice * 1764 1758 intel_sseu_subslice_total(sseu); 1765 1759 ··· 1811 1805 1812 1806 static int i915_sseu_status(struct seq_file *m, void *unused) 1813 1807 { 1814 - struct drm_i915_private *dev_priv = node_to_i915(m->private); 1815 - const struct intel_gt_info *info = &dev_priv->gt.info; 1808 + struct drm_i915_private *i915 = node_to_i915(m->private); 1809 + struct intel_gt *gt = &i915->gt; 1810 + const struct intel_gt_info *info = &gt->info; 1816 1811 struct sseu_dev_info sseu; 1817 1812 intel_wakeref_t wakeref; 1818 1813 1819 - if (INTEL_GEN(dev_priv) < 8) 1814 + if (INTEL_GEN(i915) < 8) 1820 1815 return -ENODEV; 1821 1816 1822 1817 seq_puts(m, "SSEU Device Info\n"); ··· 1829 1822 info->sseu.max_subslices, 1830 1823 info->sseu.max_eus_per_subslice); 1831 1824 1832 - with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { 1833 - if (IS_CHERRYVIEW(dev_priv)) 1834 - cherryview_sseu_device_status(dev_priv, &sseu); 1835 - else if (IS_BROADWELL(dev_priv)) 1836 - bdw_sseu_device_status(dev_priv, &sseu); 1837 - else if (IS_GEN(dev_priv, 9)) 1838 - gen9_sseu_device_status(dev_priv, &sseu); 1839 - else if (INTEL_GEN(dev_priv) >= 10) 1840 - gen10_sseu_device_status(dev_priv, &sseu); 1825 + with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 1826 + if (IS_CHERRYVIEW(i915)) 1827 + cherryview_sseu_device_status(gt, &sseu); 1828 + else if (IS_BROADWELL(i915)) 1829 + bdw_sseu_device_status(gt, &sseu); 1830 + else if (IS_GEN(i915, 9)) 1831 + gen9_sseu_device_status(gt, &sseu); 1832 + else if (INTEL_GEN(i915) >= 10) 1833 + gen10_sseu_device_status(gt, &sseu); 1841 1834 } 1842 1835 1843 1836 i915_print_sseu_info(m, false, &sseu);