Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dmaengine: hisilicon: Dump regs to debugfs

This patch adds dump of registers with debugfs for HIP08
and HIP09 DMA driver.

Signed-off-by: Jie Hai <haijie1@huawei.com>
Acked-by: Zhou Wang <wangzhou1@hisilicon.com>
Link: https://lore.kernel.org/r/20220830062251.52993-7-haijie1@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Jie Hai and committed by
Vinod Koul
5dda7a62 fd5273fa

+236 -2
+236 -2
drivers/dma/hisi_dma.c
··· 78 78 #define HISI_DMA_POLL_Q_STS_DELAY_US 10 79 79 #define HISI_DMA_POLL_Q_STS_TIME_OUT_US 1000 80 80 81 + #define HISI_DMA_MAX_DIR_NAME_LEN 128 82 + 81 83 /* 82 84 * The HIP08B(HiSilicon IP08) and HIP09A(HiSilicon IP09) are DMA iEPs, they 83 85 * have the same pci device id but different pci revision. ··· 165 163 void __iomem *queue_base; /* queue region start of register */ 166 164 struct hisi_dma_chan chan[]; 167 165 }; 166 + 167 + #ifdef CONFIG_DEBUG_FS 168 + 169 + static const struct debugfs_reg32 hisi_dma_comm_chan_regs[] = { 170 + {"DMA_QUEUE_SQ_DEPTH ", 0x0008ull}, 171 + {"DMA_QUEUE_SQ_TAIL_PTR ", 0x000Cull}, 172 + {"DMA_QUEUE_CQ_DEPTH ", 0x0018ull}, 173 + {"DMA_QUEUE_CQ_HEAD_PTR ", 0x001Cull}, 174 + {"DMA_QUEUE_CTRL0 ", 0x0020ull}, 175 + {"DMA_QUEUE_CTRL1 ", 0x0024ull}, 176 + {"DMA_QUEUE_FSM_STS ", 0x0030ull}, 177 + {"DMA_QUEUE_SQ_STS ", 0x0034ull}, 178 + {"DMA_QUEUE_CQ_TAIL_PTR ", 0x003Cull}, 179 + {"DMA_QUEUE_INT_STS ", 0x0040ull}, 180 + {"DMA_QUEUE_INT_MSK ", 0x0044ull}, 181 + {"DMA_QUEUE_INT_RO ", 0x006Cull}, 182 + }; 183 + 184 + static const struct debugfs_reg32 hisi_dma_hip08_chan_regs[] = { 185 + {"DMA_QUEUE_BYTE_CNT ", 0x0038ull}, 186 + {"DMA_ERR_INT_NUM6 ", 0x0048ull}, 187 + {"DMA_QUEUE_DESP0 ", 0x0050ull}, 188 + {"DMA_QUEUE_DESP1 ", 0x0054ull}, 189 + {"DMA_QUEUE_DESP2 ", 0x0058ull}, 190 + {"DMA_QUEUE_DESP3 ", 0x005Cull}, 191 + {"DMA_QUEUE_DESP4 ", 0x0074ull}, 192 + {"DMA_QUEUE_DESP5 ", 0x0078ull}, 193 + {"DMA_QUEUE_DESP6 ", 0x007Cull}, 194 + {"DMA_QUEUE_DESP7 ", 0x0080ull}, 195 + {"DMA_ERR_INT_NUM0 ", 0x0084ull}, 196 + {"DMA_ERR_INT_NUM1 ", 0x0088ull}, 197 + {"DMA_ERR_INT_NUM2 ", 0x008Cull}, 198 + {"DMA_ERR_INT_NUM3 ", 0x0090ull}, 199 + {"DMA_ERR_INT_NUM4 ", 0x0094ull}, 200 + {"DMA_ERR_INT_NUM5 ", 0x0098ull}, 201 + {"DMA_QUEUE_SQ_STS2 ", 0x00A4ull}, 202 + }; 203 + 204 + static const struct debugfs_reg32 hisi_dma_hip09_chan_regs[] = { 205 + {"DMA_QUEUE_ERR_INT_STS ", 0x0048ull}, 206 + {"DMA_QUEUE_ERR_INT_MSK ", 0x004Cull}, 207 + {"DFX_SQ_READ_ERR_PTR ", 0x0068ull}, 208 + {"DFX_DMA_ERR_INT_NUM0 ", 0x0084ull}, 209 + {"DFX_DMA_ERR_INT_NUM1 ", 0x0088ull}, 210 + {"DFX_DMA_ERR_INT_NUM2 ", 0x008Cull}, 211 + {"DFX_DMA_QUEUE_SQ_STS2 ", 0x00A4ull}, 212 + }; 213 + 214 + static const struct debugfs_reg32 hisi_dma_hip08_comm_regs[] = { 215 + {"DMA_ECC_ERR_ADDR ", 0x2004ull}, 216 + {"DMA_ECC_ECC_CNT ", 0x2014ull}, 217 + {"COMMON_AND_CH_ERR_STS ", 0x2030ull}, 218 + {"LOCAL_CPL_ID_STS_0 ", 0x20E0ull}, 219 + {"LOCAL_CPL_ID_STS_1 ", 0x20E4ull}, 220 + {"LOCAL_CPL_ID_STS_2 ", 0x20E8ull}, 221 + {"LOCAL_CPL_ID_STS_3 ", 0x20ECull}, 222 + {"LOCAL_TLP_NUM ", 0x2158ull}, 223 + {"SQCQ_TLP_NUM ", 0x2164ull}, 224 + {"CPL_NUM ", 0x2168ull}, 225 + {"INF_BACK_PRESS_STS ", 0x2170ull}, 226 + {"DMA_CH_RAS_LEVEL ", 0x2184ull}, 227 + {"DMA_CM_RAS_LEVEL ", 0x2188ull}, 228 + {"DMA_CH_ERR_STS ", 0x2190ull}, 229 + {"DMA_CH_DONE_STS ", 0x2194ull}, 230 + {"DMA_SQ_TAG_STS_0 ", 0x21A0ull}, 231 + {"DMA_SQ_TAG_STS_1 ", 0x21A4ull}, 232 + {"DMA_SQ_TAG_STS_2 ", 0x21A8ull}, 233 + {"DMA_SQ_TAG_STS_3 ", 0x21ACull}, 234 + {"LOCAL_P_ID_STS_0 ", 0x21B0ull}, 235 + {"LOCAL_P_ID_STS_1 ", 0x21B4ull}, 236 + {"LOCAL_P_ID_STS_2 ", 0x21B8ull}, 237 + {"LOCAL_P_ID_STS_3 ", 0x21BCull}, 238 + {"DMA_PREBUFF_INFO_0 ", 0x2200ull}, 239 + {"DMA_CM_TABLE_INFO_0 ", 0x2220ull}, 240 + {"DMA_CM_CE_RO ", 0x2244ull}, 241 + {"DMA_CM_NFE_RO ", 0x2248ull}, 242 + {"DMA_CM_FE_RO ", 0x224Cull}, 243 + }; 244 + 245 + static const struct debugfs_reg32 hisi_dma_hip09_comm_regs[] = { 246 + {"COMMON_AND_CH_ERR_STS ", 0x0030ull}, 247 + {"DMA_PORT_IDLE_STS ", 0x0150ull}, 248 + {"DMA_CH_RAS_LEVEL ", 0x0184ull}, 249 + {"DMA_CM_RAS_LEVEL ", 0x0188ull}, 250 + {"DMA_CM_CE_RO ", 0x0244ull}, 251 + {"DMA_CM_NFE_RO ", 0x0248ull}, 252 + {"DMA_CM_FE_RO ", 0x024Cull}, 253 + {"DFX_INF_BACK_PRESS_STS0 ", 0x1A40ull}, 254 + {"DFX_INF_BACK_PRESS_STS1 ", 0x1A44ull}, 255 + {"DFX_INF_BACK_PRESS_STS2 ", 0x1A48ull}, 256 + {"DFX_DMA_WRR_DISABLE ", 0x1A4Cull}, 257 + {"DFX_PA_REQ_TLP_NUM ", 0x1C00ull}, 258 + {"DFX_PA_BACK_TLP_NUM ", 0x1C04ull}, 259 + {"DFX_PA_RETRY_TLP_NUM ", 0x1C08ull}, 260 + {"DFX_LOCAL_NP_TLP_NUM ", 0x1C0Cull}, 261 + {"DFX_LOCAL_CPL_HEAD_TLP_NUM ", 0x1C10ull}, 262 + {"DFX_LOCAL_CPL_DATA_TLP_NUM ", 0x1C14ull}, 263 + {"DFX_LOCAL_CPL_EXT_DATA_TLP_NUM ", 0x1C18ull}, 264 + {"DFX_LOCAL_P_HEAD_TLP_NUM ", 0x1C1Cull}, 265 + {"DFX_LOCAL_P_ACK_TLP_NUM ", 0x1C20ull}, 266 + {"DFX_BUF_ALOC_PORT_REQ_NUM ", 0x1C24ull}, 267 + {"DFX_BUF_ALOC_PORT_RESULT_NUM ", 0x1C28ull}, 268 + {"DFX_BUF_FAIL_SIZE_NUM ", 0x1C2Cull}, 269 + {"DFX_BUF_ALOC_SIZE_NUM ", 0x1C30ull}, 270 + {"DFX_BUF_NP_RELEASE_SIZE_NUM ", 0x1C34ull}, 271 + {"DFX_BUF_P_RELEASE_SIZE_NUM ", 0x1C38ull}, 272 + {"DFX_BUF_PORT_RELEASE_SIZE_NUM ", 0x1C3Cull}, 273 + {"DFX_DMA_PREBUF_MEM0_ECC_ERR_ADDR ", 0x1CA8ull}, 274 + {"DFX_DMA_PREBUF_MEM0_ECC_CNT ", 0x1CACull}, 275 + {"DFX_DMA_LOC_NP_OSTB_ECC_ERR_ADDR ", 0x1CB0ull}, 276 + {"DFX_DMA_LOC_NP_OSTB_ECC_CNT ", 0x1CB4ull}, 277 + {"DFX_DMA_PREBUF_MEM1_ECC_ERR_ADDR ", 0x1CC0ull}, 278 + {"DFX_DMA_PREBUF_MEM1_ECC_CNT ", 0x1CC4ull}, 279 + {"DMA_CH_DONE_STS ", 0x02E0ull}, 280 + {"DMA_CH_ERR_STS ", 0x0320ull}, 281 + }; 282 + #endif /* CONFIG_DEBUG_FS*/ 168 283 169 284 static enum hisi_dma_reg_layout hisi_dma_get_reg_layout(struct pci_dev *pdev) 170 285 { ··· 836 717 INIT_LIST_HEAD(&dma_dev->channels); 837 718 } 838 719 720 + /* --- debugfs implementation --- */ 721 + #ifdef CONFIG_DEBUG_FS 722 + #include <linux/debugfs.h> 723 + static struct debugfs_reg32 *hisi_dma_get_ch_regs(struct hisi_dma_dev *hdma_dev, 724 + u32 *regs_sz) 725 + { 726 + struct device *dev = &hdma_dev->pdev->dev; 727 + struct debugfs_reg32 *regs; 728 + u32 regs_sz_comm; 729 + 730 + regs_sz_comm = ARRAY_SIZE(hisi_dma_comm_chan_regs); 731 + 732 + if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) 733 + *regs_sz = regs_sz_comm + ARRAY_SIZE(hisi_dma_hip08_chan_regs); 734 + else 735 + *regs_sz = regs_sz_comm + ARRAY_SIZE(hisi_dma_hip09_chan_regs); 736 + 737 + regs = devm_kcalloc(dev, *regs_sz, sizeof(struct debugfs_reg32), 738 + GFP_KERNEL); 739 + if (!regs) 740 + return NULL; 741 + memcpy(regs, hisi_dma_comm_chan_regs, sizeof(hisi_dma_comm_chan_regs)); 742 + 743 + if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) 744 + memcpy(regs + regs_sz_comm, hisi_dma_hip08_chan_regs, 745 + sizeof(hisi_dma_hip08_chan_regs)); 746 + else 747 + memcpy(regs + regs_sz_comm, hisi_dma_hip09_chan_regs, 748 + sizeof(hisi_dma_hip09_chan_regs)); 749 + 750 + return regs; 751 + } 752 + 753 + static int hisi_dma_create_chan_dir(struct hisi_dma_dev *hdma_dev) 754 + { 755 + char dir_name[HISI_DMA_MAX_DIR_NAME_LEN]; 756 + struct debugfs_regset32 *regsets; 757 + struct debugfs_reg32 *regs; 758 + struct dentry *chan_dir; 759 + struct device *dev; 760 + u32 regs_sz; 761 + int ret; 762 + int i; 763 + 764 + dev = &hdma_dev->pdev->dev; 765 + 766 + regsets = devm_kcalloc(dev, hdma_dev->chan_num, 767 + sizeof(*regsets), GFP_KERNEL); 768 + if (!regsets) 769 + return -ENOMEM; 770 + 771 + regs = hisi_dma_get_ch_regs(hdma_dev, &regs_sz); 772 + if (!regs) 773 + return -ENOMEM; 774 + 775 + for (i = 0; i < hdma_dev->chan_num; i++) { 776 + regsets[i].regs = regs; 777 + regsets[i].nregs = regs_sz; 778 + regsets[i].base = hdma_dev->queue_base + i * HISI_DMA_Q_OFFSET; 779 + regsets[i].dev = dev; 780 + 781 + memset(dir_name, 0, HISI_DMA_MAX_DIR_NAME_LEN); 782 + ret = sprintf(dir_name, "channel%d", i); 783 + if (ret < 0) 784 + return ret; 785 + 786 + chan_dir = debugfs_create_dir(dir_name, 787 + hdma_dev->dma_dev.dbg_dev_root); 788 + debugfs_create_regset32("regs", 0444, chan_dir, &regsets[i]); 789 + } 790 + 791 + return 0; 792 + } 793 + 794 + static void hisi_dma_create_debugfs(struct hisi_dma_dev *hdma_dev) 795 + { 796 + struct debugfs_regset32 *regset; 797 + struct device *dev; 798 + int ret; 799 + 800 + dev = &hdma_dev->pdev->dev; 801 + 802 + if (hdma_dev->dma_dev.dbg_dev_root == NULL) 803 + return; 804 + 805 + regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 806 + if (!regset) 807 + return; 808 + 809 + if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { 810 + regset->regs = hisi_dma_hip08_comm_regs; 811 + regset->nregs = ARRAY_SIZE(hisi_dma_hip08_comm_regs); 812 + } else { 813 + regset->regs = hisi_dma_hip09_comm_regs; 814 + regset->nregs = ARRAY_SIZE(hisi_dma_hip09_comm_regs); 815 + } 816 + regset->base = hdma_dev->base; 817 + regset->dev = dev; 818 + 819 + debugfs_create_regset32("regs", 0444, 820 + hdma_dev->dma_dev.dbg_dev_root, regset); 821 + 822 + ret = hisi_dma_create_chan_dir(hdma_dev); 823 + if (ret < 0) 824 + dev_info(&hdma_dev->pdev->dev, "fail to create debugfs for channels!\n"); 825 + } 826 + #else 827 + static void hisi_dma_create_debugfs(struct hisi_dma_dev *hdma_dev) { } 828 + #endif /* CONFIG_DEBUG_FS*/ 829 + /* --- debugfs implementation --- */ 830 + 839 831 static int hisi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id) 840 832 { 841 833 enum hisi_dma_reg_layout reg_layout; ··· 1023 793 1024 794 dma_dev = &hdma_dev->dma_dev; 1025 795 ret = dmaenginem_async_device_register(dma_dev); 1026 - if (ret < 0) 796 + if (ret < 0) { 1027 797 dev_err(dev, "failed to register device!\n"); 798 + return ret; 799 + } 1028 800 1029 - return ret; 801 + hisi_dma_create_debugfs(hdma_dev); 802 + 803 + return 0; 1030 804 } 1031 805 1032 806 static const struct pci_device_id hisi_dma_pci_tbl[] = {