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Merge branch 'net-sparx5-prepare-for-lan969x-switch-driver'

Daniel Machon says:

====================
net: sparx5: prepare for lan969x switch driver

== Description:

This series is the first of a multi-part series, that prepares and adds
support for the new lan969x switch driver.

The upstreaming efforts is split into multiple series (might change a
bit as we go along):

1) Prepare the Sparx5 driver for lan969x (this series)
2) Add support lan969x (same basic features as Sparx5 provides +
RGMII, excl. FDMA and VCAP)
3) Add support for lan969x FDMA
4) Add support for lan969x VCAP

== Lan969x in short:

The lan969x Ethernet switch family [1] provides a rich set of
switching features and port configurations (up to 30 ports) from 10Mbps
to 10Gbps, with support for RGMII, SGMII, QSGMII, USGMII, and USXGMII,
ideal for industrial & process automation infrastructure applications,
transport, grid automation, power substation automation, and ring &
intra-ring topologies. The LAN969x family is hardware and software
compatible and scalable supporting 46Gbps to 102Gbps switch bandwidths.

== Preparing Sparx5 for lan969x:

The lan969x switch chip reuses many of the IP's of the Sparx5 switch
chip, therefore it has been decided to add support through the existing
Sparx5 driver, in order to avoid a bunch of duplicate code. However, in
order to reuse the Sparx5 switch driver, we have to introduce some
mechanisms to handle the chip differences that are there. These
mechanisms are:

- Platform match data to contain all the differences that needs to
be handled (constants, ops etc.)

- Register macro indirection layer so that we can reuse the existing
register macros.

- Function for branching out on platform type where required.

In some places we ops out functions and in other places we branch on the
chip type. Exactly when we choose one over the other, is an estimate in
each case.

After this series is applied, the Sparx5 driver will be prepared for
lan969x and still function exactly as before.

== Patch breakdown:

Patch #1 adds private match data

Patch #2 adds register macro indirection layer

Patch #3-#4 does some preparation work

Patch #5-#7 adds chip constants and updates the code to use them

Patch #8-#13 adds and uses ops for handling functions differently on the
two platforms.

Patch #14 adds and uses a macro for branching out on the chip type.

Patch #15 (NEW) redefines macros for internal ports and PGID's.

[1] https://www.microchip.com/en-us/product/lan9698

To: David S. Miller <davem@davemloft.net>
To: Eric Dumazet <edumazet@google.com>
To: Jakub Kicinski <kuba@kernel.org>
To: Paolo Abeni <pabeni@redhat.com>
To: Lars Povlsen <lars.povlsen@microchip.com>
To: Steen Hegelund <Steen.Hegelund@microchip.com>
To: horatiu.vultur@microchip.com
To: jensemil.schulzostergaard@microchip.com
To: UNGLinuxDriver@microchip.com
To: Richard Cochran <richardcochran@gmail.com>
To: horms@kernel.org
To: justinstitt@google.com
To: gal@nvidia.com
To: aakash.r.menon@gmail.com
To: jacob.e.keller@intel.com
To: ast@fiberby.net
Cc: netdev@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
====================

Link: https://patch.msgid.link/20241004-b4-sparx5-lan969x-switch-driver-v2-0-d3290f581663@microchip.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

Paolo Abeni 5d6a8aea e793b86a

+3525 -2220
+1 -1
drivers/net/ethernet/microchip/sparx5/Makefile
··· 11 11 sparx5_ptp.o sparx5_pgid.o sparx5_tc.o sparx5_qos.o \ 12 12 sparx5_vcap_impl.o sparx5_vcap_ag_api.o sparx5_tc_flower.o \ 13 13 sparx5_tc_matchall.o sparx5_pool.o sparx5_sdlb.o sparx5_police.o \ 14 - sparx5_psfp.o sparx5_mirror.o 14 + sparx5_psfp.o sparx5_mirror.o sparx5_regs.o 15 15 16 16 sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o 17 17 sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o
+25 -31
drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
··· 15 15 #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */ 16 16 17 17 /* DSM calendar information */ 18 - #define SPX5_DSM_CAL_LEN 64 19 18 #define SPX5_DSM_CAL_EMPTY 0xFFFF 20 - #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 21 19 #define SPX5_DSM_CAL_TAXIS 8 22 20 #define SPX5_DSM_CAL_BW_LOSS 553 23 21 ··· 33 35 {62, 51, 52, 53, 99, 99, 99, 99, 99, 99, 99, 99, 99}, 34 36 {56, 63, 54, 55, 99, 99, 99, 99, 99, 99, 99, 99, 99}, 35 37 {64, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99}, 36 - }; 37 - 38 - struct sparx5_calendar_data { 39 - u32 schedule[SPX5_DSM_CAL_LEN]; 40 - u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 41 - u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 42 - u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 43 - u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 44 - u32 new_slots[SPX5_DSM_CAL_LEN]; 45 - u32 temp_sched[SPX5_DSM_CAL_LEN]; 46 - u32 indices[SPX5_DSM_CAL_LEN]; 47 - u32 short_list[SPX5_DSM_CAL_LEN]; 48 - u32 long_list[SPX5_DSM_CAL_LEN]; 49 38 }; 50 39 51 40 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) ··· 116 131 { 117 132 struct sparx5_port *port; 118 133 119 - if (portno >= SPX5_PORTS) { 134 + if (portno >= sparx5->data->consts->n_ports) { 120 135 /* Internal ports */ 121 - if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) { 136 + if (portno == 137 + sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) || 138 + portno == 139 + sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1)) { 122 140 /* Equals 1.25G */ 123 141 return SPX5_CAL_SPEED_2G5; 124 - } else if (portno == SPX5_PORT_VD0) { 142 + } else if (portno == 143 + sparx5_get_internal_port(sparx5, SPX5_PORT_VD0)) { 125 144 /* IPMC only idle BW */ 126 145 return SPX5_CAL_SPEED_NONE; 127 - } else if (portno == SPX5_PORT_VD1) { 146 + } else if (portno == 147 + sparx5_get_internal_port(sparx5, SPX5_PORT_VD1)) { 128 148 /* OAM only idle BW */ 129 149 return SPX5_CAL_SPEED_NONE; 130 - } else if (portno == SPX5_PORT_VD2) { 150 + } else if (portno == 151 + sparx5_get_internal_port(sparx5, SPX5_PORT_VD2)) { 131 152 /* IPinIP gets only idle BW */ 132 153 return SPX5_CAL_SPEED_NONE; 133 154 } ··· 150 159 /* Auto configure the QSYS calendar based on port configuration */ 151 160 int sparx5_config_auto_calendar(struct sparx5 *sparx5) 152 161 { 162 + const struct sparx5_consts *consts = sparx5->data->consts; 153 163 u32 cal[7], value, idx, portno; 154 164 u32 max_core_bw; 155 165 u32 total_bw = 0, used_port_bw = 0; ··· 166 174 } 167 175 168 176 /* Setup the calendar with the bandwidth to each port */ 169 - for (portno = 0; portno < SPX5_PORTS_ALL; portno++) { 177 + for (portno = 0; portno < consts->n_ports_all; portno++) { 170 178 u64 reg, offset, this_bw; 171 179 172 180 spd = sparx5_get_port_cal_speed(sparx5, portno); ··· 174 182 continue; 175 183 176 184 this_bw = sparx5_cal_speed_to_value(spd); 177 - if (portno < SPX5_PORTS) 185 + if (portno < consts->n_ports) 178 186 used_port_bw += this_bw; 179 187 else 180 188 /* Internal ports are granted half the value */ ··· 200 208 } 201 209 202 210 /* Halt the calendar while changing it */ 203 - spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), 204 - QSYS_CAL_CTRL_CAL_MODE, 205 - sparx5, QSYS_CAL_CTRL); 211 + if (is_sparx5(sparx5)) 212 + spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), 213 + QSYS_CAL_CTRL_CAL_MODE, 214 + sparx5, QSYS_CAL_CTRL); 206 215 207 216 /* Assign port bandwidth to auto calendar */ 208 - for (idx = 0; idx < ARRAY_SIZE(cal); idx++) 217 + for (idx = 0; idx < consts->n_auto_cals; idx++) 209 218 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); 210 219 211 220 /* Increase grant rate of all ports to account for ··· 271 278 return SPX5_DSM_CAL_EMPTY; 272 279 } 273 280 274 - static int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, 275 - struct sparx5_calendar_data *data) 281 + int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, 282 + struct sparx5_calendar_data *data) 276 283 { 277 284 bool slow_mode; 278 285 u32 gcd, idx, sum, min, factor; ··· 297 304 for (idx = 0; idx < SPX5_DSM_CAL_MAX_DEVS_PER_TAXI; idx++) { 298 305 u32 portno = data->taxi_ports[idx]; 299 306 300 - if (portno < SPX5_TAXI_PORT_MAX) { 307 + if (portno < sparx5->data->consts->n_ports_all) { 301 308 data->taxi_speeds[idx] = sparx5_cal_speed_to_value 302 309 (sparx5_get_port_cal_speed(sparx5, portno)); 303 310 } else { ··· 558 565 /* Configure the DSM calendar based on port configuration */ 559 566 int sparx5_config_dsm_calendar(struct sparx5 *sparx5) 560 567 { 568 + const struct sparx5_ops *ops = sparx5->data->ops; 561 569 int taxi; 562 570 struct sparx5_calendar_data *data; 563 571 int err = 0; ··· 567 573 if (!data) 568 574 return -ENOMEM; 569 575 570 - for (taxi = 0; taxi < SPX5_DSM_CAL_TAXIS; ++taxi) { 571 - err = sparx5_dsm_calendar_calc(sparx5, taxi, data); 576 + for (taxi = 0; taxi < sparx5->data->consts->n_dsm_cal_taxis; ++taxi) { 577 + err = ops->dsm_calendar_calc(sparx5, taxi, data); 572 578 if (err) { 573 579 dev_err(sparx5->dev, "DSM calendar calculation failed\n"); 574 580 goto cal_out;
+3 -2
drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c
··· 234 234 struct dcb_app *)) 235 235 { 236 236 struct sparx5_port *port = netdev_priv(dev); 237 + struct sparx5 *sparx5 = port->sparx5; 237 238 struct sparx5_port *port_itr; 238 239 int err, i; 239 240 240 - for (i = 0; i < SPX5_PORTS; i++) { 241 + for (i = 0; i < sparx5->data->consts->n_ports; i++) { 241 242 port_itr = port->sparx5->ports[i]; 242 243 if (!port_itr) 243 244 continue; ··· 387 386 struct sparx5_port *port; 388 387 int i; 389 388 390 - for (i = 0; i < SPX5_PORTS; i++) { 389 + for (i = 0; i < sparx5->data->consts->n_ports; i++) { 391 390 port = sparx5->ports[i]; 392 391 if (!port) 393 392 continue;
+18 -16
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
··· 505 505 static void sparx5_get_device_stats(struct sparx5 *sparx5, int portno) 506 506 { 507 507 u64 *portstats = &sparx5->stats[portno * sparx5->num_stats]; 508 - u32 tinst = sparx5_port_dev_index(portno); 509 - u32 dev = sparx5_to_high_dev(portno); 508 + u32 tinst = sparx5_port_dev_index(sparx5, portno); 509 + u32 dev = sparx5_to_high_dev(sparx5, portno); 510 510 void __iomem *inst; 511 511 512 512 inst = spx5_inst_get(sparx5, dev, tinst); ··· 819 819 820 820 portstats = &sparx5->stats[portno * sparx5->num_stats]; 821 821 if (sparx5_is_baser(port->conf.portmode)) { 822 - u32 tinst = sparx5_port_dev_index(portno); 823 - u32 dev = sparx5_to_high_dev(portno); 822 + u32 tinst = sparx5_port_dev_index(sparx5, portno); 823 + u32 dev = sparx5_to_high_dev(sparx5, portno); 824 824 825 825 inst = spx5_inst_get(sparx5, dev, tinst); 826 826 sparx5_get_dev_phy_stats(portstats, inst, tinst); ··· 844 844 845 845 portstats = &sparx5->stats[portno * sparx5->num_stats]; 846 846 if (sparx5_is_baser(port->conf.portmode)) { 847 - u32 tinst = sparx5_port_dev_index(portno); 848 - u32 dev = sparx5_to_high_dev(portno); 847 + u32 tinst = sparx5_port_dev_index(sparx5, portno); 848 + u32 dev = sparx5_to_high_dev(sparx5, portno); 849 849 850 850 inst = spx5_inst_get(sparx5, dev, tinst); 851 851 sparx5_get_dev_mac_stats(portstats, inst, tinst); ··· 912 912 913 913 portstats = &sparx5->stats[portno * sparx5->num_stats]; 914 914 if (sparx5_is_baser(port->conf.portmode)) { 915 - u32 tinst = sparx5_port_dev_index(portno); 916 - u32 dev = sparx5_to_high_dev(portno); 915 + u32 tinst = sparx5_port_dev_index(sparx5, portno); 916 + u32 dev = sparx5_to_high_dev(sparx5, portno); 917 917 918 918 inst = spx5_inst_get(sparx5, dev, tinst); 919 919 sparx5_get_dev_mac_ctrl_stats(portstats, inst, tinst); ··· 944 944 945 945 portstats = &sparx5->stats[portno * sparx5->num_stats]; 946 946 if (sparx5_is_baser(port->conf.portmode)) { 947 - u32 tinst = sparx5_port_dev_index(portno); 948 - u32 dev = sparx5_to_high_dev(portno); 947 + u32 tinst = sparx5_port_dev_index(sparx5, portno); 948 + u32 dev = sparx5_to_high_dev(sparx5, portno); 949 949 950 950 inst = spx5_inst_get(sparx5, dev, tinst); 951 951 sparx5_get_dev_rmon_stats(portstats, inst, tinst); ··· 1027 1027 1028 1028 portstats = &sparx5->stats[portno * sparx5->num_stats]; 1029 1029 if (sparx5_is_baser(port->conf.portmode)) { 1030 - u32 tinst = sparx5_port_dev_index(portno); 1031 - u32 dev = sparx5_to_high_dev(portno); 1030 + u32 tinst = sparx5_port_dev_index(sparx5, portno); 1031 + u32 dev = sparx5_to_high_dev(sparx5, portno); 1032 1032 1033 1033 inst = spx5_inst_get(sparx5, dev, tinst); 1034 1034 sparx5_get_dev_misc_stats(portstats, inst, tinst); ··· 1122 1122 { 1123 1123 int idx; 1124 1124 1125 - for (idx = 0; idx < SPX5_PORTS; idx++) 1125 + for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) 1126 1126 if (sparx5->ports[idx]) 1127 1127 sparx5_update_port_stats(sparx5, idx); 1128 1128 } ··· 1189 1189 struct sparx5 *sparx5 = port->sparx5; 1190 1190 struct sparx5_phc *phc; 1191 1191 1192 - if (!sparx5->ptp) 1192 + if (!sparx5->ptp && is_sparx5(sparx5)) 1193 1193 return ethtool_op_get_ts_info(dev, info); 1194 1194 1195 1195 phc = &sparx5->phc[SPARX5_PHC_PORT]; ··· 1228 1228 1229 1229 int sparx_stats_init(struct sparx5 *sparx5) 1230 1230 { 1231 + const struct sparx5_consts *consts = sparx5->data->consts; 1231 1232 char queue_name[32]; 1232 1233 int portno; 1233 1234 ··· 1236 1235 sparx5->num_stats = spx5_stats_count; 1237 1236 sparx5->num_ethtool_stats = ARRAY_SIZE(sparx5_stats_layout); 1238 1237 sparx5->stats = devm_kcalloc(sparx5->dev, 1239 - SPX5_PORTS_ALL * sparx5->num_stats, 1238 + consts->n_ports_all * 1239 + sparx5->num_stats, 1240 1240 sizeof(u64), GFP_KERNEL); 1241 1241 if (!sparx5->stats) 1242 1242 return -ENOMEM; 1243 1243 1244 1244 mutex_init(&sparx5->queue_stats_lock); 1245 1245 sparx5_config_stats(sparx5); 1246 - for (portno = 0; portno < SPX5_PORTS; portno++) 1246 + for (portno = 0; portno < consts->n_ports; portno++) 1247 1247 if (sparx5->ports[portno]) 1248 1248 sparx5_config_port_stats(sparx5, portno); 1249 1249
+7 -3
drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c
··· 156 156 /* Now do the normal processing of the skb */ 157 157 sparx5_ifh_parse((u32 *)skb->data, &fi); 158 158 /* Map to port netdev */ 159 - port = fi.src_port < SPX5_PORTS ? sparx5->ports[fi.src_port] : NULL; 159 + port = fi.src_port < sparx5->data->consts->n_ports ? 160 + sparx5->ports[fi.src_port] : 161 + NULL; 160 162 if (!port || !port->ndev) { 161 163 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); 162 164 sparx5_xtr_flush(sparx5, XTR_QUEUE); ··· 298 296 fdma->ops.dataptr_cb = &sparx5_fdma_rx_dataptr_cb; 299 297 fdma->ops.nextptr_cb = &fdma_nextptr_cb; 300 298 /* Fetch a netdev for SKB and NAPI use, any will do */ 301 - for (idx = 0; idx < SPX5_PORTS; ++idx) { 299 + for (idx = 0; idx < sparx5->data->consts->n_ports; ++idx) { 302 300 struct sparx5_port *port = sparx5->ports[idx]; 303 301 304 302 if (port && port->ndev) { ··· 364 362 sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); 365 363 366 364 /* CPU ports capture setup */ 367 - for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) { 365 + for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); 366 + portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); 367 + portno++) { 368 368 /* ASM CPU port: No preamble, IFH, enable padding */ 369 369 spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) | 370 370 ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |
+6 -4
drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c
··· 80 80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, 81 81 const unsigned char mac[ETH_ALEN], u16 vid) 82 82 { 83 + const struct sparx5_consts *consts = sparx5->data->consts; 83 84 int addr, type, ret; 84 85 85 - if (pgid < SPX5_PORTS) { 86 + if (pgid < consts->n_ports) { 86 87 type = MAC_ENTRY_ADDR_TYPE_UPSID_PN; 87 88 addr = pgid % 32; 88 89 addr += (pgid / 32) << 5; /* Add upsid */ 89 90 } else { 90 91 type = MAC_ENTRY_ADDR_TYPE_MC_IDX; 91 - addr = pgid - SPX5_PORTS; 92 + addr = pgid - consts->n_ports; 92 93 } 93 94 94 95 mutex_lock(&sparx5->lock); ··· 129 128 struct sparx5_port *port = netdev_priv(dev); 130 129 struct sparx5 *sparx5 = port->sparx5; 131 130 132 - return sparx5_mact_learn(sparx5, PGID_CPU, addr, port->pvid); 131 + return sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), 132 + addr, port->pvid); 133 133 } 134 134 135 135 static int sparx5_mact_get(struct sparx5 *sparx5, ··· 373 371 return; 374 372 375 373 port = LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(cfg2); 376 - if (port >= SPX5_PORTS) 374 + if (port >= sparx5->data->consts->n_ports) 377 375 return; 378 376 379 377 if (!test_bit(port, sparx5->bridge_mask))
+160 -68
drivers/net/ethernet/microchip/sparx5/sparx5_main.c
··· 29 29 #include "sparx5_port.h" 30 30 #include "sparx5_qos.h" 31 31 32 - #define QLIM_WM(fraction) \ 33 - ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) 32 + const struct sparx5_regs *regs; 33 + 34 34 #define IO_RANGES 3 35 35 36 36 struct initial_port_config { ··· 43 43 struct sparx5_ram_config { 44 44 void __iomem *init_reg; 45 45 u32 init_val; 46 - }; 47 - 48 - struct sparx5_main_io_resource { 49 - enum sparx5_target id; 50 - phys_addr_t offset; 51 - int range; 52 46 }; 53 47 54 48 static const struct sparx5_main_io_resource sparx5_main_iomap[] = { ··· 208 214 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 209 215 }; 210 216 217 + bool is_sparx5(struct sparx5 *sparx5) 218 + { 219 + switch (sparx5->target_ct) { 220 + case SPX5_TARGET_CT_7546: 221 + case SPX5_TARGET_CT_7549: 222 + case SPX5_TARGET_CT_7552: 223 + case SPX5_TARGET_CT_7556: 224 + case SPX5_TARGET_CT_7558: 225 + case SPX5_TARGET_CT_7546TSN: 226 + case SPX5_TARGET_CT_7549TSN: 227 + case SPX5_TARGET_CT_7552TSN: 228 + case SPX5_TARGET_CT_7556TSN: 229 + case SPX5_TARGET_CT_7558TSN: 230 + return true; 231 + default: 232 + return false; 233 + } 234 + } 235 + 211 236 static int sparx5_create_targets(struct sparx5 *sparx5) 212 237 { 238 + const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; 239 + int iomap_size = sparx5->data->iomap_size; 240 + int ioranges = sparx5->data->ioranges; 213 241 struct resource *iores[IO_RANGES]; 214 242 void __iomem *iomem[IO_RANGES]; 215 243 void __iomem *begin[IO_RANGES]; 216 244 int range_id[IO_RANGES]; 217 245 int idx, jdx; 218 246 219 - for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 220 - const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 247 + for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) { 248 + const struct sparx5_main_io_resource *io = &iomap[jdx]; 221 249 222 - if (idx == iomap->range) { 250 + if (idx == io->range) { 223 251 range_id[idx] = jdx; 224 252 idx++; 225 253 } 226 254 } 227 - for (idx = 0; idx < IO_RANGES; idx++) { 255 + for (idx = 0; idx < ioranges; idx++) { 228 256 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 229 257 idx); 230 258 if (!iores[idx]) { ··· 261 245 iores[idx]->name); 262 246 return -ENOMEM; 263 247 } 264 - begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; 248 + begin[idx] = iomem[idx] - iomap[range_id[idx]].offset; 265 249 } 266 - for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 267 - const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 250 + for (jdx = 0; jdx < iomap_size; jdx++) { 251 + const struct sparx5_main_io_resource *io = &iomap[jdx]; 268 252 269 - sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; 253 + sparx5->regs[io->id] = begin[io->range] + io->offset; 270 254 } 271 255 return 0; 272 256 } ··· 481 465 return -ENODEV; 482 466 } 483 467 484 - switch (freq) { 485 - case SPX5_CORE_CLOCK_250MHZ: 486 - clk_div = 10; 487 - pol_upd_int = 312; 488 - break; 489 - case SPX5_CORE_CLOCK_500MHZ: 490 - clk_div = 5; 491 - pol_upd_int = 624; 492 - break; 493 - case SPX5_CORE_CLOCK_625MHZ: 494 - clk_div = 4; 495 - pol_upd_int = 780; 496 - break; 497 - default: 498 - dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", 499 - sparx5->coreclock, sparx5->target_ct); 500 - return -EINVAL; 468 + if (is_sparx5(sparx5)) { 469 + switch (freq) { 470 + case SPX5_CORE_CLOCK_250MHZ: 471 + clk_div = 10; 472 + pol_upd_int = 312; 473 + break; 474 + case SPX5_CORE_CLOCK_500MHZ: 475 + clk_div = 5; 476 + pol_upd_int = 624; 477 + break; 478 + case SPX5_CORE_CLOCK_625MHZ: 479 + clk_div = 4; 480 + pol_upd_int = 780; 481 + break; 482 + default: 483 + dev_err(sparx5->dev, 484 + "%d coreclock not supported on (%#04x)\n", 485 + sparx5->coreclock, sparx5->target_ct); 486 + return -EINVAL; 487 + } 488 + 489 + /* Configure the LCPLL */ 490 + spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 491 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 492 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 493 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 494 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 495 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 496 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 497 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 498 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 499 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 500 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 501 + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 502 + sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); 501 503 } 502 504 503 505 /* Update state with chosen frequency */ 504 506 sparx5->coreclock = freq; 505 - 506 - /* Configure the LCPLL */ 507 - spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 508 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 509 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 510 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 511 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 512 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 513 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 514 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 515 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 516 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 517 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 518 - CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 519 - sparx5, 520 - CLKGEN_LCPLL1_CORE_CLK_CFG); 521 - 522 507 clk_period = sparx5_clk_period(freq); 523 508 524 509 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), ··· 542 525 sparx5, 543 526 LRN_AUTOAGE_CFG_1); 544 527 545 - for (idx = 0; idx < 3; idx++) 528 + for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) 546 529 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 547 530 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 548 531 sparx5, ··· 562 545 return 0; 563 546 } 564 547 548 + static u32 qlim_wm(struct sparx5 *sparx5, int fraction) 549 + { 550 + return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) * 551 + fraction / 100; 552 + } 553 + 565 554 static int sparx5_qlim_set(struct sparx5 *sparx5) 566 555 { 556 + const struct sparx5_consts *consts = sparx5->data->consts; 567 557 u32 res, dp, prio; 568 558 569 559 for (res = 0; res < 2; res++) { 570 560 for (prio = 0; prio < 8; prio++) 571 561 spx5_wr(0xFFF, sparx5, 572 - QRES_RES_CFG(prio + 630 + res * 1024)); 562 + QRES_RES_CFG(prio + 563 + consts->qres_max_prio_idx + 564 + res * 1024)); 573 565 574 566 for (dp = 0; dp < 4; dp++) 575 567 spx5_wr(0xFFF, sparx5, 576 - QRES_RES_CFG(dp + 638 + res * 1024)); 568 + QRES_RES_CFG(dp + 569 + consts->qres_max_colour_idx + 570 + res * 1024)); 577 571 } 578 572 579 573 /* Set 80,90,95,100% of memory size for top watermarks */ 580 - spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 581 - spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 582 - spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 583 - spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 574 + spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 575 + spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 576 + spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 577 + spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 584 578 585 579 return 0; 586 580 } ··· 613 585 GCB_HW_SGPIO_SD_CFG); 614 586 615 587 /* Refer to LOS SGPIO */ 616 - for (idx = 0; idx < SPX5_PORTS; idx++) 588 + for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) 617 589 if (sparx5->ports[idx]) 618 590 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 619 591 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, ··· 624 596 static int sparx5_start(struct sparx5 *sparx5) 625 597 { 626 598 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 599 + const struct sparx5_consts *consts = sparx5->data->consts; 600 + const struct sparx5_ops *ops = sparx5->data->ops; 627 601 char queue_name[32]; 628 602 u32 idx; 629 603 int err; 630 604 631 605 /* Setup own UPSIDs */ 632 - for (idx = 0; idx < 3; idx++) { 606 + for (idx = 0; idx < consts->n_own_upsids; idx++) { 633 607 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 634 608 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 635 609 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); ··· 639 609 } 640 610 641 611 /* Enable CPU ports */ 642 - for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) 612 + for (idx = consts->n_ports; idx < consts->n_ports_all; idx++) 643 613 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 644 614 QFWD_SWITCH_PORT_MODE_PORT_ENA, 645 615 sparx5, ··· 649 619 sparx5_update_fwd(sparx5); 650 620 651 621 /* CPU copy CPU pgids */ 652 - spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 653 - sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); 654 - spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 655 - sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); 622 + spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, 623 + ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); 624 + spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, 625 + ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST))); 656 626 657 627 /* Recalc injected frame FCS */ 658 - for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) 628 + for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); 629 + idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++) 659 630 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 660 631 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 661 632 sparx5, ANA_CL_FILTER_CTRL(idx)); ··· 671 640 sparx5_vlan_init(sparx5); 672 641 673 642 /* Add host mode BC address (points only to CPU) */ 674 - sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); 643 + sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast, 644 + NULL_VID); 675 645 676 646 /* Enable queue limitation watermarks */ 677 647 sparx5_qlim_set(sparx5); ··· 752 720 753 721 if (sparx5->ptp_irq >= 0) { 754 722 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, 755 - NULL, sparx5_ptp_irq_handler, 723 + NULL, ops->ptp_irq_handler, 756 724 IRQF_ONESHOT, "sparx5-ptp", 757 725 sparx5); 758 726 if (err) ··· 790 758 sparx5->pdev = pdev; 791 759 sparx5->dev = &pdev->dev; 792 760 spin_lock_init(&sparx5->tx_lock); 761 + 762 + sparx5->data = device_get_match_data(sparx5->dev); 763 + if (!sparx5->data) 764 + return -EINVAL; 765 + 766 + regs = sparx5->data->regs; 793 767 794 768 /* Do switch core reset if available */ 795 769 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); ··· 975 937 destroy_workqueue(sparx5->mact_queue); 976 938 } 977 939 940 + static const struct sparx5_regs sparx5_regs = { 941 + .tsize = sparx5_tsize, 942 + .gaddr = sparx5_gaddr, 943 + .gcnt = sparx5_gcnt, 944 + .gsize = sparx5_gsize, 945 + .raddr = sparx5_raddr, 946 + .rcnt = sparx5_rcnt, 947 + .fpos = sparx5_fpos, 948 + .fsize = sparx5_fsize, 949 + }; 950 + 951 + static const struct sparx5_consts sparx5_consts = { 952 + .n_ports = 65, 953 + .n_ports_all = 70, 954 + .n_hsch_l1_elems = 64, 955 + .n_hsch_queues = 8, 956 + .n_lb_groups = 10, 957 + .n_pgids = 2113, /* (2048 + n_ports) */ 958 + .n_sio_clks = 3, 959 + .n_own_upsids = 3, 960 + .n_auto_cals = 7, 961 + .n_filters = 1024, 962 + .n_gates = 1024, 963 + .n_sdlbs = 4096, 964 + .n_dsm_cal_taxis = 8, 965 + .buf_size = 4194280, 966 + .qres_max_prio_idx = 630, 967 + .qres_max_colour_idx = 638, 968 + .tod_pin = 4, 969 + }; 970 + 971 + static const struct sparx5_ops sparx5_ops = { 972 + .is_port_2g5 = &sparx5_port_is_2g5, 973 + .is_port_5g = &sparx5_port_is_5g, 974 + .is_port_10g = &sparx5_port_is_10g, 975 + .is_port_25g = &sparx5_port_is_25g, 976 + .get_port_dev_index = &sparx5_port_dev_mapping, 977 + .get_port_dev_bit = &sparx5_port_dev_mapping, 978 + .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, 979 + .get_sdlb_group = &sparx5_get_sdlb_group, 980 + .set_port_mux = &sparx5_port_mux_set, 981 + .ptp_irq_handler = &sparx5_ptp_irq_handler, 982 + .dsm_calendar_calc = &sparx5_dsm_calendar_calc, 983 + }; 984 + 985 + static const struct sparx5_match_data sparx5_desc = { 986 + .iomap = sparx5_main_iomap, 987 + .iomap_size = ARRAY_SIZE(sparx5_main_iomap), 988 + .ioranges = 3, 989 + .regs = &sparx5_regs, 990 + .consts = &sparx5_consts, 991 + .ops = &sparx5_ops, 992 + }; 993 + 978 994 static const struct of_device_id mchp_sparx5_match[] = { 979 - { .compatible = "microchip,sparx5-switch" }, 995 + { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, 980 996 { } 981 997 }; 982 998 MODULE_DEVICE_TABLE(of, mchp_sparx5_match);
+110 -18
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
··· 52 52 }; 53 53 54 54 #define SPX5_PORTS 65 55 - #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 56 - #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 57 - #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 58 - #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 59 - #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 60 - #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 61 - #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 55 + #define SPX5_PORTS_ALL 70 /* Total number of ports */ 62 56 63 - #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 64 - #define PGID_UC_FLOOD (PGID_BASE + 0) 65 - #define PGID_MC_FLOOD (PGID_BASE + 1) 66 - #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 67 - #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 68 - #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 69 - #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 70 - #define PGID_BCAST (PGID_BASE + 6) 71 - #define PGID_CPU (PGID_BASE + 7) 72 - #define PGID_MCAST_START (PGID_BASE + 8) 57 + #define SPX5_PORT_CPU_0 0 /* CPU Port 0 */ 58 + #define SPX5_PORT_CPU_1 1 /* CPU Port 1 */ 59 + #define SPX5_PORT_VD0 2 /* VD0/Port used for IPMC */ 60 + #define SPX5_PORT_VD1 3 /* VD1/Port used for AFI/OAM */ 61 + #define SPX5_PORT_VD2 4 /* VD2/Port used for IPinIP*/ 62 + 63 + #define PGID_UC_FLOOD 0 64 + #define PGID_MC_FLOOD 1 65 + #define PGID_IPV4_MC_DATA 2 66 + #define PGID_IPV4_MC_CTRL 3 67 + #define PGID_IPV6_MC_DATA 4 68 + #define PGID_IPV6_MC_CTRL 5 69 + #define PGID_BCAST 6 70 + #define PGID_CPU 7 71 + #define PGID_MCAST_START 8 73 72 74 73 #define PGID_TABLE_SIZE 3290 75 74 ··· 99 100 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 100 101 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 101 102 103 + #define SPX5_DSM_CAL_LEN 64 104 + #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 105 + 102 106 struct sparx5; 107 + 108 + struct sparx5_calendar_data { 109 + u32 schedule[SPX5_DSM_CAL_LEN]; 110 + u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 111 + u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 112 + u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 113 + u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 114 + u32 new_slots[SPX5_DSM_CAL_LEN]; 115 + u32 temp_sched[SPX5_DSM_CAL_LEN]; 116 + u32 indices[SPX5_DSM_CAL_LEN]; 117 + u32 short_list[SPX5_DSM_CAL_LEN]; 118 + u32 long_list[SPX5_DSM_CAL_LEN]; 119 + }; 103 120 104 121 /* Frame DMA receive state: 105 122 * For each DB, there is a SKB, and the skb data pointer is mapped in ··· 241 226 #define SPARX5_SKB_CB(skb) \ 242 227 ((struct sparx5_skb_cb *)((skb)->cb)) 243 228 229 + struct sparx5_regs { 230 + const unsigned int *tsize; 231 + const unsigned int *gaddr; 232 + const unsigned int *gcnt; 233 + const unsigned int *gsize; 234 + const unsigned int *raddr; 235 + const unsigned int *rcnt; 236 + const unsigned int *fpos; 237 + const unsigned int *fsize; 238 + }; 239 + 240 + struct sparx5_consts { 241 + u32 n_ports; /* Number of front ports */ 242 + u32 n_ports_all; /* Number of front ports + internal ports */ 243 + u32 n_hsch_l1_elems; /* Number of HSCH layer 1 elements */ 244 + u32 n_hsch_queues; /* Number of HSCH queues */ 245 + u32 n_lb_groups; /* Number of leacky bucket groupd */ 246 + u32 n_pgids; /* Number of PGID's */ 247 + u32 n_sio_clks; /* Number of serial IO clocks */ 248 + u32 n_own_upsids; /* Number of own UPSID's */ 249 + u32 n_auto_cals; /* Number of auto calendars */ 250 + u32 n_filters; /* Number of PSFP filters */ 251 + u32 n_gates; /* Number of PSFP gates */ 252 + u32 n_sdlbs; /* Number of service dual leaky buckets */ 253 + u32 n_dsm_cal_taxis; /* Number of DSM calendar taxis */ 254 + u32 buf_size; /* Amount of QLIM watermark memory */ 255 + u32 qres_max_prio_idx; /* Maximum QRES prio index */ 256 + u32 qres_max_colour_idx; /* Maximum QRES colour index */ 257 + u32 tod_pin; /* PTP TOD pin */ 258 + }; 259 + 260 + struct sparx5_ops { 261 + bool (*is_port_2g5)(int portno); 262 + bool (*is_port_5g)(int portno); 263 + bool (*is_port_10g)(int portno); 264 + bool (*is_port_25g)(int portno); 265 + u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); 266 + u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); 267 + u32 (*get_hsch_max_group_rate)(int grp); 268 + struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); 269 + int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, 270 + struct sparx5_port_config *conf); 271 + 272 + irqreturn_t (*ptp_irq_handler)(int irq, void *args); 273 + int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, 274 + struct sparx5_calendar_data *data); 275 + }; 276 + 277 + struct sparx5_main_io_resource { 278 + enum sparx5_target id; 279 + phys_addr_t offset; 280 + int range; 281 + }; 282 + 283 + struct sparx5_match_data { 284 + const struct sparx5_regs *regs; 285 + const struct sparx5_consts *consts; 286 + const struct sparx5_ops *ops; 287 + const struct sparx5_main_io_resource *iomap; 288 + int ioranges; 289 + int iomap_size; 290 + }; 291 + 244 292 struct sparx5 { 245 293 struct platform_device *pdev; 246 294 struct device *dev; ··· 371 293 struct list_head mall_entries; 372 294 /* Common root for debugfs */ 373 295 struct dentry *debugfs_root; 296 + const struct sparx5_match_data *data; 374 297 }; 298 + 299 + /* sparx5_main.c */ 300 + bool is_sparx5(struct sparx5 *sparx5); 375 301 376 302 /* sparx5_switchdev.c */ 377 303 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); ··· 437 355 /* sparx5_calendar.c */ 438 356 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 439 357 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 358 + int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, 359 + struct sparx5_calendar_data *data); 360 + 440 361 441 362 /* sparx5_ethtool.c */ 442 363 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); ··· 460 375 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 461 376 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 462 377 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 463 - void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 378 + void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); 464 379 bool sparx5_netdevice_check(const struct net_device *dev); 465 380 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 466 381 int sparx5_register_netdevs(struct sparx5 *sparx5); ··· 498 413 void sparx5_pgid_init(struct sparx5 *spx5); 499 414 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 500 415 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 416 + int sparx5_get_pgid(struct sparx5 *sparx5, int pgid); 501 417 502 418 /* sparx5_pool.c */ 503 419 struct sparx5_pool_entry { ··· 511 425 int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id); 512 426 int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, 513 427 u32 *id); 428 + 429 + /* sparx5_port.c */ 430 + int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, 431 + struct sparx5_port_config *conf); 432 + int sparx5_get_internal_port(struct sparx5 *sparx5, int port); 514 433 515 434 /* sparx5_sdlb.c */ 516 435 #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF ··· 535 444 }; 536 445 537 446 extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; 447 + struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx); 538 448 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, 539 449 u64 rate); 540 450
+2511 -1948
drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0+ 2 2 * Microchip Sparx5 Switch driver 3 3 * 4 - * Copyright (c) 2021 Microchip Technology Inc. 4 + * Copyright (c) 2024 Microchip Technology Inc. 5 5 */ 6 6 7 - /* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100. 8 - * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada 7 + /* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200. 8 + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b 9 9 */ 10 10 11 11 #ifndef _SPARX5_MAIN_REGS_H_ ··· 14 14 #include <linux/bitfield.h> 15 15 #include <linux/types.h> 16 16 #include <linux/bug.h> 17 + 18 + #include "sparx5_regs.h" 17 19 18 20 enum sparx5_target { 19 21 TARGET_ANA_AC = 1, ··· 54 52 TARGET_VCAP_SUPER = 326, 55 53 TARGET_VOP = 327, 56 54 TARGET_XQS = 331, 57 - NUM_TARGETS = 332 55 + NUM_TARGETS = 517 58 56 }; 57 + 58 + /* sparx5_main.c 59 + * 60 + * This is used by the register macros to access chip differences (if any) in: 61 + * target size, register address, register count, group address, group count, 62 + * group size, field position and field size. 63 + */ 64 + extern const struct sparx5_regs *regs; 65 + 66 + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ 67 + #define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 68 + #define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 59 69 60 70 #define __REG(...) __VA_ARGS__ 61 71 62 - /* ANA_AC:RAM_CTRL:RAM_INIT */ 63 - #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC,\ 64 - 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) 72 + /* ANA_AC:RAM_CTRL:RAM_INIT */ 73 + #define ANA_AC_RAM_INIT \ 74 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\ 75 + 0, 1, 4) 65 76 66 77 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) 67 78 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ ··· 88 73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 89 74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 90 75 91 - /* ANA_AC:PS_COMMON:OWN_UPSID */ 92 - #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC,\ 93 - 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) 76 + /* ANA_AC:PS_COMMON:OWN_UPSID */ 77 + #define ANA_AC_OWN_UPSID(r) \ 78 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\ 79 + 52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4) 94 80 95 81 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 96 82 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ ··· 99 83 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ 100 84 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) 101 85 102 - /* ANA_AC:MIRROR_PROBE:PROBE_CFG */ 103 - #define ANA_AC_PROBE_CFG(g) \ 104 - __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4) 86 + /* ANA_AC:MIRROR_PROBE:PROBE_CFG */ 87 + #define ANA_AC_PROBE_CFG(g) \ 88 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 89 + 32, 0, 0, 1, 4) 105 90 106 - #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) 91 + #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) 107 92 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ 108 93 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 109 94 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ 110 95 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 111 96 112 - #define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) 97 + #define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) 113 98 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ 114 99 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 115 100 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ 116 101 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 117 102 118 - #define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) 103 + #define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) 119 104 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ 120 105 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x) 121 106 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ 122 107 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x) 123 108 124 - #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) 109 + #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) 125 110 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ 126 111 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 127 112 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ 128 113 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 129 114 130 - #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) 115 + #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) 131 116 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ 132 117 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 133 118 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ 134 119 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 135 120 136 - #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) 121 + #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) 137 122 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ 138 123 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 139 124 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ 140 125 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 141 126 142 - /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ 143 - #define ANA_AC_PROBE_PORT_CFG(g) \ 144 - __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4) 127 + /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ 128 + #define ANA_AC_PROBE_PORT_CFG(g) \ 129 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 130 + 32, 8, 0, 1, 4) 145 131 146 - /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ 147 - #define ANA_AC_PROBE_PORT_CFG1(g) \ 148 - __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4) 132 + /* SPARX5 ONLY */ 133 + /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ 134 + #define ANA_AC_PROBE_PORT_CFG1(g) \ 135 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 136 + 32, 12, 0, 1, 4) 149 137 150 - /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ 151 - #define ANA_AC_PROBE_PORT_CFG2(g) \ 152 - __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4) 138 + /* SPARX5 ONLY */ 139 + /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ 140 + #define ANA_AC_PROBE_PORT_CFG2(g) \ 141 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 142 + 32, 16, 0, 1, 4) 153 143 154 - #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) 144 + #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) 155 145 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ 156 146 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 157 147 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ 158 148 FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 159 149 160 - /* ANA_AC:SRC:SRC_CFG */ 161 - #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ 162 - 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) 150 + /* ANA_AC:SRC:SRC_CFG */ 151 + #define ANA_AC_SRC_CFG(g) \ 152 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 153 + regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4) 163 154 164 - /* ANA_AC:SRC:SRC_CFG1 */ 165 - #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ 166 - 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) 155 + /* SPARX5 ONLY */ 156 + /* ANA_AC:SRC:SRC_CFG1 */ 157 + #define ANA_AC_SRC_CFG1(g) \ 158 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 159 + regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4) 167 160 168 - /* ANA_AC:SRC:SRC_CFG2 */ 169 - #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ 170 - 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) 161 + /* SPARX5 ONLY */ 162 + /* ANA_AC:SRC:SRC_CFG2 */ 163 + #define ANA_AC_SRC_CFG2(g) \ 164 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 165 + regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4) 171 166 172 167 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) 173 168 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ ··· 186 159 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ 187 160 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) 188 161 189 - /* ANA_AC:PGID:PGID_CFG */ 190 - #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ 191 - 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) 162 + /* ANA_AC:PGID:PGID_CFG */ 163 + #define ANA_AC_PGID_CFG(g) \ 164 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 165 + regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4) 192 166 193 - /* ANA_AC:PGID:PGID_CFG1 */ 194 - #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ 195 - 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) 167 + /* SPARX5 ONLY */ 168 + /* ANA_AC:PGID:PGID_CFG1 */ 169 + #define ANA_AC_PGID_CFG1(g) \ 170 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 171 + regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4) 196 172 197 - /* ANA_AC:PGID:PGID_CFG2 */ 198 - #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ 199 - 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) 173 + /* SPARX5 ONLY */ 174 + /* ANA_AC:PGID:PGID_CFG2 */ 175 + #define ANA_AC_PGID_CFG2(g) \ 176 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 177 + regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4) 200 178 201 179 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) 202 180 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ ··· 209 177 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ 210 178 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) 211 179 212 - /* ANA_AC:PGID:PGID_MISC_CFG */ 213 - #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ 214 - 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) 180 + /* ANA_AC:PGID:PGID_MISC_CFG */ 181 + #define ANA_AC_PGID_MISC_CFG(g) \ 182 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 183 + regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4) 215 184 216 185 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) 217 186 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ ··· 232 199 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ 233 200 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 234 201 235 - /* ANA_AC:TSN_SF:TSN_SF */ 236 - #define ANA_AC_TSN_SF __REG(TARGET_ANA_AC,\ 237 - 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4) 202 + /* ANA_AC:TSN_SF:TSN_SF */ 203 + #define ANA_AC_TSN_SF \ 204 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0, \ 205 + 0, 1, 4) 238 206 239 207 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) 240 208 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ ··· 243 209 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ 244 210 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 245 211 246 - #define ANA_AC_TSN_SF_PORT_NUM GENMASK(8, 0) 212 + #define ANA_AC_TSN_SF_PORT_NUM\ 213 + GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0) 247 214 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ 248 - FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x) 215 + spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x) 249 216 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ 250 - FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x) 217 + spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x) 251 218 252 - /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ 253 - #define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\ 254 - 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4) 219 + /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ 220 + #define ANA_AC_TSN_SF_CFG(g) \ 221 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g, \ 222 + regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4) 255 223 256 - #define ANA_AC_TSN_SF_CFG_TSN_SGID GENMASK(25, 16) 224 + #define ANA_AC_TSN_SF_CFG_TSN_SGID\ 225 + GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16) 257 226 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ 258 - FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 227 + spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 259 228 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ 260 - FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 229 + spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 261 230 262 231 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) 263 232 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ ··· 280 243 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ 281 244 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 282 245 283 - /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ 284 - #define ANA_AC_TSN_SF_STATUS __REG(TARGET_ANA_AC,\ 285 - 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4) 246 + /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ 247 + #define ANA_AC_TSN_SF_STATUS \ 248 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \ 249 + 16, 0, 0, 1, 4) 286 250 287 251 #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) 288 252 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ ··· 297 259 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ 298 260 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 299 261 300 - #define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1) 262 + #define ANA_AC_TSN_SF_STATUS_TSN_SFID\ 263 + GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1) 301 264 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ 302 - FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 265 + spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 303 266 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ 304 - FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 267 + spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 305 268 306 269 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) 307 270 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ ··· 310 271 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ 311 272 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 312 273 313 - /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ 314 - #define ANA_AC_SG_ACCESS_CTRL __REG(TARGET_ANA_AC,\ 315 - 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4) 274 + /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ 275 + #define ANA_AC_SG_ACCESS_CTRL \ 276 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ 277 + 0, 0, 1, 4) 316 278 317 - #define ANA_AC_SG_ACCESS_CTRL_SGID GENMASK(9, 0) 279 + #define ANA_AC_SG_ACCESS_CTRL_SGID\ 280 + GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0) 318 281 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ 319 - FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x) 282 + spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x) 320 283 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ 321 - FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x) 284 + spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x) 322 285 323 286 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) 324 287 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ ··· 328 287 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ 329 288 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 330 289 331 - /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ 332 - #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD __REG(TARGET_ANA_AC,\ 333 - 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4) 290 + /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ 291 + #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD \ 292 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ 293 + 8, 0, 1, 4) 334 294 335 295 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) 336 296 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ ··· 345 303 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ 346 304 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 347 305 348 - /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ 349 - #define ANA_AC_SG_CONFIG_REG_1 __REG(TARGET_ANA_AC,\ 350 - 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4) 306 + /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ 307 + #define ANA_AC_SG_CONFIG_REG_1 \ 308 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 309 + 48, 0, 1, 4) 351 310 352 - /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ 353 - #define ANA_AC_SG_CONFIG_REG_2 __REG(TARGET_ANA_AC,\ 354 - 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4) 311 + /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ 312 + #define ANA_AC_SG_CONFIG_REG_2 \ 313 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 314 + 52, 0, 1, 4) 355 315 356 - /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ 357 - #define ANA_AC_SG_CONFIG_REG_3 __REG(TARGET_ANA_AC,\ 358 - 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4) 316 + /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ 317 + #define ANA_AC_SG_CONFIG_REG_3 \ 318 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 319 + 56, 0, 1, 4) 359 320 360 321 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) 361 322 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ ··· 414 369 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ 415 370 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 416 371 417 - /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ 418 - #define ANA_AC_SG_CONFIG_REG_4 __REG(TARGET_ANA_AC,\ 419 - 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4) 372 + /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ 373 + #define ANA_AC_SG_CONFIG_REG_4 \ 374 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 375 + 60, 0, 1, 4) 420 376 421 - /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ 422 - #define ANA_AC_SG_CONFIG_REG_5 __REG(TARGET_ANA_AC,\ 423 - 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4) 377 + /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ 378 + #define ANA_AC_SG_CONFIG_REG_5 \ 379 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 380 + 64, 0, 1, 4) 424 381 425 - /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ 426 - #define ANA_AC_SG_GCL_GS_CONFIG(r) __REG(TARGET_ANA_AC,\ 427 - 0, 1, 851584, 0, 1, 128, 0, r, 4, 4) 382 + /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ 383 + #define ANA_AC_SG_GCL_GS_CONFIG(r) \ 384 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 385 + 0, r, 4, 4) 428 386 429 387 #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) 430 388 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ ··· 441 393 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ 442 394 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 443 395 444 - /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ 445 - #define ANA_AC_SG_GCL_TI_CONFIG(r) __REG(TARGET_ANA_AC,\ 446 - 0, 1, 851584, 0, 1, 128, 16, r, 4, 4) 396 + /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ 397 + #define ANA_AC_SG_GCL_TI_CONFIG(r) \ 398 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 399 + 16, r, 4, 4) 447 400 448 - /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ 449 - #define ANA_AC_SG_GCL_OCT_CONFIG(r) __REG(TARGET_ANA_AC,\ 450 - 0, 1, 851584, 0, 1, 128, 32, r, 4, 4) 401 + /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ 402 + #define ANA_AC_SG_GCL_OCT_CONFIG(r) \ 403 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 404 + 32, r, 4, 4) 451 405 452 - /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ 453 - #define ANA_AC_SG_STATUS_REG_1 __REG(TARGET_ANA_AC,\ 454 - 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4) 406 + /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ 407 + #define ANA_AC_SG_STATUS_REG_1 \ 408 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 409 + 0, 0, 1, 4) 455 410 456 - /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ 457 - #define ANA_AC_SG_STATUS_REG_2 __REG(TARGET_ANA_AC,\ 458 - 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4) 411 + /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ 412 + #define ANA_AC_SG_STATUS_REG_2 \ 413 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 414 + 4, 0, 1, 4) 459 415 460 - /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ 461 - #define ANA_AC_SG_STATUS_REG_3 __REG(TARGET_ANA_AC,\ 462 - 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4) 416 + /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ 417 + #define ANA_AC_SG_STATUS_REG_3 \ 418 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 419 + 8, 0, 1, 4) 463 420 464 421 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) 465 422 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ ··· 496 443 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ 497 444 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 498 445 499 - /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ 500 - #define ANA_AC_SG_STATUS_REG_4 __REG(TARGET_ANA_AC,\ 501 - 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4) 446 + /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ 447 + #define ANA_AC_SG_STATUS_REG_4 \ 448 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 449 + 12, 0, 1, 4) 502 450 503 - /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 504 - #define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC,\ 505 - 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) 451 + /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 452 + #define ANA_AC_PORT_SGE_CFG(r) \ 453 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ 454 + 0, 1, 20, 0, r, 4, 4) 506 455 507 - #define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) 456 + #define ANA_AC_PORT_SGE_CFG_MASK\ 457 + GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0) 508 458 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ 509 - FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) 459 + spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x) 510 460 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ 511 - FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) 461 + spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x) 512 462 513 - /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 514 - #define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC,\ 515 - 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) 463 + /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 464 + #define ANA_AC_STAT_RESET \ 465 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ 466 + 0, 1, 20, 16, 0, 1, 4) 516 467 517 468 #define ANA_AC_STAT_RESET_RESET BIT(0) 518 469 #define ANA_AC_STAT_RESET_RESET_SET(x)\ ··· 524 467 #define ANA_AC_STAT_RESET_RESET_GET(x)\ 525 468 FIELD_GET(ANA_AC_STAT_RESET_RESET, x) 526 469 527 - /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 528 - #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\ 529 - 0, 1, 843776, g, 70, 64, 4, r, 4, 4) 470 + /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 471 + #define ANA_AC_PORT_STAT_CFG(g, r) \ 472 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ 473 + regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4) 530 474 531 475 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) 532 476 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ ··· 547 489 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ 548 490 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 549 491 550 - /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 551 - #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\ 552 - 0, 1, 843776, g, 70, 64, 20, r, 4, 4) 492 + /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 493 + #define ANA_AC_PORT_STAT_LSB_CNT(g, r) \ 494 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ 495 + regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4) 553 496 554 - /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ 555 - #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) __REG(TARGET_ANA_AC,\ 556 - 0, 1, 893792, 0, 1, 24, 0, r, 2, 4) 497 + /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ 498 + #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) \ 499 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 500 + 0, 1, 24, 0, r, 2, 4) 557 501 558 502 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0) 559 503 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ ··· 563 503 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ 564 504 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 565 505 566 - /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ 567 - #define ANA_AC_ACL_STAT_GLOBAL_CFG(r) __REG(TARGET_ANA_AC,\ 568 - 0, 1, 893792, 0, 1, 24, 8, r, 2, 4) 506 + /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ 507 + #define ANA_AC_ACL_STAT_GLOBAL_CFG(r) \ 508 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 509 + 0, 1, 24, 8, r, 2, 4) 569 510 570 511 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0) 571 512 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ ··· 574 513 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ 575 514 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 576 515 577 - /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ 578 - #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) __REG(TARGET_ANA_AC,\ 579 - 0, 1, 893792, 0, 1, 24, 16, r, 2, 4) 516 + /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ 517 + #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) \ 518 + __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 519 + 0, 1, 24, 16, r, 2, 4) 580 520 581 521 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0) 582 522 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ ··· 585 523 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ 586 524 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 587 525 588 - /* ANA_ACL:COMMON:VCAP_S2_CFG */ 589 - #define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL,\ 590 - 0, 1, 32768, 0, 1, 592, 0, r, 70, 4) 526 + /* ANA_ACL:COMMON:VCAP_S2_CFG */ 527 + #define ANA_ACL_VCAP_S2_CFG(r) \ 528 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 529 + 0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4) 591 530 592 531 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) 593 532 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ ··· 674 611 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ 675 612 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 676 613 677 - /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 678 - #define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL,\ 679 - 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4) 614 + /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 615 + #define ANA_ACL_SWAP_IP_CTRL \ 616 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 617 + 412, 0, 1, 4) 680 618 681 619 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) 682 620 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ ··· 709 645 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ 710 646 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 711 647 712 - /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 713 - #define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL,\ 714 - 0, 1, 32768, 0, 1, 592, 424, r, 4, 4) 648 + /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 649 + #define ANA_ACL_VCAP_S2_RLEG_STAT(r) \ 650 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 651 + 424, r, 4, 4) 715 652 716 653 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) 717 654 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ ··· 726 661 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ 727 662 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 728 663 729 - /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 730 - #define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL,\ 731 - 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4) 664 + /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 665 + #define ANA_ACL_VCAP_S2_FRAGMENT_CFG \ 666 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 667 + 440, 0, 1, 4) 732 668 733 669 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) 734 670 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ ··· 749 683 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ 750 684 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 751 685 752 - /* ANA_ACL:COMMON:OWN_UPSID */ 753 - #define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL,\ 754 - 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) 686 + /* ANA_ACL:COMMON:OWN_UPSID */ 687 + #define ANA_ACL_OWN_UPSID(r) \ 688 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 689 + 580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4) 755 690 756 691 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 757 692 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ ··· 760 693 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ 761 694 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 762 695 763 - /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 764 - #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\ 765 - 0, 1, 34200, g, 134, 16, 0, r, 4, 4) 696 + /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 697 + #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) \ 698 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g, \ 699 + regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4) 766 700 767 701 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) 768 702 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ ··· 813 745 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 814 746 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 815 747 816 - /* ANA_ACL:CNT_A:CNT_A */ 817 - #define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\ 818 - 0, 1, 0, g, 4096, 4, 0, 0, 1, 4) 748 + /* ANA_ACL:CNT_A:CNT_A */ 749 + #define ANA_ACL_CNT_A(g) \ 750 + __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0, \ 751 + 0, 1, 4) 819 752 820 - /* ANA_ACL:CNT_B:CNT_B */ 821 - #define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\ 822 - 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4) 753 + /* ANA_ACL:CNT_B:CNT_B */ 754 + #define ANA_ACL_CNT_B(g) \ 755 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g, \ 756 + regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4) 823 757 824 - /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 825 - #define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL,\ 826 - 0, 1, 36408, 0, 1, 16, 0, r, 4, 4) 758 + /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 759 + #define ANA_ACL_SEC_LOOKUP_STICKY(r) \ 760 + __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16, \ 761 + 0, r, 4, 4) 827 762 828 763 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) 829 764 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ ··· 936 865 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 937 866 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 938 867 939 - /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 940 - #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL,\ 941 - 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) 868 + /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 869 + #define ANA_AC_POL_POL_UPD_INT_CFG \ 870 + __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \ 871 + 0, 1, 1160, 1148, 0, 1, 4) 942 872 943 873 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) 944 874 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ ··· 947 875 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ 948 876 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 949 877 950 - /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 951 - #define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ 952 - 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) 878 + /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 879 + #define ANA_AC_POL_BDLB_DLB_CTRL \ 880 + __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \ 881 + 0, 1, 8, 0, 0, 1, 4) 953 882 954 883 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 955 884 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ ··· 976 903 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 977 904 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 978 905 979 - /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 980 - #define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ 981 - 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) 906 + /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 907 + #define ANA_AC_POL_SLB_DLB_CTRL \ 908 + __REG(TARGET_ANA_AC_POL, 0, 1, \ 909 + regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4) 982 910 983 911 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 984 912 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ ··· 1005 931 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 1006 932 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 1007 933 1008 - /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ 1009 - #define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\ 1010 - 0, 1, 295468, g, 10, 24, 0, 0, 1, 4) 934 + /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ 935 + #define ANA_AC_SDLB_XLB_START(g) \ 936 + __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 937 + g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4) 1011 938 1012 - #define ANA_AC_SDLB_XLB_START_LBSET_START GENMASK(12, 0) 939 + #define ANA_AC_SDLB_XLB_START_LBSET_START\ 940 + GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0) 1013 941 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ 1014 - FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x) 942 + spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x) 1015 943 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ 1016 - FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x) 944 + spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x) 1017 945 1018 - /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ 1019 - #define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\ 1020 - 0, 1, 295468, g, 10, 24, 4, 0, 1, 4) 946 + /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ 947 + #define ANA_AC_SDLB_PUP_INTERVAL(g) \ 948 + __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 949 + g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4) 1021 950 1022 951 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) 1023 952 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ ··· 1028 951 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ 1029 952 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 1030 953 1031 - /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ 1032 - #define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\ 1033 - 0, 1, 295468, g, 10, 24, 8, 0, 1, 4) 954 + /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ 955 + #define ANA_AC_SDLB_PUP_CTRL(g) \ 956 + __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 957 + g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4) 1034 958 1035 959 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) 1036 960 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ ··· 1045 967 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ 1046 968 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 1047 969 1048 - /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ 1049 - #define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ 1050 - 0, 1, 295468, g, 10, 24, 12, 0, 1, 4) 970 + /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ 971 + #define ANA_AC_SDLB_LBGRP_MISC(g) \ 972 + __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 973 + g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4) 1051 974 1052 - #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT GENMASK(12, 8) 975 + #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\ 976 + GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8) 1053 977 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ 1054 - FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 978 + spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 1055 979 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ 1056 - FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 980 + spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 1057 981 1058 - /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ 1059 - #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\ 1060 - 0, 1, 295468, g, 10, 24, 16, 0, 1, 4) 982 + /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ 983 + #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ 984 + __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 985 + g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4) 1061 986 1062 987 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) 1063 988 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ ··· 1068 987 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ 1069 988 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 1070 989 1071 - /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ 1072 - #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\ 1073 - 0, 1, 295468, g, 10, 24, 20, 0, 1, 4) 990 + /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ 991 + #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ 992 + __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 993 + g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4) 1074 994 1075 995 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) 1076 996 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ ··· 1085 1003 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ 1086 1004 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1087 1005 1088 - #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16) 1006 + #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\ 1007 + GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16) 1089 1008 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ 1090 - FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1009 + spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1091 1010 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ 1092 - FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1011 + spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1093 1012 1094 - /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ 1095 - #define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\ 1096 - 0, 1, 0, g, 4616, 64, 0, r, 2, 4) 1013 + /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ 1014 + #define ANA_AC_SDLB_PUP_TOKENS(g, r) \ 1015 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1016 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4) 1097 1017 1098 1018 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) 1099 1019 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ ··· 1103 1019 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ 1104 1020 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1105 1021 1106 - /* ANA_AC_SDLB:LBSET_TBL:THRES */ 1107 - #define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\ 1108 - 0, 1, 0, g, 4616, 64, 8, r, 2, 4) 1022 + /* ANA_AC_SDLB:LBSET_TBL:THRES */ 1023 + #define ANA_AC_SDLB_THRES(g, r) \ 1024 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1025 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4) 1109 1026 1110 1027 #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) 1111 1028 #define ANA_AC_SDLB_THRES_THRES_SET(x)\ ··· 1120 1035 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ 1121 1036 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) 1122 1037 1123 - /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ 1124 - #define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\ 1125 - 0, 1, 0, g, 4616, 64, 16, 0, 1, 4) 1038 + /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ 1039 + #define ANA_AC_SDLB_XLB_NEXT(g) \ 1040 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1041 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4) 1126 1042 1127 - #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT GENMASK(12, 0) 1043 + #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\ 1044 + GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0) 1128 1045 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ 1129 - FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1046 + spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1130 1047 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ 1131 - FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1048 + spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1132 1049 1133 - #define ANA_AC_SDLB_XLB_NEXT_LBGRP GENMASK(27, 24) 1050 + #define ANA_AC_SDLB_XLB_NEXT_LBGRP\ 1051 + GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24) 1134 1052 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ 1135 - FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1053 + spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1136 1054 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ 1137 - FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1055 + spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1138 1056 1139 - /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ 1140 - #define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\ 1141 - 0, 1, 0, g, 4616, 64, 20, r, 2, 4) 1057 + /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ 1058 + #define ANA_AC_SDLB_INH_CTRL(g, r) \ 1059 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1060 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4) 1142 1061 1143 1062 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) 1144 1063 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ ··· 1162 1073 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ 1163 1074 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1164 1075 1165 - /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ 1166 - #define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\ 1167 - 0, 1, 0, g, 4616, 64, 28, 0, 1, 4) 1076 + /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ 1077 + #define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ 1078 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1079 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4) 1168 1080 1169 - #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR GENMASK(12, 0) 1081 + #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\ 1082 + GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0) 1170 1083 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ 1171 - FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1084 + spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1172 1085 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ 1173 - FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1086 + spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1174 1087 1175 - /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ 1176 - #define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ 1177 - 0, 1, 0, g, 4616, 64, 32, 0, 1, 4) 1088 + /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ 1089 + #define ANA_AC_SDLB_DLB_MISC(g) \ 1090 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1091 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4) 1178 1092 1179 1093 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) 1180 1094 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ ··· 1197 1105 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ 1198 1106 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1199 1107 1200 - /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ 1201 - #define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\ 1202 - 0, 1, 0, g, 4616, 64, 36, 0, 1, 4) 1108 + /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ 1109 + #define ANA_AC_SDLB_DLB_CFG(g) \ 1110 + __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1111 + regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4) 1203 1112 1204 1113 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) 1205 1114 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ ··· 1250 1157 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ 1251 1158 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1252 1159 1253 - /* ANA_CL:PORT:FILTER_CTRL */ 1254 - #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ 1255 - 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) 1160 + /* ANA_CL:PORT:FILTER_CTRL */ 1161 + #define ANA_CL_FILTER_CTRL(g) \ 1162 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1163 + regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4) 1256 1164 1257 1165 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) 1258 1166 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ ··· 1273 1179 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ 1274 1180 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1275 1181 1276 - /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 1277 - #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\ 1278 - 0, 1, 131072, g, 70, 512, 8, r, 3, 4) 1182 + /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 1183 + #define ANA_CL_VLAN_FILTER_CTRL(g, r) \ 1184 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1185 + regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4) 1279 1186 1280 1187 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) 1281 1188 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ ··· 1344 1249 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ 1345 1250 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1346 1251 1347 - /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 1348 - #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ 1349 - 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) 1252 + /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 1253 + #define ANA_CL_ETAG_FILTER_CTRL(g) \ 1254 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1255 + regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4) 1350 1256 1351 1257 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) 1352 1258 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ ··· 1361 1265 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ 1362 1266 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1363 1267 1364 - /* ANA_CL:PORT:VLAN_CTRL */ 1365 - #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\ 1366 - 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) 1268 + /* ANA_CL:PORT:VLAN_CTRL */ 1269 + #define ANA_CL_VLAN_CTRL(g) \ 1270 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1271 + regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4) 1367 1272 1368 1273 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) 1369 1274 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ ··· 1432 1335 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ 1433 1336 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) 1434 1337 1435 - /* ANA_CL:PORT:VLAN_CTRL_2 */ 1436 - #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\ 1437 - 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) 1338 + /* ANA_CL:PORT:VLAN_CTRL_2 */ 1339 + #define ANA_CL_VLAN_CTRL_2(g) \ 1340 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1341 + regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4) 1438 1342 1439 1343 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) 1440 1344 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ ··· 1443 1345 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ 1444 1346 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1445 1347 1446 - /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 1447 - #define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\ 1448 - 0, 1, 131072, g, 70, 512, 108, r, 16, 4) 1348 + /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 1349 + #define ANA_CL_PCP_DEI_MAP_CFG(g, r) \ 1350 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1351 + regs->gcnt[GC_ANA_CL_PORT], 512, 108, r, 16, 4) 1449 1352 1450 1353 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) 1451 1354 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ ··· 1460 1361 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ 1461 1362 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1462 1363 1463 - /* ANA_CL:PORT:QOS_CFG */ 1464 - #define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\ 1465 - 0, 1, 131072, g, 70, 512, 172, 0, 1, 4) 1364 + /* ANA_CL:PORT:QOS_CFG */ 1365 + #define ANA_CL_QOS_CFG(g) \ 1366 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1367 + regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4) 1466 1368 1467 1369 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) 1468 1370 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ ··· 1537 1437 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ 1538 1438 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1539 1439 1540 - /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 1541 - #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\ 1542 - 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) 1440 + /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 1441 + #define ANA_CL_CAPTURE_BPDU_CFG(g) \ 1442 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1443 + regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4) 1543 1444 1544 - /* ANA_CL:PORT:ADV_CL_CFG_2 */ 1545 - #define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\ 1546 - 0, 1, 131072, g, 70, 512, 200, r, 6, 4) 1445 + /* ANA_CL:PORT:ADV_CL_CFG_2 */ 1446 + #define ANA_CL_ADV_CL_CFG_2(g, r) \ 1447 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1448 + regs->gcnt[GC_ANA_CL_PORT], 512, 200, r, 6, 4) 1547 1449 1548 1450 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) 1549 1451 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ ··· 1559 1457 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ 1560 1458 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1561 1459 1562 - /* ANA_CL:PORT:ADV_CL_CFG */ 1563 - #define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\ 1564 - 0, 1, 131072, g, 70, 512, 224, r, 6, 4) 1460 + /* ANA_CL:PORT:ADV_CL_CFG */ 1461 + #define ANA_CL_ADV_CL_CFG(g, r) \ 1462 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1463 + regs->gcnt[GC_ANA_CL_PORT], 512, 224, r, 6, 4) 1565 1464 1566 1465 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) 1567 1466 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ ··· 1606 1503 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ 1607 1504 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1608 1505 1609 - /* ANA_CL:COMMON:OWN_UPSID */ 1610 - #define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL,\ 1611 - 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) 1506 + /* ANA_CL:COMMON:OWN_UPSID */ 1507 + #define ANA_CL_OWN_UPSID(r) \ 1508 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\ 1509 + r, regs->rcnt[RC_ANA_CL_OWN_UPSID], 4) 1612 1510 1613 1511 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1614 1512 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ ··· 1617 1513 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ 1618 1514 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1619 1515 1620 - /* ANA_CL:COMMON:DSCP_CFG */ 1621 - #define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL,\ 1622 - 0, 1, 166912, 0, 1, 756, 256, r, 64, 4) 1516 + /* ANA_CL:COMMON:DSCP_CFG */ 1517 + #define ANA_CL_DSCP_CFG(r) \ 1518 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ 1519 + 256, r, 64, 4) 1623 1520 1624 1521 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) 1625 1522 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ ··· 1652 1547 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 1653 1548 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1654 1549 1655 - /* ANA_CL:COMMON:QOS_MAP_CFG */ 1656 - #define ANA_CL_QOS_MAP_CFG(r) __REG(TARGET_ANA_CL,\ 1657 - 0, 1, 166912, 0, 1, 756, 512, r, 32, 4) 1550 + /* ANA_CL:COMMON:QOS_MAP_CFG */ 1551 + #define ANA_CL_QOS_MAP_CFG(r) \ 1552 + __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ 1553 + 512, r, 32, 4) 1658 1554 1659 1555 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) 1660 1556 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ ··· 1663 1557 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ 1664 1558 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1665 1559 1666 - /* ANA_L2:COMMON:FWD_CFG */ 1667 - #define ANA_L2_FWD_CFG __REG(TARGET_ANA_L2,\ 1668 - 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4) 1560 + /* ANA_L2:COMMON:FWD_CFG */ 1561 + #define ANA_L2_FWD_CFG \ 1562 + __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1563 + regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4) 1669 1564 1670 1565 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) 1671 1566 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ ··· 1740 1633 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ 1741 1634 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) 1742 1635 1743 - /* ANA_L2:COMMON:AUTO_LRN_CFG */ 1744 - #define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2,\ 1745 - 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) 1636 + /* ANA_L2:COMMON:AUTO_LRN_CFG */ 1637 + #define ANA_L2_AUTO_LRN_CFG \ 1638 + __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1639 + regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4) 1746 1640 1747 - /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 1748 - #define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2,\ 1749 - 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) 1641 + /* SPARX5 ONLY */ 1642 + /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 1643 + #define ANA_L2_AUTO_LRN_CFG1 \ 1644 + __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1645 + regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4) 1750 1646 1751 - /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 1752 - #define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2,\ 1753 - 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) 1647 + /* SPARX5 ONLY */ 1648 + /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 1649 + #define ANA_L2_AUTO_LRN_CFG2 \ 1650 + __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1651 + regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4) 1754 1652 1755 1653 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) 1756 1654 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ ··· 1763 1651 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ 1764 1652 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1765 1653 1766 - /* ANA_L2:COMMON:OWN_UPSID */ 1767 - #define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2,\ 1768 - 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) 1654 + /* ANA_L2:COMMON:OWN_UPSID */ 1655 + #define ANA_L2_OWN_UPSID(r) \ 1656 + __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1657 + regs->gsize[GW_ANA_L2_COMMON], 672, r, \ 1658 + regs->rcnt[RC_ANA_L2_OWN_UPSID], 4) 1769 1659 1770 1660 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1771 1661 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ ··· 1775 1661 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ 1776 1662 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1777 1663 1778 - /* ANA_L2:ISDX:DLB_CFG */ 1779 - #define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\ 1780 - 0, 1, 0, g, 4096, 128, 56, 0, 1, 4) 1664 + /* ANA_L2:ISDX:DLB_CFG */ 1665 + #define ANA_L2_DLB_CFG(g) \ 1666 + __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \ 1667 + 0, 1, 4) 1781 1668 1782 - #define ANA_L2_DLB_CFG_DLB_IDX GENMASK(12, 0) 1669 + #define ANA_L2_DLB_CFG_DLB_IDX\ 1670 + GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0) 1783 1671 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ 1784 - FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x) 1672 + spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x) 1785 1673 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ 1786 - FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x) 1674 + spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x) 1787 1675 1788 - /* ANA_L2:ISDX:TSN_CFG */ 1789 - #define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\ 1790 - 0, 1, 0, g, 4096, 128, 100, 0, 1, 4) 1676 + /* ANA_L2:ISDX:TSN_CFG */ 1677 + #define ANA_L2_TSN_CFG(g) \ 1678 + __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \ 1679 + 0, 1, 4) 1791 1680 1792 - #define ANA_L2_TSN_CFG_TSN_SFID GENMASK(9, 0) 1681 + #define ANA_L2_TSN_CFG_TSN_SFID\ 1682 + GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0) 1793 1683 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ 1794 - FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x) 1684 + spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x) 1795 1685 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ 1796 - FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x) 1686 + spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x) 1797 1687 1798 - /* ANA_L3:COMMON:VLAN_CTRL */ 1799 - #define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3,\ 1800 - 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) 1688 + /* ANA_L3:COMMON:VLAN_CTRL */ 1689 + #define ANA_L3_VLAN_CTRL \ 1690 + __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\ 1691 + 0, 1, 4) 1801 1692 1802 1693 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) 1803 1694 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ ··· 1810 1691 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ 1811 1692 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1812 1693 1813 - /* ANA_L3:VLAN:VLAN_CFG */ 1814 - #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\ 1815 - 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) 1694 + /* ANA_L3:VLAN:VLAN_CFG */ 1695 + #define ANA_L3_VLAN_CFG(g) \ 1696 + __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \ 1697 + 1, 4) 1816 1698 1817 1699 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) 1818 1700 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ ··· 1869 1749 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ 1870 1750 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1871 1751 1872 - /* ANA_L3:VLAN:VLAN_MASK_CFG */ 1873 - #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\ 1874 - 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) 1752 + /* ANA_L3:VLAN:VLAN_MASK_CFG */ 1753 + #define ANA_L3_VLAN_MASK_CFG(g) \ 1754 + __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\ 1755 + 1, 4) 1875 1756 1876 - /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 1877 - #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\ 1878 - 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) 1757 + /* SPARX5 ONLY */ 1758 + /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 1759 + #define ANA_L3_VLAN_MASK_CFG1(g) \ 1760 + __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\ 1761 + 1, 4) 1879 1762 1880 - /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 1881 - #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\ 1882 - 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) 1763 + /* SPARX5 ONLY */ 1764 + /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 1765 + #define ANA_L3_VLAN_MASK_CFG2(g) \ 1766 + __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\ 1767 + 1, 4) 1883 1768 1884 1769 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) 1885 1770 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ ··· 1892 1767 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ 1893 1768 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1894 1769 1895 - /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 1896 - #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\ 1897 - 0, 1, 0, g, 65, 512, 0, 0, 1, 4) 1898 - 1899 - /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 1900 - #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ 1901 - 0, 1, 0, g, 65, 512, 4, 0, 1, 4) 1902 - 1903 - /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1904 - #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 1905 - 0, 1, 0, g, 65, 512, 8, 0, 1, 4) 1906 - 1907 - /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1908 - #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ 1909 - 0, 1, 0, g, 65, 512, 12, 0, 1, 4) 1910 - 1911 - /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1912 - #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 1913 - 0, 1, 0, g, 65, 512, 16, 0, 1, 4) 1914 - 1915 - /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1916 - #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ 1917 - 0, 1, 0, g, 65, 512, 20, 0, 1, 4) 1918 - 1919 - /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1920 - #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\ 1921 - 0, 1, 0, g, 65, 512, 24, 0, 1, 4) 1922 - 1923 - /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1924 - #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\ 1925 - 0, 1, 0, g, 65, 512, 28, 0, 1, 4) 1926 - 1927 - /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1928 - #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\ 1929 - 0, 1, 0, g, 65, 512, 32, 0, 1, 4) 1930 - 1931 - /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1932 - #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ 1933 - 0, 1, 0, g, 65, 512, 36, 0, 1, 4) 1934 - 1935 - /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1936 - #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ 1937 - 0, 1, 0, g, 65, 512, 40, 0, 1, 4) 1938 - 1939 - /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1940 - #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ 1941 - 0, 1, 0, g, 65, 512, 44, 0, 1, 4) 1942 - 1943 - /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1944 - #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 1945 - 0, 1, 0, g, 65, 512, 48, 0, 1, 4) 1946 - 1947 - /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1948 - #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 1949 - 0, 1, 0, g, 65, 512, 52, 0, 1, 4) 1950 - 1951 - /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1952 - #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ 1953 - 0, 1, 0, g, 65, 512, 56, 0, 1, 4) 1954 - 1955 - /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1956 - #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ 1957 - 0, 1, 0, g, 65, 512, 60, 0, 1, 4) 1958 - 1959 - /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1960 - #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 1961 - 0, 1, 0, g, 65, 512, 64, 0, 1, 4) 1962 - 1963 - /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1964 - #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 1965 - 0, 1, 0, g, 65, 512, 68, 0, 1, 4) 1966 - 1967 - /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1968 - #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 1969 - 0, 1, 0, g, 65, 512, 72, 0, 1, 4) 1970 - 1971 - /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1972 - #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 1973 - 0, 1, 0, g, 65, 512, 76, 0, 1, 4) 1974 - 1975 - /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1976 - #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 1977 - 0, 1, 0, g, 65, 512, 80, 0, 1, 4) 1978 - 1979 - /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 1980 - #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 1981 - 0, 1, 0, g, 65, 512, 84, 0, 1, 4) 1982 - 1983 - /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 1984 - #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 1985 - 0, 1, 0, g, 65, 512, 88, 0, 1, 4) 1986 - 1987 - /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 1988 - #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\ 1989 - 0, 1, 0, g, 65, 512, 92, 0, 1, 4) 1990 - 1991 - /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 1992 - #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\ 1993 - 0, 1, 0, g, 65, 512, 96, 0, 1, 4) 1994 - 1995 - /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 1996 - #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 1997 - 0, 1, 0, g, 65, 512, 100, 0, 1, 4) 1998 - 1999 - /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 2000 - #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 2001 - 0, 1, 0, g, 65, 512, 104, 0, 1, 4) 2002 - 2003 - /* ASM:DEV_STATISTICS:TX_UC_CNT */ 2004 - #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\ 2005 - 0, 1, 0, g, 65, 512, 108, 0, 1, 4) 2006 - 2007 - /* ASM:DEV_STATISTICS:TX_MC_CNT */ 2008 - #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\ 2009 - 0, 1, 0, g, 65, 512, 112, 0, 1, 4) 2010 - 2011 - /* ASM:DEV_STATISTICS:TX_BC_CNT */ 2012 - #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\ 2013 - 0, 1, 0, g, 65, 512, 116, 0, 1, 4) 2014 - 2015 - /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 2016 - #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 2017 - 0, 1, 0, g, 65, 512, 120, 0, 1, 4) 2018 - 2019 - /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 2020 - #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 2021 - 0, 1, 0, g, 65, 512, 124, 0, 1, 4) 2022 - 2023 - /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 2024 - #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 2025 - 0, 1, 0, g, 65, 512, 128, 0, 1, 4) 2026 - 2027 - /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 2028 - #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 2029 - 0, 1, 0, g, 65, 512, 132, 0, 1, 4) 2030 - 2031 - /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 2032 - #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 2033 - 0, 1, 0, g, 65, 512, 136, 0, 1, 4) 2034 - 2035 - /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 2036 - #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 2037 - 0, 1, 0, g, 65, 512, 140, 0, 1, 4) 2038 - 2039 - /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 2040 - #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 2041 - 0, 1, 0, g, 65, 512, 144, 0, 1, 4) 2042 - 2043 - /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 2044 - #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ 2045 - 0, 1, 0, g, 65, 512, 148, 0, 1, 4) 2046 - 2047 - /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 2048 - #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 2049 - 0, 1, 0, g, 65, 512, 152, 0, 1, 4) 2050 - 2051 - /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 2052 - #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 2053 - 0, 1, 0, g, 65, 512, 156, 0, 1, 4) 2054 - 2055 - /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 2056 - #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 2057 - 0, 1, 0, g, 65, 512, 160, 0, 1, 4) 2058 - 2059 - /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 2060 - #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 2061 - 0, 1, 0, g, 65, 512, 164, 0, 1, 4) 2062 - 2063 - /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 2064 - #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ 2065 - 0, 1, 0, g, 65, 512, 168, 0, 1, 4) 2066 - 2067 - /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 2068 - #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 2069 - 0, 1, 0, g, 65, 512, 172, 0, 1, 4) 2070 - 2071 - /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 2072 - #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ 2073 - 0, 1, 0, g, 65, 512, 176, 0, 1, 4) 2074 - 2075 - /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 2076 - #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 2077 - 0, 1, 0, g, 65, 512, 180, 0, 1, 4) 2078 - 2079 - /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 2080 - #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ 2081 - 0, 1, 0, g, 65, 512, 184, 0, 1, 4) 2082 - 2083 - /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 2084 - #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\ 2085 - 0, 1, 0, g, 65, 512, 188, 0, 1, 4) 2086 - 2087 - /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 2088 - #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\ 2089 - 0, 1, 0, g, 65, 512, 192, 0, 1, 4) 2090 - 2091 - /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 2092 - #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\ 2093 - 0, 1, 0, g, 65, 512, 196, 0, 1, 4) 2094 - 2095 - /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 2096 - #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ 2097 - 0, 1, 0, g, 65, 512, 200, 0, 1, 4) 2098 - 2099 - /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 2100 - #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ 2101 - 0, 1, 0, g, 65, 512, 204, 0, 1, 4) 2102 - 2103 - /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 2104 - #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ 2105 - 0, 1, 0, g, 65, 512, 208, 0, 1, 4) 2106 - 2107 - /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 2108 - #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 2109 - 0, 1, 0, g, 65, 512, 212, 0, 1, 4) 2110 - 2111 - /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 2112 - #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 2113 - 0, 1, 0, g, 65, 512, 216, 0, 1, 4) 2114 - 2115 - /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 2116 - #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ 2117 - 0, 1, 0, g, 65, 512, 220, 0, 1, 4) 2118 - 2119 - /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 2120 - #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ 2121 - 0, 1, 0, g, 65, 512, 224, 0, 1, 4) 2122 - 2123 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 2124 - #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 2125 - 0, 1, 0, g, 65, 512, 228, 0, 1, 4) 2126 - 2127 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 2128 - #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 2129 - 0, 1, 0, g, 65, 512, 232, 0, 1, 4) 2130 - 2131 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 2132 - #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 2133 - 0, 1, 0, g, 65, 512, 236, 0, 1, 4) 2134 - 2135 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 2136 - #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 2137 - 0, 1, 0, g, 65, 512, 240, 0, 1, 4) 2138 - 2139 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 2140 - #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 2141 - 0, 1, 0, g, 65, 512, 244, 0, 1, 4) 2142 - 2143 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 2144 - #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 2145 - 0, 1, 0, g, 65, 512, 248, 0, 1, 4) 2146 - 2147 - /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 2148 - #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 2149 - 0, 1, 0, g, 65, 512, 252, 0, 1, 4) 2150 - 2151 - /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 2152 - #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 2153 - 0, 1, 0, g, 65, 512, 256, 0, 1, 4) 2154 - 2155 - /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 2156 - #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 2157 - 0, 1, 0, g, 65, 512, 260, 0, 1, 4) 2158 - 2159 - /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 2160 - #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\ 2161 - 0, 1, 0, g, 65, 512, 264, 0, 1, 4) 2162 - 2163 - /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 2164 - #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\ 2165 - 0, 1, 0, g, 65, 512, 268, 0, 1, 4) 2166 - 2167 - /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 2168 - #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\ 2169 - 0, 1, 0, g, 65, 512, 272, 0, 1, 4) 2170 - 2171 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 2172 - #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 2173 - 0, 1, 0, g, 65, 512, 276, 0, 1, 4) 2174 - 2175 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 2176 - #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 2177 - 0, 1, 0, g, 65, 512, 280, 0, 1, 4) 2178 - 2179 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 2180 - #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 2181 - 0, 1, 0, g, 65, 512, 284, 0, 1, 4) 2182 - 2183 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 2184 - #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 2185 - 0, 1, 0, g, 65, 512, 288, 0, 1, 4) 2186 - 2187 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 2188 - #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 2189 - 0, 1, 0, g, 65, 512, 292, 0, 1, 4) 2190 - 2191 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 2192 - #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 2193 - 0, 1, 0, g, 65, 512, 296, 0, 1, 4) 2194 - 2195 - /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 2196 - #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 2197 - 0, 1, 0, g, 65, 512, 300, 0, 1, 4) 2198 - 2199 - /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 2200 - #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ 2201 - 0, 1, 0, g, 65, 512, 304, 0, 1, 4) 2202 - 2203 - /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 2204 - #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\ 2205 - 0, 1, 0, g, 65, 512, 308, 0, 1, 4) 2206 - 2207 - /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 2208 - #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\ 2209 - 0, 1, 0, g, 65, 512, 312, 0, 1, 4) 2210 - 2211 - /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 2212 - #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\ 2213 - 0, 1, 0, g, 65, 512, 316, 0, 1, 4) 2214 - 2215 - /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 2216 - #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\ 2217 - 0, 1, 0, g, 65, 512, 320, 0, 1, 4) 2218 - 2219 - /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 2220 - #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\ 2221 - 0, 1, 0, g, 65, 512, 324, 0, 1, 4) 2222 - 2223 - /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 2224 - #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\ 2225 - 0, 1, 0, g, 65, 512, 328, 0, 1, 4) 2226 - 2227 - /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 2228 - #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\ 2229 - 0, 1, 0, g, 65, 512, 332, 0, 1, 4) 2230 - 2231 - /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 2232 - #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\ 2233 - 0, 1, 0, g, 65, 512, 336, 0, 1, 4) 2234 - 2235 - /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 2236 - #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\ 2237 - 0, 1, 0, g, 65, 512, 340, 0, 1, 4) 2238 - 2239 - /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 2240 - #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\ 2241 - 0, 1, 0, g, 65, 512, 344, 0, 1, 4) 2242 - 2243 - /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 2244 - #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\ 2245 - 0, 1, 0, g, 65, 512, 348, 0, 1, 4) 2246 - 2247 - /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 2248 - #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\ 2249 - 0, 1, 0, g, 65, 512, 352, 0, 1, 4) 2250 - 2251 - /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 2252 - #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2253 - 0, 1, 0, g, 65, 512, 356, 0, 1, 4) 1770 + /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 1771 + #define ASM_RX_IN_BYTES_CNT(g) \ 1772 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1773 + 0, 0, 1, 4) 1774 + 1775 + /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 1776 + #define ASM_RX_SYMBOL_ERR_CNT(g) \ 1777 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1778 + 4, 0, 1, 4) 1779 + 1780 + /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1781 + #define ASM_RX_PAUSE_CNT(g) \ 1782 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1783 + 8, 0, 1, 4) 1784 + 1785 + /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1786 + #define ASM_RX_UNSUP_OPCODE_CNT(g) \ 1787 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1788 + 12, 0, 1, 4) 1789 + 1790 + /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1791 + #define ASM_RX_OK_BYTES_CNT(g) \ 1792 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1793 + 16, 0, 1, 4) 1794 + 1795 + /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1796 + #define ASM_RX_BAD_BYTES_CNT(g) \ 1797 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1798 + 20, 0, 1, 4) 1799 + 1800 + /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1801 + #define ASM_RX_UC_CNT(g) \ 1802 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1803 + 24, 0, 1, 4) 1804 + 1805 + /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1806 + #define ASM_RX_MC_CNT(g) \ 1807 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1808 + 28, 0, 1, 4) 1809 + 1810 + /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1811 + #define ASM_RX_BC_CNT(g) \ 1812 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1813 + 32, 0, 1, 4) 1814 + 1815 + /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1816 + #define ASM_RX_CRC_ERR_CNT(g) \ 1817 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1818 + 36, 0, 1, 4) 1819 + 1820 + /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1821 + #define ASM_RX_UNDERSIZE_CNT(g) \ 1822 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1823 + 40, 0, 1, 4) 1824 + 1825 + /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1826 + #define ASM_RX_FRAGMENTS_CNT(g) \ 1827 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1828 + 44, 0, 1, 4) 1829 + 1830 + /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1831 + #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) \ 1832 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1833 + 48, 0, 1, 4) 1834 + 1835 + /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1836 + #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ 1837 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1838 + 52, 0, 1, 4) 1839 + 1840 + /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1841 + #define ASM_RX_OVERSIZE_CNT(g) \ 1842 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1843 + 56, 0, 1, 4) 1844 + 1845 + /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1846 + #define ASM_RX_JABBERS_CNT(g) \ 1847 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1848 + 60, 0, 1, 4) 1849 + 1850 + /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1851 + #define ASM_RX_SIZE64_CNT(g) \ 1852 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1853 + 64, 0, 1, 4) 1854 + 1855 + /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1856 + #define ASM_RX_SIZE65TO127_CNT(g) \ 1857 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1858 + 68, 0, 1, 4) 1859 + 1860 + /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1861 + #define ASM_RX_SIZE128TO255_CNT(g) \ 1862 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1863 + 72, 0, 1, 4) 1864 + 1865 + /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1866 + #define ASM_RX_SIZE256TO511_CNT(g) \ 1867 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1868 + 76, 0, 1, 4) 1869 + 1870 + /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1871 + #define ASM_RX_SIZE512TO1023_CNT(g) \ 1872 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1873 + 80, 0, 1, 4) 1874 + 1875 + /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 1876 + #define ASM_RX_SIZE1024TO1518_CNT(g) \ 1877 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1878 + 84, 0, 1, 4) 1879 + 1880 + /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 1881 + #define ASM_RX_SIZE1519TOMAX_CNT(g) \ 1882 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1883 + 88, 0, 1, 4) 1884 + 1885 + /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 1886 + #define ASM_RX_IPG_SHRINK_CNT(g) \ 1887 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1888 + 92, 0, 1, 4) 1889 + 1890 + /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 1891 + #define ASM_TX_OUT_BYTES_CNT(g) \ 1892 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1893 + 96, 0, 1, 4) 1894 + 1895 + /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 1896 + #define ASM_TX_PAUSE_CNT(g) \ 1897 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1898 + 100, 0, 1, 4) 1899 + 1900 + /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 1901 + #define ASM_TX_OK_BYTES_CNT(g) \ 1902 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1903 + 104, 0, 1, 4) 1904 + 1905 + /* ASM:DEV_STATISTICS:TX_UC_CNT */ 1906 + #define ASM_TX_UC_CNT(g) \ 1907 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1908 + 108, 0, 1, 4) 1909 + 1910 + /* ASM:DEV_STATISTICS:TX_MC_CNT */ 1911 + #define ASM_TX_MC_CNT(g) \ 1912 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1913 + 112, 0, 1, 4) 1914 + 1915 + /* ASM:DEV_STATISTICS:TX_BC_CNT */ 1916 + #define ASM_TX_BC_CNT(g) \ 1917 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1918 + 116, 0, 1, 4) 1919 + 1920 + /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 1921 + #define ASM_TX_SIZE64_CNT(g) \ 1922 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1923 + 120, 0, 1, 4) 1924 + 1925 + /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 1926 + #define ASM_TX_SIZE65TO127_CNT(g) \ 1927 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1928 + 124, 0, 1, 4) 1929 + 1930 + /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 1931 + #define ASM_TX_SIZE128TO255_CNT(g) \ 1932 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1933 + 128, 0, 1, 4) 1934 + 1935 + /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 1936 + #define ASM_TX_SIZE256TO511_CNT(g) \ 1937 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1938 + 132, 0, 1, 4) 1939 + 1940 + /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 1941 + #define ASM_TX_SIZE512TO1023_CNT(g) \ 1942 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1943 + 136, 0, 1, 4) 1944 + 1945 + /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 1946 + #define ASM_TX_SIZE1024TO1518_CNT(g) \ 1947 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1948 + 140, 0, 1, 4) 1949 + 1950 + /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 1951 + #define ASM_TX_SIZE1519TOMAX_CNT(g) \ 1952 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1953 + 144, 0, 1, 4) 1954 + 1955 + /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 1956 + #define ASM_RX_ALIGNMENT_LOST_CNT(g) \ 1957 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1958 + 148, 0, 1, 4) 1959 + 1960 + /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 1961 + #define ASM_RX_TAGGED_FRMS_CNT(g) \ 1962 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1963 + 152, 0, 1, 4) 1964 + 1965 + /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 1966 + #define ASM_RX_UNTAGGED_FRMS_CNT(g) \ 1967 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1968 + 156, 0, 1, 4) 1969 + 1970 + /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 1971 + #define ASM_TX_TAGGED_FRMS_CNT(g) \ 1972 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1973 + 160, 0, 1, 4) 1974 + 1975 + /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 1976 + #define ASM_TX_UNTAGGED_FRMS_CNT(g) \ 1977 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1978 + 164, 0, 1, 4) 1979 + 1980 + /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 1981 + #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) \ 1982 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1983 + 168, 0, 1, 4) 1984 + 1985 + /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 1986 + #define ASM_PMAC_RX_PAUSE_CNT(g) \ 1987 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1988 + 172, 0, 1, 4) 1989 + 1990 + /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 1991 + #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) \ 1992 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1993 + 176, 0, 1, 4) 1994 + 1995 + /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 1996 + #define ASM_PMAC_RX_OK_BYTES_CNT(g) \ 1997 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1998 + 180, 0, 1, 4) 1999 + 2000 + /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 2001 + #define ASM_PMAC_RX_BAD_BYTES_CNT(g) \ 2002 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2003 + 184, 0, 1, 4) 2004 + 2005 + /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 2006 + #define ASM_PMAC_RX_UC_CNT(g) \ 2007 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2008 + 188, 0, 1, 4) 2009 + 2010 + /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 2011 + #define ASM_PMAC_RX_MC_CNT(g) \ 2012 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2013 + 192, 0, 1, 4) 2014 + 2015 + /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 2016 + #define ASM_PMAC_RX_BC_CNT(g) \ 2017 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2018 + 196, 0, 1, 4) 2019 + 2020 + /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 2021 + #define ASM_PMAC_RX_CRC_ERR_CNT(g) \ 2022 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2023 + 200, 0, 1, 4) 2024 + 2025 + /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 2026 + #define ASM_PMAC_RX_UNDERSIZE_CNT(g) \ 2027 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2028 + 204, 0, 1, 4) 2029 + 2030 + /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 2031 + #define ASM_PMAC_RX_FRAGMENTS_CNT(g) \ 2032 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2033 + 208, 0, 1, 4) 2034 + 2035 + /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 2036 + #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) \ 2037 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2038 + 212, 0, 1, 4) 2039 + 2040 + /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 2041 + #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ 2042 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2043 + 216, 0, 1, 4) 2044 + 2045 + /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 2046 + #define ASM_PMAC_RX_OVERSIZE_CNT(g) \ 2047 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2048 + 220, 0, 1, 4) 2049 + 2050 + /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 2051 + #define ASM_PMAC_RX_JABBERS_CNT(g) \ 2052 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2053 + 224, 0, 1, 4) 2054 + 2055 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 2056 + #define ASM_PMAC_RX_SIZE64_CNT(g) \ 2057 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2058 + 228, 0, 1, 4) 2059 + 2060 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 2061 + #define ASM_PMAC_RX_SIZE65TO127_CNT(g) \ 2062 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2063 + 232, 0, 1, 4) 2064 + 2065 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 2066 + #define ASM_PMAC_RX_SIZE128TO255_CNT(g) \ 2067 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2068 + 236, 0, 1, 4) 2069 + 2070 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 2071 + #define ASM_PMAC_RX_SIZE256TO511_CNT(g) \ 2072 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2073 + 240, 0, 1, 4) 2074 + 2075 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 2076 + #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) \ 2077 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2078 + 244, 0, 1, 4) 2079 + 2080 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 2081 + #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) \ 2082 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2083 + 248, 0, 1, 4) 2084 + 2085 + /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 2086 + #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) \ 2087 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2088 + 252, 0, 1, 4) 2089 + 2090 + /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 2091 + #define ASM_PMAC_TX_PAUSE_CNT(g) \ 2092 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2093 + 256, 0, 1, 4) 2094 + 2095 + /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 2096 + #define ASM_PMAC_TX_OK_BYTES_CNT(g) \ 2097 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2098 + 260, 0, 1, 4) 2099 + 2100 + /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 2101 + #define ASM_PMAC_TX_UC_CNT(g) \ 2102 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2103 + 264, 0, 1, 4) 2104 + 2105 + /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 2106 + #define ASM_PMAC_TX_MC_CNT(g) \ 2107 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2108 + 268, 0, 1, 4) 2109 + 2110 + /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 2111 + #define ASM_PMAC_TX_BC_CNT(g) \ 2112 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2113 + 272, 0, 1, 4) 2114 + 2115 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 2116 + #define ASM_PMAC_TX_SIZE64_CNT(g) \ 2117 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2118 + 276, 0, 1, 4) 2119 + 2120 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 2121 + #define ASM_PMAC_TX_SIZE65TO127_CNT(g) \ 2122 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2123 + 280, 0, 1, 4) 2124 + 2125 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 2126 + #define ASM_PMAC_TX_SIZE128TO255_CNT(g) \ 2127 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2128 + 284, 0, 1, 4) 2129 + 2130 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 2131 + #define ASM_PMAC_TX_SIZE256TO511_CNT(g) \ 2132 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2133 + 288, 0, 1, 4) 2134 + 2135 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 2136 + #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) \ 2137 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2138 + 292, 0, 1, 4) 2139 + 2140 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 2141 + #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) \ 2142 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2143 + 296, 0, 1, 4) 2144 + 2145 + /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 2146 + #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) \ 2147 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2148 + 300, 0, 1, 4) 2149 + 2150 + /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 2151 + #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) \ 2152 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2153 + 304, 0, 1, 4) 2154 + 2155 + /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 2156 + #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) \ 2157 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2158 + 308, 0, 1, 4) 2159 + 2160 + /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 2161 + #define ASM_MM_RX_SMD_ERR_CNT(g) \ 2162 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2163 + 312, 0, 1, 4) 2164 + 2165 + /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 2166 + #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) \ 2167 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2168 + 316, 0, 1, 4) 2169 + 2170 + /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 2171 + #define ASM_MM_RX_MERGE_FRAG_CNT(g) \ 2172 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2173 + 320, 0, 1, 4) 2174 + 2175 + /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 2176 + #define ASM_MM_TX_PFRAGMENT_CNT(g) \ 2177 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2178 + 324, 0, 1, 4) 2179 + 2180 + /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 2181 + #define ASM_TX_MULTI_COLL_CNT(g) \ 2182 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2183 + 328, 0, 1, 4) 2184 + 2185 + /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 2186 + #define ASM_TX_LATE_COLL_CNT(g) \ 2187 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2188 + 332, 0, 1, 4) 2189 + 2190 + /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 2191 + #define ASM_TX_XCOLL_CNT(g) \ 2192 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2193 + 336, 0, 1, 4) 2194 + 2195 + /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 2196 + #define ASM_TX_DEFER_CNT(g) \ 2197 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2198 + 340, 0, 1, 4) 2199 + 2200 + /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 2201 + #define ASM_TX_XDEFER_CNT(g) \ 2202 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2203 + 344, 0, 1, 4) 2204 + 2205 + /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 2206 + #define ASM_TX_BACKOFF1_CNT(g) \ 2207 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2208 + 348, 0, 1, 4) 2209 + 2210 + /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 2211 + #define ASM_TX_CSENSE_CNT(g) \ 2212 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2213 + 352, 0, 1, 4) 2214 + 2215 + /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 2216 + #define ASM_RX_IN_BYTES_MSB_CNT(g) \ 2217 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2218 + 356, 0, 1, 4) 2254 2219 2255 2220 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) 2256 2221 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ ··· 2348 2133 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 2349 2134 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2350 2135 2351 - /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 2352 - #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2353 - 0, 1, 0, g, 65, 512, 360, 0, 1, 4) 2136 + /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 2137 + #define ASM_RX_OK_BYTES_MSB_CNT(g) \ 2138 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2139 + 360, 0, 1, 4) 2354 2140 2355 2141 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2356 2142 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ ··· 2359 2143 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 2360 2144 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2361 2145 2362 - /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 2363 - #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2364 - 0, 1, 0, g, 65, 512, 364, 0, 1, 4) 2146 + /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 2147 + #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) \ 2148 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2149 + 364, 0, 1, 4) 2365 2150 2366 2151 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2367 2152 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ ··· 2370 2153 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 2371 2154 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2372 2155 2373 - /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 2374 - #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2375 - 0, 1, 0, g, 65, 512, 368, 0, 1, 4) 2156 + /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 2157 + #define ASM_RX_BAD_BYTES_MSB_CNT(g) \ 2158 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2159 + 368, 0, 1, 4) 2376 2160 2377 2161 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2378 2162 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ ··· 2381 2163 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2382 2164 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2383 2165 2384 - /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 2385 - #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2386 - 0, 1, 0, g, 65, 512, 372, 0, 1, 4) 2166 + /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 2167 + #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) \ 2168 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2169 + 372, 0, 1, 4) 2387 2170 2388 2171 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2389 2172 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ ··· 2392 2173 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2393 2174 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2394 2175 2395 - /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 2396 - #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2397 - 0, 1, 0, g, 65, 512, 376, 0, 1, 4) 2176 + /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 2177 + #define ASM_TX_OUT_BYTES_MSB_CNT(g) \ 2178 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2179 + 376, 0, 1, 4) 2398 2180 2399 2181 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) 2400 2182 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ ··· 2403 2183 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 2404 2184 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2405 2185 2406 - /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 2407 - #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2408 - 0, 1, 0, g, 65, 512, 380, 0, 1, 4) 2186 + /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 2187 + #define ASM_TX_OK_BYTES_MSB_CNT(g) \ 2188 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2189 + 380, 0, 1, 4) 2409 2190 2410 2191 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2411 2192 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ ··· 2414 2193 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 2415 2194 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2416 2195 2417 - /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 2418 - #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2419 - 0, 1, 0, g, 65, 512, 384, 0, 1, 4) 2196 + /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 2197 + #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) \ 2198 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2199 + 384, 0, 1, 4) 2420 2200 2421 2201 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2422 2202 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ ··· 2425 2203 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 2426 2204 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2427 2205 2428 - /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 2429 - #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\ 2430 - 0, 1, 0, g, 65, 512, 388, 0, 1, 4) 2206 + /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 2207 + #define ASM_RX_SYNC_LOST_ERR_CNT(g) \ 2208 + __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2209 + 388, 0, 1, 4) 2431 2210 2432 - /* ASM:CFG:STAT_CFG */ 2433 - #define ASM_STAT_CFG __REG(TARGET_ASM,\ 2434 - 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) 2211 + /* ASM:CFG:STAT_CFG */ 2212 + #define ASM_STAT_CFG \ 2213 + __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ 2214 + regs->gsize[GW_ASM_CFG], 0, 0, 1, 4) 2435 2215 2436 2216 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) 2437 2217 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ ··· 2441 2217 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ 2442 2218 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2443 2219 2444 - /* ASM:CFG:PORT_CFG */ 2445 - #define ASM_PORT_CFG(r) __REG(TARGET_ASM,\ 2446 - 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) 2220 + /* ASM:CFG:PORT_CFG */ 2221 + #define ASM_PORT_CFG(r) \ 2222 + __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ 2223 + regs->gsize[GW_ASM_CFG], 540, r, regs->rcnt[RC_ASM_PORT_CFG], 4) 2447 2224 2448 2225 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) 2449 2226 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ ··· 2512 2287 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ 2513 2288 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) 2514 2289 2515 - /* ASM:RAM_CTRL:RAM_INIT */ 2516 - #define ASM_RAM_INIT __REG(TARGET_ASM,\ 2517 - 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) 2290 + /* ASM:RAM_CTRL:RAM_INIT */ 2291 + #define ASM_RAM_INIT \ 2292 + __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 2293 + 4) 2518 2294 2519 2295 #define ASM_RAM_INIT_RAM_INIT BIT(1) 2520 2296 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ ··· 2529 2303 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 2530 2304 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2531 2305 2532 - /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 2533 - #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN,\ 2534 - 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 2306 + /* SPARX5 ONLY */ 2307 + /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 2308 + #define CLKGEN_LCPLL1_CORE_CLK_CFG \ 2309 + __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 2535 2310 2536 2311 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) 2537 2312 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ ··· 2570 2343 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ 2571 2344 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2572 2345 2573 - /* CPU:CPU_REGS:PROC_CTRL */ 2574 - #define CPU_PROC_CTRL __REG(TARGET_CPU,\ 2575 - 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) 2346 + /* CPU:CPU_REGS:PROC_CTRL */ 2347 + #define CPU_PROC_CTRL \ 2348 + __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS], \ 2349 + regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4) 2576 2350 2577 - #define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) 2351 + #define CPU_PROC_CTRL_AARCH64_MODE_ENA\ 2352 + BIT(regs->fpos[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA]) 2578 2353 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ 2579 - FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2354 + spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2580 2355 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ 2581 - FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2356 + spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2582 2357 2583 - #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) 2358 + #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS\ 2359 + BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS]) 2584 2360 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ 2585 - FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2361 + spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2586 2362 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ 2587 - FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2363 + spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2588 2364 2589 - #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) 2365 + #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS\ 2366 + BIT(regs->fpos[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS]) 2590 2367 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ 2591 - FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2368 + spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2592 2369 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ 2593 - FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2370 + spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2594 2371 2595 - #define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) 2372 + #define CPU_PROC_CTRL_BE_EXCEP_MODE\ 2373 + BIT(regs->fpos[FP_CPU_PROC_CTRL_BE_EXCEP_MODE]) 2596 2374 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ 2597 - FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2375 + spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2598 2376 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ 2599 - FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2377 + spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2600 2378 2601 - #define CPU_PROC_CTRL_VINITHI BIT(8) 2379 + #define CPU_PROC_CTRL_VINITHI\ 2380 + BIT(regs->fpos[FP_CPU_PROC_CTRL_VINITHI]) 2602 2381 #define CPU_PROC_CTRL_VINITHI_SET(x)\ 2603 - FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) 2382 + spx5_field_prep(CPU_PROC_CTRL_VINITHI, x) 2604 2383 #define CPU_PROC_CTRL_VINITHI_GET(x)\ 2605 - FIELD_GET(CPU_PROC_CTRL_VINITHI, x) 2384 + spx5_field_get(CPU_PROC_CTRL_VINITHI, x) 2606 2385 2607 - #define CPU_PROC_CTRL_CFGTE BIT(7) 2386 + #define CPU_PROC_CTRL_CFGTE\ 2387 + BIT(regs->fpos[FP_CPU_PROC_CTRL_CFGTE]) 2608 2388 #define CPU_PROC_CTRL_CFGTE_SET(x)\ 2609 - FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) 2389 + spx5_field_prep(CPU_PROC_CTRL_CFGTE, x) 2610 2390 #define CPU_PROC_CTRL_CFGTE_GET(x)\ 2611 - FIELD_GET(CPU_PROC_CTRL_CFGTE, x) 2391 + spx5_field_get(CPU_PROC_CTRL_CFGTE, x) 2612 2392 2613 - #define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) 2393 + #define CPU_PROC_CTRL_CP15S_DISABLE\ 2394 + BIT(regs->fpos[FP_CPU_PROC_CTRL_CP15S_DISABLE]) 2614 2395 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ 2615 - FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) 2396 + spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x) 2616 2397 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ 2617 - FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) 2398 + spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x) 2618 2399 2619 - #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) 2400 + #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE\ 2401 + BIT(regs->fpos[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE]) 2620 2402 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ 2621 - FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2403 + spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2622 2404 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ 2623 - FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2405 + spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2624 2406 2407 + /* SPARX5 ONLY */ 2625 2408 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) 2626 2409 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ 2627 2410 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2628 2411 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ 2629 2412 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2630 2413 2414 + /* SPARX5 ONLY */ 2631 2415 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) 2632 2416 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ 2633 2417 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) 2634 2418 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ 2635 2419 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) 2636 2420 2421 + /* SPARX5 ONLY */ 2637 2422 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) 2638 2423 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ 2639 2424 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) 2640 2425 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ 2641 2426 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) 2642 2427 2643 - #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) 2428 + #define CPU_PROC_CTRL_L2_FLUSH_REQ\ 2429 + BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_FLUSH_REQ]) 2644 2430 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ 2645 - FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2431 + spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2646 2432 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ 2647 - FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2433 + spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2648 2434 2435 + /* SPARX5 ONLY */ 2649 2436 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) 2650 2437 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ 2651 2438 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) 2652 2439 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ 2653 2440 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) 2654 2441 2655 - /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2656 - #define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G,\ 2657 - t, 12, 0, 0, 1, 60, 0, 0, 1, 4) 2442 + /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2443 + #define DEV10G_MAC_ENA_CFG(t) \ 2444 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ 2445 + 4) 2658 2446 2659 2447 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) 2660 2448 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ ··· 2683 2441 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2684 2442 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2685 2443 2686 - /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2687 - #define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G,\ 2688 - t, 12, 0, 0, 1, 60, 8, 0, 1, 4) 2444 + /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2445 + #define DEV10G_MAC_MAXLEN_CFG(t) \ 2446 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1, \ 2447 + 4) 2689 2448 2690 2449 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2691 2450 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ ··· 2700 2457 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2701 2458 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2702 2459 2703 - /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 2704 - #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G,\ 2705 - t, 12, 0, 0, 1, 60, 12, 0, 1, 4) 2460 + /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 2461 + #define DEV10G_MAC_NUM_TAGS_CFG(t) \ 2462 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \ 2463 + 4) 2706 2464 2707 2465 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) 2708 2466 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ ··· 2711 2467 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ 2712 2468 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2713 2469 2714 - /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2715 - #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G,\ 2716 - t, 12, 0, 0, 1, 60, 16, r, 3, 4) 2470 + /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2471 + #define DEV10G_MAC_TAGS_CFG(t, r) \ 2472 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \ 2473 + 4) 2717 2474 2718 2475 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2719 2476 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ ··· 2728 2483 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ 2729 2484 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2730 2485 2731 - /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2732 - #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G,\ 2733 - t, 12, 0, 0, 1, 60, 28, 0, 1, 4) 2486 + /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2487 + #define DEV10G_MAC_ADV_CHK_CFG(t) \ 2488 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \ 2489 + 4) 2734 2490 2735 2491 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2736 2492 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ ··· 2775 2529 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2776 2530 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2777 2531 2778 - /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 2779 - #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G,\ 2780 - t, 12, 0, 0, 1, 60, 48, 0, 1, 4) 2532 + /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 2533 + #define DEV10G_MAC_TX_MONITOR_STICKY(t) \ 2534 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \ 2535 + 4) 2781 2536 2782 2537 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) 2783 2538 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ ··· 2810 2563 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ 2811 2564 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2812 2565 2813 - /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2814 - #define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G,\ 2815 - t, 12, 436, 0, 1, 52, 0, 0, 1, 4) 2566 + /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2567 + #define DEV10G_DEV_RST_CTRL(t) \ 2568 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\ 2569 + 4) 2816 2570 2817 2571 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2818 2572 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ ··· 2869 2621 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2870 2622 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2871 2623 2872 - /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2873 - #define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G,\ 2874 - t, 12, 488, 0, 1, 32, 0, 0, 1, 4) 2624 + /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2625 + #define DEV10G_PCS25G_CFG(t) \ 2626 + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ 2627 + 4) 2875 2628 2876 2629 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) 2877 2630 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ ··· 2880 2631 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2881 2632 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2882 2633 2883 - /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2884 - #define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G,\ 2885 - t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 2634 + /* SPARX5 ONLY */ 2635 + /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2636 + #define DEV25G_MAC_ENA_CFG(t) \ 2637 + __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 2886 2638 2887 2639 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) 2888 2640 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ ··· 2897 2647 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2898 2648 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2899 2649 2900 - /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2901 - #define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G,\ 2902 - t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 2650 + /* SPARX5 ONLY */ 2651 + /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2652 + #define DEV25G_MAC_MAXLEN_CFG(t) \ 2653 + __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 2903 2654 2904 2655 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2905 2656 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ ··· 2914 2663 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2915 2664 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2916 2665 2917 - /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2918 - #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G,\ 2919 - t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 2666 + /* SPARX5 ONLY */ 2667 + /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2668 + #define DEV25G_MAC_ADV_CHK_CFG(t) \ 2669 + __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 2920 2670 2921 2671 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2922 2672 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ ··· 2961 2709 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2962 2710 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2963 2711 2964 - /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2965 - #define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G,\ 2966 - t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 2712 + /* SPARX5 ONLY */ 2713 + /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2714 + #define DEV25G_DEV_RST_CTRL(t) \ 2715 + __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 2967 2716 2968 2717 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2969 2718 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ ··· 3020 2767 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3021 2768 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 3022 2769 3023 - /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 3024 - #define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G,\ 3025 - t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 2770 + /* SPARX5 ONLY */ 2771 + /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2772 + #define DEV25G_PCS25G_CFG(t) \ 2773 + __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 3026 2774 3027 2775 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) 3028 2776 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ ··· 3031 2777 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 3032 2778 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 3033 2779 3034 - /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 3035 - #define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G,\ 3036 - t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 2780 + /* SPARX5 ONLY */ 2781 + /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 2782 + #define DEV25G_PCS25G_SD_CFG(t) \ 2783 + __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 3037 2784 3038 2785 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) 3039 2786 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ ··· 3054 2799 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ 3055 2800 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 3056 2801 3057 - /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3058 - #define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5,\ 3059 - t, 65, 0, 0, 1, 36, 0, 0, 1, 4) 2802 + /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2803 + #define DEV2G5_DEV_RST_CTRL(t) \ 2804 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1, \ 2805 + 4) 3060 2806 3061 2807 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) 3062 2808 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ ··· 3107 2851 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3108 2852 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 3109 2853 3110 - /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3111 - #define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5,\ 3112 - t, 65, 52, 0, 1, 36, 0, 0, 1, 4) 2854 + /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2855 + #define DEV2G5_MAC_ENA_CFG(t) \ 2856 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \ 2857 + 4) 3113 2858 3114 2859 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) 3115 2860 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ ··· 3124 2867 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ 3125 2868 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 3126 2869 3127 - /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 3128 - #define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5,\ 3129 - t, 65, 52, 0, 1, 36, 4, 0, 1, 4) 2870 + /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 2871 + #define DEV2G5_MAC_MODE_CFG(t) \ 2872 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \ 2873 + 4) 3130 2874 3131 2875 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) 3132 2876 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ ··· 3147 2889 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ 3148 2890 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 3149 2891 3150 - /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3151 - #define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5,\ 3152 - t, 65, 52, 0, 1, 36, 8, 0, 1, 4) 2892 + /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2893 + #define DEV2G5_MAC_MAXLEN_CFG(t) \ 2894 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \ 2895 + 4) 3153 2896 3154 2897 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3155 2898 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ ··· 3158 2899 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3159 2900 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 3160 2901 3161 - /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 3162 - #define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5,\ 3163 - t, 65, 52, 0, 1, 36, 12, 0, 1, 4) 2902 + /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2903 + #define DEV2G5_MAC_TAGS_CFG(t) \ 2904 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\ 2905 + 4) 3164 2906 3165 2907 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 3166 2908 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ ··· 3187 2927 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 3188 2928 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 3189 2929 3190 - /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 3191 - #define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5,\ 3192 - t, 65, 52, 0, 1, 36, 16, 0, 1, 4) 2930 + /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 2931 + #define DEV2G5_MAC_TAGS_CFG2(t) \ 2932 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\ 2933 + 4) 3193 2934 3194 2935 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) 3195 2936 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ ··· 3204 2943 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ 3205 2944 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 3206 2945 3207 - /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3208 - #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5,\ 3209 - t, 65, 52, 0, 1, 36, 20, 0, 1, 4) 2946 + /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2947 + #define DEV2G5_MAC_ADV_CHK_CFG(t) \ 2948 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\ 2949 + 4) 3210 2950 3211 2951 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) 3212 2952 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ ··· 3215 2953 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ 3216 2954 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 3217 2955 3218 - /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 3219 - #define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5,\ 3220 - t, 65, 52, 0, 1, 36, 24, 0, 1, 4) 2956 + /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 2957 + #define DEV2G5_MAC_IFG_CFG(t) \ 2958 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\ 2959 + 4) 3221 2960 3222 2961 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) 3223 2962 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ ··· 3244 2981 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ 3245 2982 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 3246 2983 3247 - /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 3248 - #define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5,\ 3249 - t, 65, 52, 0, 1, 36, 28, 0, 1, 4) 2984 + /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 2985 + #define DEV2G5_MAC_HDX_CFG(t) \ 2986 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\ 2987 + 4) 3250 2988 3251 2989 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) 3252 2990 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ ··· 3279 3015 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ 3280 3016 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3281 3017 3282 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 3283 - #define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5,\ 3284 - t, 65, 88, 0, 1, 68, 0, 0, 1, 4) 3018 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 3019 + #define DEV2G5_PCS1G_CFG(t) \ 3020 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \ 3021 + 4) 3285 3022 3286 3023 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) 3287 3024 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ ··· 3302 3037 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ 3303 3038 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3304 3039 3305 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 3306 - #define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5,\ 3307 - t, 65, 88, 0, 1, 68, 4, 0, 1, 4) 3040 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 3041 + #define DEV2G5_PCS1G_MODE_CFG(t) \ 3042 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \ 3043 + 4) 3308 3044 3309 3045 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) 3310 3046 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ ··· 3325 3059 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 3326 3060 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3327 3061 3328 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 3329 - #define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5,\ 3330 - t, 65, 88, 0, 1, 68, 8, 0, 1, 4) 3062 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 3063 + #define DEV2G5_PCS1G_SD_CFG(t) \ 3064 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \ 3065 + 4) 3331 3066 3332 3067 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) 3333 3068 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ ··· 3348 3081 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ 3349 3082 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3350 3083 3351 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 3352 - #define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5,\ 3353 - t, 65, 88, 0, 1, 68, 12, 0, 1, 4) 3084 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 3085 + #define DEV2G5_PCS1G_ANEG_CFG(t) \ 3086 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\ 3087 + 4) 3354 3088 3355 3089 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 3356 3090 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ ··· 3377 3109 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ 3378 3110 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3379 3111 3380 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 3381 - #define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5,\ 3382 - t, 65, 88, 0, 1, 68, 20, 0, 1, 4) 3112 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 3113 + #define DEV2G5_PCS1G_LB_CFG(t) \ 3114 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\ 3115 + 4) 3383 3116 3384 3117 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) 3385 3118 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ ··· 3400 3131 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ 3401 3132 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3402 3133 3403 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 3404 - #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5,\ 3405 - t, 65, 88, 0, 1, 68, 32, 0, 1, 4) 3134 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 3135 + #define DEV2G5_PCS1G_ANEG_STATUS(t) \ 3136 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\ 3137 + 4) 3406 3138 3407 3139 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) 3408 3140 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ ··· 3429 3159 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 3430 3160 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3431 3161 3432 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 3433 - #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5,\ 3434 - t, 65, 88, 0, 1, 68, 40, 0, 1, 4) 3162 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 3163 + #define DEV2G5_PCS1G_LINK_STATUS(t) \ 3164 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\ 3165 + 4) 3435 3166 3436 3167 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) 3437 3168 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ ··· 3458 3187 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 3459 3188 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3460 3189 3461 - /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 3462 - #define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5,\ 3463 - t, 65, 88, 0, 1, 68, 48, 0, 1, 4) 3190 + /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 3191 + #define DEV2G5_PCS1G_STICKY(t) \ 3192 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\ 3193 + 4) 3464 3194 3465 3195 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 3466 3196 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ ··· 3475 3203 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ 3476 3204 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3477 3205 3478 - /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 3479 - #define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5,\ 3480 - t, 65, 164, 0, 1, 4, 0, 0, 1, 4) 3206 + /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 3207 + #define DEV2G5_PCS_FX100_CFG(t) \ 3208 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \ 3209 + 4) 3481 3210 3482 3211 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) 3483 3212 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ ··· 3558 3285 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ 3559 3286 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3560 3287 3561 - /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 3562 - #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5,\ 3563 - t, 65, 168, 0, 1, 4, 0, 0, 1, 4) 3288 + /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 3289 + #define DEV2G5_PCS_FX100_STATUS(t) \ 3290 + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \ 3291 + 4) 3564 3292 3565 3293 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) 3566 3294 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ ··· 3611 3337 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ 3612 3338 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3613 3339 3614 - /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3615 - #define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G,\ 3616 - t, 13, 0, 0, 1, 60, 0, 0, 1, 4) 3340 + /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3341 + #define DEV5G_MAC_ENA_CFG(t) \ 3342 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4) 3617 3343 3618 3344 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) 3619 3345 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ ··· 3627 3353 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ 3628 3354 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3629 3355 3630 - /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3631 - #define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G,\ 3632 - t, 13, 0, 0, 1, 60, 8, 0, 1, 4) 3356 + /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3357 + #define DEV5G_MAC_MAXLEN_CFG(t) \ 3358 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4) 3633 3359 3634 3360 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 3635 3361 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ ··· 3643 3369 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3644 3370 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3645 3371 3646 - /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3647 - #define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G,\ 3648 - t, 13, 0, 0, 1, 60, 28, 0, 1, 4) 3372 + /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3373 + #define DEV5G_MAC_ADV_CHK_CFG(t) \ 3374 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1, \ 3375 + 4) 3649 3376 3650 3377 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 3651 3378 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ ··· 3690 3415 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 3691 3416 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3692 3417 3693 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 3694 - #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3695 - t, 13, 60, 0, 1, 312, 0, 0, 1, 4) 3696 - 3697 - /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 3698 - #define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3699 - t, 13, 60, 0, 1, 312, 4, 0, 1, 4) 3700 - 3701 - /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 3702 - #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ 3703 - t, 13, 60, 0, 1, 312, 8, 0, 1, 4) 3704 - 3705 - /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 3706 - #define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3707 - t, 13, 60, 0, 1, 312, 12, 0, 1, 4) 3708 - 3709 - /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 3710 - #define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3711 - t, 13, 60, 0, 1, 312, 16, 0, 1, 4) 3712 - 3713 - /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 3714 - #define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3715 - t, 13, 60, 0, 1, 312, 20, 0, 1, 4) 3716 - 3717 - /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 3718 - #define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3719 - t, 13, 60, 0, 1, 312, 24, 0, 1, 4) 3720 - 3721 - /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 3722 - #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3723 - t, 13, 60, 0, 1, 312, 28, 0, 1, 4) 3724 - 3725 - /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 3726 - #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ 3727 - t, 13, 60, 0, 1, 312, 32, 0, 1, 4) 3728 - 3729 - /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 3730 - #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3731 - t, 13, 60, 0, 1, 312, 36, 0, 1, 4) 3732 - 3733 - /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3734 - #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3735 - t, 13, 60, 0, 1, 312, 40, 0, 1, 4) 3736 - 3737 - /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 3738 - #define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3739 - t, 13, 60, 0, 1, 312, 44, 0, 1, 4) 3740 - 3741 - /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 3742 - #define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ 3743 - t, 13, 60, 0, 1, 312, 48, 0, 1, 4) 3744 - 3745 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 3746 - #define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3747 - t, 13, 60, 0, 1, 312, 52, 0, 1, 4) 3748 - 3749 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 3750 - #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3751 - t, 13, 60, 0, 1, 312, 56, 0, 1, 4) 3752 - 3753 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 3754 - #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3755 - t, 13, 60, 0, 1, 312, 60, 0, 1, 4) 3756 - 3757 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 3758 - #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3759 - t, 13, 60, 0, 1, 312, 64, 0, 1, 4) 3760 - 3761 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 3762 - #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3763 - t, 13, 60, 0, 1, 312, 68, 0, 1, 4) 3764 - 3765 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 3766 - #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3767 - t, 13, 60, 0, 1, 312, 72, 0, 1, 4) 3768 - 3769 - /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 3770 - #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3771 - t, 13, 60, 0, 1, 312, 76, 0, 1, 4) 3772 - 3773 - /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 3774 - #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G,\ 3775 - t, 13, 60, 0, 1, 312, 80, 0, 1, 4) 3776 - 3777 - /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 3778 - #define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3779 - t, 13, 60, 0, 1, 312, 84, 0, 1, 4) 3780 - 3781 - /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 3782 - #define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3783 - t, 13, 60, 0, 1, 312, 88, 0, 1, 4) 3784 - 3785 - /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 3786 - #define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3787 - t, 13, 60, 0, 1, 312, 92, 0, 1, 4) 3788 - 3789 - /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 3790 - #define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3791 - t, 13, 60, 0, 1, 312, 96, 0, 1, 4) 3792 - 3793 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 3794 - #define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3795 - t, 13, 60, 0, 1, 312, 100, 0, 1, 4) 3796 - 3797 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 3798 - #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3799 - t, 13, 60, 0, 1, 312, 104, 0, 1, 4) 3800 - 3801 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 3802 - #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3803 - t, 13, 60, 0, 1, 312, 108, 0, 1, 4) 3804 - 3805 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 3806 - #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3807 - t, 13, 60, 0, 1, 312, 112, 0, 1, 4) 3808 - 3809 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 3810 - #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3811 - t, 13, 60, 0, 1, 312, 116, 0, 1, 4) 3812 - 3813 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 3814 - #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3815 - t, 13, 60, 0, 1, 312, 120, 0, 1, 4) 3816 - 3817 - /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 3818 - #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3819 - t, 13, 60, 0, 1, 312, 124, 0, 1, 4) 3820 - 3821 - /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 3822 - #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ 3823 - t, 13, 60, 0, 1, 312, 128, 0, 1, 4) 3824 - 3825 - /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 3826 - #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3827 - t, 13, 60, 0, 1, 312, 132, 0, 1, 4) 3828 - 3829 - /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 3830 - #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3831 - t, 13, 60, 0, 1, 312, 136, 0, 1, 4) 3832 - 3833 - /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 3834 - #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3835 - t, 13, 60, 0, 1, 312, 140, 0, 1, 4) 3836 - 3837 - /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 3838 - #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3839 - t, 13, 60, 0, 1, 312, 144, 0, 1, 4) 3840 - 3841 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 3842 - #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3843 - t, 13, 60, 0, 1, 312, 148, 0, 1, 4) 3844 - 3845 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 3846 - #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3847 - t, 13, 60, 0, 1, 312, 152, 0, 1, 4) 3848 - 3849 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 3850 - #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ 3851 - t, 13, 60, 0, 1, 312, 156, 0, 1, 4) 3852 - 3853 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 3854 - #define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3855 - t, 13, 60, 0, 1, 312, 160, 0, 1, 4) 3856 - 3857 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 3858 - #define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3859 - t, 13, 60, 0, 1, 312, 164, 0, 1, 4) 3860 - 3861 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 3862 - #define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3863 - t, 13, 60, 0, 1, 312, 168, 0, 1, 4) 3864 - 3865 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 3866 - #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3867 - t, 13, 60, 0, 1, 312, 172, 0, 1, 4) 3868 - 3869 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 3870 - #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3871 - t, 13, 60, 0, 1, 312, 176, 0, 1, 4) 3872 - 3873 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 3874 - #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ 3875 - t, 13, 60, 0, 1, 312, 180, 0, 1, 4) 3876 - 3877 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 3878 - #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3879 - t, 13, 60, 0, 1, 312, 184, 0, 1, 4) 3880 - 3881 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3882 - #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3883 - t, 13, 60, 0, 1, 312, 188, 0, 1, 4) 3884 - 3885 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 3886 - #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3887 - t, 13, 60, 0, 1, 312, 192, 0, 1, 4) 3888 - 3889 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 3890 - #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ 3891 - t, 13, 60, 0, 1, 312, 196, 0, 1, 4) 3892 - 3893 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 3894 - #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3895 - t, 13, 60, 0, 1, 312, 200, 0, 1, 4) 3896 - 3897 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 3898 - #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3899 - t, 13, 60, 0, 1, 312, 204, 0, 1, 4) 3900 - 3901 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 3902 - #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3903 - t, 13, 60, 0, 1, 312, 208, 0, 1, 4) 3904 - 3905 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 3906 - #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3907 - t, 13, 60, 0, 1, 312, 212, 0, 1, 4) 3908 - 3909 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 3910 - #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3911 - t, 13, 60, 0, 1, 312, 216, 0, 1, 4) 3912 - 3913 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 3914 - #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3915 - t, 13, 60, 0, 1, 312, 220, 0, 1, 4) 3916 - 3917 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 3918 - #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3919 - t, 13, 60, 0, 1, 312, 224, 0, 1, 4) 3920 - 3921 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 3922 - #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3923 - t, 13, 60, 0, 1, 312, 228, 0, 1, 4) 3924 - 3925 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 3926 - #define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3927 - t, 13, 60, 0, 1, 312, 232, 0, 1, 4) 3928 - 3929 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 3930 - #define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3931 - t, 13, 60, 0, 1, 312, 236, 0, 1, 4) 3932 - 3933 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 3934 - #define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3935 - t, 13, 60, 0, 1, 312, 240, 0, 1, 4) 3936 - 3937 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 3938 - #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3939 - t, 13, 60, 0, 1, 312, 244, 0, 1, 4) 3940 - 3941 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 3942 - #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3943 - t, 13, 60, 0, 1, 312, 248, 0, 1, 4) 3944 - 3945 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 3946 - #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3947 - t, 13, 60, 0, 1, 312, 252, 0, 1, 4) 3948 - 3949 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 3950 - #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3951 - t, 13, 60, 0, 1, 312, 256, 0, 1, 4) 3952 - 3953 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 3954 - #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3955 - t, 13, 60, 0, 1, 312, 260, 0, 1, 4) 3956 - 3957 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 3958 - #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3959 - t, 13, 60, 0, 1, 312, 264, 0, 1, 4) 3960 - 3961 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 3962 - #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3963 - t, 13, 60, 0, 1, 312, 268, 0, 1, 4) 3964 - 3965 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 3966 - #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ 3967 - t, 13, 60, 0, 1, 312, 272, 0, 1, 4) 3968 - 3969 - /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 3970 - #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3971 - t, 13, 60, 0, 1, 312, 276, 0, 1, 4) 3972 - 3973 - /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 3974 - #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3975 - t, 13, 60, 0, 1, 312, 280, 0, 1, 4) 3976 - 3977 - /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 3978 - #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G,\ 3979 - t, 13, 60, 0, 1, 312, 284, 0, 1, 4) 3980 - 3981 - /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 3982 - #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G,\ 3983 - t, 13, 60, 0, 1, 312, 288, 0, 1, 4) 3984 - 3985 - /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 3986 - #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G,\ 3987 - t, 13, 60, 0, 1, 312, 292, 0, 1, 4) 3988 - 3989 - /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 3990 - #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3991 - t, 13, 60, 0, 1, 312, 296, 0, 1, 4) 3992 - 3993 - /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 3994 - #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3995 - t, 13, 60, 0, 1, 312, 300, 0, 1, 4) 3996 - 3997 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 3998 - #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3999 - t, 13, 60, 0, 1, 312, 304, 0, 1, 4) 4000 - 4001 - /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 4002 - #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ 4003 - t, 13, 60, 0, 1, 312, 308, 0, 1, 4) 4004 - 4005 - /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 4006 - #define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4007 - t, 13, 372, 0, 1, 64, 0, 0, 1, 4) 4008 - 4009 - /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 4010 - #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4011 - t, 13, 372, 0, 1, 64, 4, 0, 1, 4) 3418 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 3419 + #define DEV5G_RX_SYMBOL_ERR_CNT(t) \ 3420 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1, \ 3421 + 4) 3422 + 3423 + /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 3424 + #define DEV5G_RX_PAUSE_CNT(t) \ 3425 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1, \ 3426 + 4) 3427 + 3428 + /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 3429 + #define DEV5G_RX_UNSUP_OPCODE_CNT(t) \ 3430 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1, \ 3431 + 4) 3432 + 3433 + /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 3434 + #define DEV5G_RX_UC_CNT(t) \ 3435 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \ 3436 + 4) 3437 + 3438 + /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 3439 + #define DEV5G_RX_MC_CNT(t) \ 3440 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \ 3441 + 4) 3442 + 3443 + /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 3444 + #define DEV5G_RX_BC_CNT(t) \ 3445 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \ 3446 + 4) 3447 + 3448 + /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 3449 + #define DEV5G_RX_CRC_ERR_CNT(t) \ 3450 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \ 3451 + 4) 3452 + 3453 + /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 3454 + #define DEV5G_RX_UNDERSIZE_CNT(t) \ 3455 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \ 3456 + 4) 3457 + 3458 + /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 3459 + #define DEV5G_RX_FRAGMENTS_CNT(t) \ 3460 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \ 3461 + 4) 3462 + 3463 + /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 3464 + #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) \ 3465 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \ 3466 + 4) 3467 + 3468 + /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3469 + #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ 3470 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \ 3471 + 4) 3472 + 3473 + /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 3474 + #define DEV5G_RX_OVERSIZE_CNT(t) \ 3475 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \ 3476 + 4) 3477 + 3478 + /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 3479 + #define DEV5G_RX_JABBERS_CNT(t) \ 3480 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \ 3481 + 4) 3482 + 3483 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 3484 + #define DEV5G_RX_SIZE64_CNT(t) \ 3485 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \ 3486 + 4) 3487 + 3488 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 3489 + #define DEV5G_RX_SIZE65TO127_CNT(t) \ 3490 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \ 3491 + 4) 3492 + 3493 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 3494 + #define DEV5G_RX_SIZE128TO255_CNT(t) \ 3495 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \ 3496 + 4) 3497 + 3498 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 3499 + #define DEV5G_RX_SIZE256TO511_CNT(t) \ 3500 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \ 3501 + 4) 3502 + 3503 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 3504 + #define DEV5G_RX_SIZE512TO1023_CNT(t) \ 3505 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \ 3506 + 4) 3507 + 3508 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 3509 + #define DEV5G_RX_SIZE1024TO1518_CNT(t) \ 3510 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \ 3511 + 4) 3512 + 3513 + /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 3514 + #define DEV5G_RX_SIZE1519TOMAX_CNT(t) \ 3515 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \ 3516 + 4) 3517 + 3518 + /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 3519 + #define DEV5G_RX_IPG_SHRINK_CNT(t) \ 3520 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \ 3521 + 4) 3522 + 3523 + /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 3524 + #define DEV5G_TX_PAUSE_CNT(t) \ 3525 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \ 3526 + 4) 3527 + 3528 + /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 3529 + #define DEV5G_TX_UC_CNT(t) \ 3530 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \ 3531 + 4) 3532 + 3533 + /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 3534 + #define DEV5G_TX_MC_CNT(t) \ 3535 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \ 3536 + 4) 3537 + 3538 + /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 3539 + #define DEV5G_TX_BC_CNT(t) \ 3540 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \ 3541 + 4) 3542 + 3543 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 3544 + #define DEV5G_TX_SIZE64_CNT(t) \ 3545 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\ 3546 + 4) 3547 + 3548 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 3549 + #define DEV5G_TX_SIZE65TO127_CNT(t) \ 3550 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\ 3551 + 4) 3552 + 3553 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 3554 + #define DEV5G_TX_SIZE128TO255_CNT(t) \ 3555 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\ 3556 + 4) 3557 + 3558 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 3559 + #define DEV5G_TX_SIZE256TO511_CNT(t) \ 3560 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\ 3561 + 4) 3562 + 3563 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 3564 + #define DEV5G_TX_SIZE512TO1023_CNT(t) \ 3565 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\ 3566 + 4) 3567 + 3568 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 3569 + #define DEV5G_TX_SIZE1024TO1518_CNT(t) \ 3570 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\ 3571 + 4) 3572 + 3573 + /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 3574 + #define DEV5G_TX_SIZE1519TOMAX_CNT(t) \ 3575 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\ 3576 + 4) 3577 + 3578 + /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 3579 + #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) \ 3580 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\ 3581 + 4) 3582 + 3583 + /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 3584 + #define DEV5G_RX_TAGGED_FRMS_CNT(t) \ 3585 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\ 3586 + 4) 3587 + 3588 + /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 3589 + #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) \ 3590 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\ 3591 + 4) 3592 + 3593 + /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 3594 + #define DEV5G_TX_TAGGED_FRMS_CNT(t) \ 3595 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\ 3596 + 4) 3597 + 3598 + /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 3599 + #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) \ 3600 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\ 3601 + 4) 3602 + 3603 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 3604 + #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) \ 3605 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\ 3606 + 4) 3607 + 3608 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 3609 + #define DEV5G_PMAC_RX_PAUSE_CNT(t) \ 3610 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\ 3611 + 4) 3612 + 3613 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 3614 + #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) \ 3615 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\ 3616 + 4) 3617 + 3618 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 3619 + #define DEV5G_PMAC_RX_UC_CNT(t) \ 3620 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\ 3621 + 4) 3622 + 3623 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 3624 + #define DEV5G_PMAC_RX_MC_CNT(t) \ 3625 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\ 3626 + 4) 3627 + 3628 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 3629 + #define DEV5G_PMAC_RX_BC_CNT(t) \ 3630 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\ 3631 + 4) 3632 + 3633 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 3634 + #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) \ 3635 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\ 3636 + 4) 3637 + 3638 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 3639 + #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) \ 3640 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\ 3641 + 4) 3642 + 3643 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 3644 + #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) \ 3645 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\ 3646 + 4) 3647 + 3648 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 3649 + #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) \ 3650 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\ 3651 + 4) 3652 + 3653 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3654 + #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ 3655 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\ 3656 + 4) 3657 + 3658 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 3659 + #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) \ 3660 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\ 3661 + 4) 3662 + 3663 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 3664 + #define DEV5G_PMAC_RX_JABBERS_CNT(t) \ 3665 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\ 3666 + 4) 3667 + 3668 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 3669 + #define DEV5G_PMAC_RX_SIZE64_CNT(t) \ 3670 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\ 3671 + 4) 3672 + 3673 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 3674 + #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) \ 3675 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\ 3676 + 4) 3677 + 3678 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 3679 + #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) \ 3680 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\ 3681 + 4) 3682 + 3683 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 3684 + #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) \ 3685 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\ 3686 + 4) 3687 + 3688 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 3689 + #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) \ 3690 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\ 3691 + 4) 3692 + 3693 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 3694 + #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) \ 3695 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\ 3696 + 4) 3697 + 3698 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 3699 + #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) \ 3700 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\ 3701 + 4) 3702 + 3703 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 3704 + #define DEV5G_PMAC_TX_PAUSE_CNT(t) \ 3705 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\ 3706 + 4) 3707 + 3708 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 3709 + #define DEV5G_PMAC_TX_UC_CNT(t) \ 3710 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\ 3711 + 4) 3712 + 3713 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 3714 + #define DEV5G_PMAC_TX_MC_CNT(t) \ 3715 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\ 3716 + 4) 3717 + 3718 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 3719 + #define DEV5G_PMAC_TX_BC_CNT(t) \ 3720 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\ 3721 + 4) 3722 + 3723 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 3724 + #define DEV5G_PMAC_TX_SIZE64_CNT(t) \ 3725 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\ 3726 + 4) 3727 + 3728 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 3729 + #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) \ 3730 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\ 3731 + 4) 3732 + 3733 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 3734 + #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) \ 3735 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\ 3736 + 4) 3737 + 3738 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 3739 + #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) \ 3740 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\ 3741 + 4) 3742 + 3743 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 3744 + #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) \ 3745 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\ 3746 + 4) 3747 + 3748 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 3749 + #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) \ 3750 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\ 3751 + 4) 3752 + 3753 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 3754 + #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) \ 3755 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\ 3756 + 4) 3757 + 3758 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 3759 + #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) \ 3760 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\ 3761 + 4) 3762 + 3763 + /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 3764 + #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) \ 3765 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\ 3766 + 4) 3767 + 3768 + /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 3769 + #define DEV5G_MM_RX_SMD_ERR_CNT(t) \ 3770 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\ 3771 + 4) 3772 + 3773 + /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 3774 + #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) \ 3775 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\ 3776 + 4) 3777 + 3778 + /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 3779 + #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) \ 3780 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\ 3781 + 4) 3782 + 3783 + /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 3784 + #define DEV5G_MM_TX_PFRAGMENT_CNT(t) \ 3785 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\ 3786 + 4) 3787 + 3788 + /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 3789 + #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) \ 3790 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\ 3791 + 4) 3792 + 3793 + /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 3794 + #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) \ 3795 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\ 3796 + 4) 3797 + 3798 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 3799 + #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) \ 3800 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\ 3801 + 4) 3802 + 3803 + /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 3804 + #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) \ 3805 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\ 3806 + 4) 3807 + 3808 + /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 3809 + #define DEV5G_RX_IN_BYTES_CNT(t) \ 3810 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1, \ 3811 + 4) 3812 + 3813 + /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 3814 + #define DEV5G_RX_IN_BYTES_MSB_CNT(t) \ 3815 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1, \ 3816 + 4) 4012 3817 4013 3818 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) 4014 3819 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ ··· 4096 3741 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 4097 3742 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 4098 3743 4099 - /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 4100 - #define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4101 - t, 13, 372, 0, 1, 64, 8, 0, 1, 4) 3744 + /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 3745 + #define DEV5G_RX_OK_BYTES_CNT(t) \ 3746 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1, \ 3747 + 4) 4102 3748 4103 - /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 4104 - #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4105 - t, 13, 372, 0, 1, 64, 12, 0, 1, 4) 3749 + /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 3750 + #define DEV5G_RX_OK_BYTES_MSB_CNT(t) \ 3751 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \ 3752 + 4) 4106 3753 4107 3754 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4108 3755 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ ··· 4112 3755 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 4113 3756 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 4114 3757 4115 - /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 4116 - #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4117 - t, 13, 372, 0, 1, 64, 16, 0, 1, 4) 3758 + /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 3759 + #define DEV5G_RX_BAD_BYTES_CNT(t) \ 3760 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \ 3761 + 4) 4118 3762 4119 - /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 4120 - #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4121 - t, 13, 372, 0, 1, 64, 20, 0, 1, 4) 3763 + /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 3764 + #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) \ 3765 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \ 3766 + 4) 4122 3767 4123 3768 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 4124 3769 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ ··· 4128 3769 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 4129 3770 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 4130 3771 4131 - /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 4132 - #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4133 - t, 13, 372, 0, 1, 64, 24, 0, 1, 4) 3772 + /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 3773 + #define DEV5G_TX_OUT_BYTES_CNT(t) \ 3774 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \ 3775 + 4) 4134 3776 4135 - /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 4136 - #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4137 - t, 13, 372, 0, 1, 64, 28, 0, 1, 4) 3777 + /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 3778 + #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) \ 3779 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \ 3780 + 4) 4138 3781 4139 3782 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) 4140 3783 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ ··· 4144 3783 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 4145 3784 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 4146 3785 4147 - /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 4148 - #define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4149 - t, 13, 372, 0, 1, 64, 32, 0, 1, 4) 3786 + /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 3787 + #define DEV5G_TX_OK_BYTES_CNT(t) \ 3788 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \ 3789 + 4) 4150 3790 4151 - /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 4152 - #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4153 - t, 13, 372, 0, 1, 64, 36, 0, 1, 4) 3791 + /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 3792 + #define DEV5G_TX_OK_BYTES_MSB_CNT(t) \ 3793 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \ 3794 + 4) 4154 3795 4155 3796 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4156 3797 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ ··· 4160 3797 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 4161 3798 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 4162 3799 4163 - /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 4164 - #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4165 - t, 13, 372, 0, 1, 64, 40, 0, 1, 4) 3800 + /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 3801 + #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) \ 3802 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \ 3803 + 4) 4166 3804 4167 - /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 4168 - #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4169 - t, 13, 372, 0, 1, 64, 44, 0, 1, 4) 3805 + /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 3806 + #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) \ 3807 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \ 3808 + 4) 4170 3809 4171 3810 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4172 3811 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ ··· 4176 3811 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 4177 3812 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 4178 3813 4179 - /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 4180 - #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4181 - t, 13, 372, 0, 1, 64, 48, 0, 1, 4) 3814 + /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 3815 + #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) \ 3816 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \ 3817 + 4) 4182 3818 4183 - /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 4184 - #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4185 - t, 13, 372, 0, 1, 64, 52, 0, 1, 4) 3819 + /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 3820 + #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) \ 3821 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \ 3822 + 4) 4186 3823 4187 3824 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 4188 3825 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ ··· 4192 3825 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 4193 3826 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 4194 3827 4195 - /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 4196 - #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 4197 - t, 13, 372, 0, 1, 64, 56, 0, 1, 4) 3828 + /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 3829 + #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) \ 3830 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \ 3831 + 4) 4198 3832 4199 - /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 4200 - #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 4201 - t, 13, 372, 0, 1, 64, 60, 0, 1, 4) 3833 + /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 3834 + #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) \ 3835 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \ 3836 + 4) 4202 3837 4203 3838 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4204 3839 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ ··· 4208 3839 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 4209 3840 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 4210 3841 4211 - /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 4212 - #define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G,\ 4213 - t, 13, 436, 0, 1, 52, 0, 0, 1, 4) 3842 + /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3843 + #define DEV5G_DEV_RST_CTRL(t) \ 3844 + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1, \ 3845 + 4) 4214 3846 4215 3847 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 4216 3848 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ ··· 4267 3897 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 4268 3898 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 4269 3899 4270 - /* DSM:RAM_CTRL:RAM_INIT */ 4271 - #define DSM_RAM_INIT __REG(TARGET_DSM,\ 4272 - 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 3900 + /* DSM:RAM_CTRL:RAM_INIT */ 3901 + #define DSM_RAM_INIT \ 3902 + __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 4273 3903 4274 3904 #define DSM_RAM_INIT_RAM_INIT BIT(1) 4275 3905 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ ··· 4283 3913 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4284 3914 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) 4285 3915 4286 - /* DSM:CFG:BUF_CFG */ 4287 - #define DSM_BUF_CFG(r) __REG(TARGET_DSM,\ 4288 - 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) 3916 + /* DSM:CFG:BUF_CFG */ 3917 + #define DSM_BUF_CFG(r) \ 3918 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, \ 3919 + regs->rcnt[RC_DSM_BUF_CFG], 4) 4289 3920 4290 3921 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) 4291 3922 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ ··· 4312 3941 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ 4313 3942 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 4314 3943 4315 - /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 4316 - #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM,\ 4317 - 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) 3944 + /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 3945 + #define DSM_DEV_TX_STOP_WM_CFG(r) \ 3946 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \ 3947 + regs->rcnt[RC_DSM_DEV_TX_STOP_WM_CFG], 4) 4318 3948 4319 3949 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) 4320 3950 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ ··· 4341 3969 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ 4342 3970 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 4343 3971 4344 - /* DSM:CFG:RX_PAUSE_CFG */ 4345 - #define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM,\ 4346 - 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4) 3972 + /* DSM:CFG:RX_PAUSE_CFG */ 3973 + #define DSM_RX_PAUSE_CFG(r) \ 3974 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, \ 3975 + regs->rcnt[RC_DSM_RX_PAUSE_CFG], 4) 4347 3976 4348 3977 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) 4349 3978 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ ··· 4358 3985 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ 4359 3986 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 4360 3987 4361 - /* DSM:CFG:MAC_CFG */ 4362 - #define DSM_MAC_CFG(r) __REG(TARGET_DSM,\ 4363 - 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4) 3988 + /* DSM:CFG:MAC_CFG */ 3989 + #define DSM_MAC_CFG(r) \ 3990 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, \ 3991 + regs->rcnt[RC_DSM_MAC_CFG], 4) 4364 3992 4365 3993 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) 4366 3994 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ ··· 4387 4013 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ 4388 4014 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4389 4015 4390 - /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 4391 - #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM,\ 4392 - 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4) 4016 + /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 4017 + #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) \ 4018 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, \ 4019 + regs->rcnt[RC_DSM_MAC_ADDR_BASE_HIGH_CFG], 4) 4393 4020 4394 4021 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) 4395 4022 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ ··· 4398 4023 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ 4399 4024 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4400 4025 4401 - /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 4402 - #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM,\ 4403 - 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4) 4026 + /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 4027 + #define DSM_MAC_ADDR_BASE_LOW_CFG(r) \ 4028 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, \ 4029 + regs->rcnt[RC_DSM_MAC_ADDR_BASE_LOW_CFG], 4) 4404 4030 4405 4031 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) 4406 4032 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ ··· 4409 4033 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ 4410 4034 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4411 4035 4412 - /* DSM:CFG:TAXI_CAL_CFG */ 4413 - #define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM,\ 4414 - 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4) 4036 + /* DSM:CFG:TAXI_CAL_CFG */ 4037 + #define DSM_TAXI_CAL_CFG(r) \ 4038 + __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, \ 4039 + regs->rcnt[RC_DSM_TAXI_CAL_CFG], 4) 4415 4040 4416 4041 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) 4417 4042 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ ··· 4444 4067 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ 4445 4068 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4446 4069 4447 - /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ 4448 - #define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\ 4449 - 0, 1, 149504, g, 138, 8, 0, r, 2, 4) 4070 + /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ 4071 + #define EACL_VCAP_ES2_KEY_SEL(g, r) \ 4072 + __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ 4073 + g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4) 4450 4074 4451 4075 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) 4452 4076 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ ··· 4473 4095 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ 4474 4096 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4475 4097 4476 - /* EACL:CNT_TBL:ES2_CNT */ 4477 - #define EACL_ES2_CNT(g) __REG(TARGET_EACL,\ 4478 - 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4) 4098 + /* EACL:CNT_TBL:ES2_CNT */ 4099 + #define EACL_ES2_CNT(g) \ 4100 + __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g, \ 4101 + regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4) 4479 4102 4480 - /* EACL:POL_CFG:POL_EACL_CFG */ 4481 - #define EACL_POL_EACL_CFG __REG(TARGET_EACL,\ 4482 - 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4) 4103 + /* EACL:POL_CFG:POL_EACL_CFG */ 4104 + #define EACL_POL_EACL_CFG \ 4105 + __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \ 4106 + 0, 1, 4) 4483 4107 4484 4108 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) 4485 4109 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ ··· 4519 4139 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ 4520 4140 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4521 4141 4522 - /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ 4523 - #define EACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_EACL,\ 4524 - 0, 1, 118696, 0, 1, 8, 0, r, 2, 4) 4142 + /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ 4143 + #define EACL_SEC_LOOKUP_STICKY(r) \ 4144 + __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0, \ 4145 + r, 2, 4) 4525 4146 4526 4147 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 4527 4148 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ ··· 4572 4191 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 4573 4192 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4574 4193 4575 - /* EACL:RAM_CTRL:RAM_INIT */ 4576 - #define EACL_RAM_INIT __REG(TARGET_EACL,\ 4577 - 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4) 4194 + /* EACL:RAM_CTRL:RAM_INIT */ 4195 + #define EACL_RAM_INIT \ 4196 + __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \ 4197 + 1, 4) 4578 4198 4579 4199 #define EACL_RAM_INIT_RAM_INIT BIT(1) 4580 4200 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ ··· 4589 4207 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4590 4208 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4591 4209 4592 - /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 4593 - #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA,\ 4594 - 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 4210 + /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 4211 + #define FDMA_CH_ACTIVATE \ 4212 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1, \ 4213 + 4) 4595 4214 4596 4215 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 4597 4216 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ ··· 4600 4217 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 4601 4218 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4602 4219 4603 - /* FDMA:FDMA:FDMA_CH_RELOAD */ 4604 - #define FDMA_CH_RELOAD __REG(TARGET_FDMA,\ 4605 - 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 4220 + /* FDMA:FDMA:FDMA_CH_RELOAD */ 4221 + #define FDMA_CH_RELOAD \ 4222 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1, \ 4223 + 4) 4606 4224 4607 4225 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 4608 4226 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ ··· 4611 4227 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 4612 4228 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 4613 4229 4614 - /* FDMA:FDMA:FDMA_CH_DISABLE */ 4615 - #define FDMA_CH_DISABLE __REG(TARGET_FDMA,\ 4616 - 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 4230 + /* FDMA:FDMA:FDMA_CH_DISABLE */ 4231 + #define FDMA_CH_DISABLE \ 4232 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1, \ 4233 + 4) 4617 4234 4618 4235 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 4619 4236 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ ··· 4622 4237 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 4623 4238 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 4624 4239 4625 - /* FDMA:FDMA:FDMA_DCB_LLP */ 4626 - #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA,\ 4627 - 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 4240 + /* FDMA:FDMA:FDMA_DCB_LLP */ 4241 + #define FDMA_DCB_LLP(r) \ 4242 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \ 4243 + 4) 4628 4244 4629 - /* FDMA:FDMA:FDMA_DCB_LLP1 */ 4630 - #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA,\ 4631 - 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 4245 + /* FDMA:FDMA:FDMA_DCB_LLP1 */ 4246 + #define FDMA_DCB_LLP1(r) \ 4247 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \ 4248 + 4) 4632 4249 4633 - /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 4634 - #define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA,\ 4635 - 0, 1, 8, 0, 1, 428, 116, r, 8, 4) 4250 + /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 4251 + #define FDMA_DCB_LLP_PREV(r) \ 4252 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\ 4253 + 4) 4636 4254 4637 - /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 4638 - #define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA,\ 4639 - 0, 1, 8, 0, 1, 428, 148, r, 8, 4) 4255 + /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 4256 + #define FDMA_DCB_LLP_PREV1(r) \ 4257 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\ 4258 + 4) 4640 4259 4641 - /* FDMA:FDMA:FDMA_CH_CFG */ 4642 - #define FDMA_CH_CFG(r) __REG(TARGET_FDMA,\ 4643 - 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 4260 + /* FDMA:FDMA:FDMA_CH_CFG */ 4261 + #define FDMA_CH_CFG(r) \ 4262 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\ 4263 + 4) 4644 4264 4645 - #define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7) 4265 + #define FDMA_CH_CFG_CH_XTR_STATUS_MODE\ 4266 + BIT(regs->fpos[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE]) 4646 4267 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ 4647 - FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4268 + spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4648 4269 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ 4649 - FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4270 + spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4650 4271 4651 - #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6) 4272 + #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY\ 4273 + BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY]) 4652 4274 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 4653 - FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4275 + spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4654 4276 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 4655 - FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4277 + spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4656 4278 4657 - #define FDMA_CH_CFG_CH_INJ_PORT BIT(5) 4279 + #define FDMA_CH_CFG_CH_INJ_PORT\ 4280 + BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INJ_PORT]) 4658 4281 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 4659 - FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 4282 + spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x) 4660 4283 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 4661 - FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 4284 + spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x) 4662 4285 4663 - #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1) 4286 + #define FDMA_CH_CFG_CH_DCB_DB_CNT\ 4287 + GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1) 4664 4288 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 4665 - FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4289 + spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4666 4290 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 4667 - FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4291 + spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4668 4292 4669 4293 #define FDMA_CH_CFG_CH_MEM BIT(0) 4670 4294 #define FDMA_CH_CFG_CH_MEM_SET(x)\ ··· 4681 4287 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 4682 4288 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 4683 4289 4684 - /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 4685 - #define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA,\ 4686 - 0, 1, 8, 0, 1, 428, 256, r, 8, 4) 4290 + /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 4291 + #define FDMA_CH_TRANSLATE(r) \ 4292 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\ 4293 + 4) 4687 4294 4688 4295 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) 4689 4296 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ ··· 4692 4297 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ 4693 4298 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) 4694 4299 4695 - /* FDMA:FDMA:FDMA_XTR_CFG */ 4696 - #define FDMA_XTR_CFG __REG(TARGET_FDMA,\ 4697 - 0, 1, 8, 0, 1, 428, 364, 0, 1, 4) 4300 + /* FDMA:FDMA:FDMA_XTR_CFG */ 4301 + #define FDMA_XTR_CFG \ 4302 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\ 4303 + 4) 4698 4304 4699 4305 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) 4700 4306 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ ··· 4709 4313 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ 4710 4314 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4711 4315 4712 - /* FDMA:FDMA:FDMA_PORT_CTRL */ 4713 - #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA,\ 4714 - 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 4316 + /* FDMA:FDMA:FDMA_PORT_CTRL */ 4317 + #define FDMA_PORT_CTRL(r) \ 4318 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\ 4319 + 4) 4715 4320 4716 4321 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 4717 4322 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ ··· 4744 4347 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ 4745 4348 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4746 4349 4747 - /* FDMA:FDMA:FDMA_INTR_DCB */ 4748 - #define FDMA_INTR_DCB __REG(TARGET_FDMA,\ 4749 - 0, 1, 8, 0, 1, 428, 384, 0, 1, 4) 4350 + /* FDMA:FDMA:FDMA_INTR_DCB */ 4351 + #define FDMA_INTR_DCB \ 4352 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\ 4353 + 4) 4750 4354 4751 4355 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) 4752 4356 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ ··· 4755 4357 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ 4756 4358 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) 4757 4359 4758 - /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 4759 - #define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA,\ 4760 - 0, 1, 8, 0, 1, 428, 388, 0, 1, 4) 4360 + /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 4361 + #define FDMA_INTR_DCB_ENA \ 4362 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\ 4363 + 4) 4761 4364 4762 4365 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) 4763 4366 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ ··· 4766 4367 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ 4767 4368 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4768 4369 4769 - /* FDMA:FDMA:FDMA_INTR_DB */ 4770 - #define FDMA_INTR_DB __REG(TARGET_FDMA,\ 4771 - 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 4370 + /* FDMA:FDMA:FDMA_INTR_DB */ 4371 + #define FDMA_INTR_DB \ 4372 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\ 4373 + 4) 4772 4374 4773 4375 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) 4774 4376 #define FDMA_INTR_DB_INTR_DB_SET(x)\ ··· 4777 4377 #define FDMA_INTR_DB_INTR_DB_GET(x)\ 4778 4378 FIELD_GET(FDMA_INTR_DB_INTR_DB, x) 4779 4379 4780 - /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 4781 - #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA,\ 4782 - 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 4380 + /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 4381 + #define FDMA_INTR_DB_ENA \ 4382 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\ 4383 + 4) 4783 4384 4784 4385 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 4785 4386 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ ··· 4788 4387 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 4789 4388 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4790 4389 4791 - /* FDMA:FDMA:FDMA_INTR_ERR */ 4792 - #define FDMA_INTR_ERR __REG(TARGET_FDMA,\ 4793 - 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 4390 + /* FDMA:FDMA:FDMA_INTR_ERR */ 4391 + #define FDMA_INTR_ERR \ 4392 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\ 4393 + 4) 4794 4394 4795 4395 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) 4796 4396 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ ··· 4805 4403 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ 4806 4404 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) 4807 4405 4808 - /* FDMA:FDMA:FDMA_ERRORS */ 4809 - #define FDMA_ERRORS __REG(TARGET_FDMA,\ 4810 - 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 4406 + /* FDMA:FDMA:FDMA_ERRORS */ 4407 + #define FDMA_ERRORS \ 4408 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\ 4409 + 4) 4811 4410 4812 4411 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) 4813 4412 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ ··· 4858 4455 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ 4859 4456 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) 4860 4457 4861 - /* FDMA:FDMA:FDMA_ERRORS_2 */ 4862 - #define FDMA_ERRORS_2 __REG(TARGET_FDMA,\ 4863 - 0, 1, 8, 0, 1, 428, 416, 0, 1, 4) 4458 + /* FDMA:FDMA:FDMA_ERRORS_2 */ 4459 + #define FDMA_ERRORS_2 \ 4460 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\ 4461 + 4) 4864 4462 4865 4463 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) 4866 4464 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ ··· 4869 4465 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ 4870 4466 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4871 4467 4872 - /* FDMA:FDMA:FDMA_CTRL */ 4873 - #define FDMA_CTRL __REG(TARGET_FDMA,\ 4874 - 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) 4468 + /* FDMA:FDMA:FDMA_CTRL */ 4469 + #define FDMA_CTRL \ 4470 + __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\ 4471 + 4) 4875 4472 4876 4473 #define FDMA_CTRL_NRESET BIT(0) 4877 4474 #define FDMA_CTRL_NRESET_SET(x)\ ··· 4880 4475 #define FDMA_CTRL_NRESET_GET(x)\ 4881 4476 FIELD_GET(FDMA_CTRL_NRESET, x) 4882 4477 4883 - /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 4884 - #define GCB_CHIP_ID __REG(TARGET_GCB,\ 4885 - 0, 1, 0, 0, 1, 424, 0, 0, 1, 4) 4478 + /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 4479 + #define GCB_CHIP_ID \ 4480 + __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0, \ 4481 + 1, 4) 4886 4482 4887 4483 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) 4888 4484 #define GCB_CHIP_ID_REV_ID_SET(x)\ ··· 4909 4503 #define GCB_CHIP_ID_ONE_GET(x)\ 4910 4504 FIELD_GET(GCB_CHIP_ID_ONE, x) 4911 4505 4912 - /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 4913 - #define GCB_SOFT_RST __REG(TARGET_GCB,\ 4914 - 0, 1, 0, 0, 1, 424, 8, 0, 1, 4) 4506 + /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 4507 + #define GCB_SOFT_RST \ 4508 + __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ 4509 + regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4) 4915 4510 4511 + /* SPARX5 ONLY */ 4916 4512 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) 4917 4513 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ 4918 4514 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) ··· 4933 4525 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ 4934 4526 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4935 4527 4936 - /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 4937 - #define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB,\ 4938 - 0, 1, 0, 0, 1, 424, 20, 0, 1, 4) 4528 + /* SPARX5 ONLY */ 4529 + /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 4530 + #define GCB_HW_SGPIO_SD_CFG \ 4531 + __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \ 4532 + 1, 4) 4939 4533 4940 4534 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) 4941 4535 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ ··· 4951 4541 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ 4952 4542 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4953 4543 4954 - /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 4955 - #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB,\ 4956 - 0, 1, 0, 0, 1, 424, 24, r, 65, 4) 4544 + /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 4545 + #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) \ 4546 + __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ 4547 + regs->raddr[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG], r, \ 4548 + regs->rcnt[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG], 4) 4957 4549 4958 - #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0) 4550 + #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL\ 4551 + GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0) 4959 4552 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ 4960 - FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4553 + spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4961 4554 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ 4962 - FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4555 + spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4963 4556 4964 - /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 4965 - #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\ 4966 - 0, 1, 876, g, 3, 280, 20, 0, 1, 4) 4557 + /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 4558 + #define GCB_SIO_CLOCK(g) \ 4559 + __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g, \ 4560 + regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4) 4967 4561 4968 4562 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) 4969 4563 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ ··· 4981 4567 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ 4982 4568 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4983 4569 4984 - /* HSCH:HSCH_CFG:CIR_CFG */ 4985 - #define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\ 4986 - 0, 1, 0, g, 5040, 32, 0, 0, 1, 4) 4570 + /* HSCH:HSCH_CFG:CIR_CFG */ 4571 + #define HSCH_CIR_CFG(g) \ 4572 + __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \ 4573 + 1, 4) 4987 4574 4988 4575 #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) 4989 4576 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ ··· 4998 4583 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ 4999 4584 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) 5000 4585 5001 - /* HSCH:HSCH_CFG:EIR_CFG */ 5002 - #define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\ 5003 - 0, 1, 0, g, 5040, 32, 4, 0, 1, 4) 4586 + /* HSCH:HSCH_CFG:EIR_CFG */ 4587 + #define HSCH_EIR_CFG(g) \ 4588 + __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \ 4589 + 1, 4) 5004 4590 5005 4591 #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) 5006 4592 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ ··· 5015 4599 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ 5016 4600 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) 5017 4601 5018 - /* HSCH:HSCH_CFG:SE_CFG */ 5019 - #define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\ 5020 - 0, 1, 0, g, 5040, 32, 8, 0, 1, 4) 4602 + /* HSCH:HSCH_CFG:SE_CFG */ 4603 + #define HSCH_SE_CFG(g) \ 4604 + __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \ 4605 + 1, 4) 5021 4606 5022 - #define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6) 4607 + #define HSCH_SE_CFG_SE_DWRR_CNT\ 4608 + GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6) 5023 4609 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ 5024 - FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x) 4610 + spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x) 5025 4611 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ 5026 - FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x) 4612 + spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x) 5027 4613 5028 4614 #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) 5029 4615 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ ··· 5051 4633 #define HSCH_SE_CFG_SE_STOP_GET(x)\ 5052 4634 FIELD_GET(HSCH_SE_CFG_SE_STOP, x) 5053 4635 5054 - /* HSCH:HSCH_CFG:SE_CONNECT */ 5055 - #define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\ 5056 - 0, 1, 0, g, 5040, 32, 12, 0, 1, 4) 4636 + /* HSCH:HSCH_CFG:SE_CONNECT */ 4637 + #define HSCH_SE_CONNECT(g) \ 4638 + __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\ 4639 + 1, 4) 5057 4640 5058 - #define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0) 4641 + #define HSCH_SE_CONNECT_SE_LEAK_LINK\ 4642 + GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0) 5059 4643 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ 5060 - FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 4644 + spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 5061 4645 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ 5062 - FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 4646 + spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 5063 4647 5064 - /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 5065 - #define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\ 5066 - 0, 1, 0, g, 5040, 32, 16, 0, 1, 4) 4648 + /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 4649 + #define HSCH_SE_DLB_SENSE(g) \ 4650 + __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\ 4651 + 1, 4) 5067 4652 5068 4653 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) 5069 4654 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ ··· 5074 4653 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ 5075 4654 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 5076 4655 5077 - #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3) 4656 + #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT\ 4657 + GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3) 5078 4658 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ 5079 - FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 4659 + spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 5080 4660 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ 5081 - FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 4661 + spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 5082 4662 5083 4663 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) 5084 4664 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ ··· 5099 4677 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ 5100 4678 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 5101 4679 5102 - /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 5103 - #define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\ 5104 - 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) 4680 + /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 4681 + #define HSCH_DWRR_ENTRY(g) \ 4682 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g, \ 4683 + regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4) 5105 4684 5106 4685 #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) 5107 4686 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ ··· 5116 4693 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ 5117 4694 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 5118 4695 5119 - /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 5120 - #define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH,\ 5121 - 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) 4696 + /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 4697 + #define HSCH_HSCH_CFG_CFG \ 4698 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ 4699 + 284, 0, 1, 4) 5122 4700 5123 - #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14) 4701 + #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX\ 4702 + GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14) 5124 4703 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ 5125 - FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 4704 + spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 5126 4705 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ 5127 - FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 4706 + spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 5128 4707 5129 4708 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) 5130 4709 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ ··· 5140 4715 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ 5141 4716 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 5142 4717 5143 - /* HSCH:HSCH_MISC:SYS_CLK_PER */ 5144 - #define HSCH_SYS_CLK_PER __REG(TARGET_HSCH,\ 5145 - 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4) 4718 + /* SPARX5 ONLY */ 4719 + /* HSCH:HSCH_MISC:SYS_CLK_PER */ 4720 + #define HSCH_SYS_CLK_PER \ 4721 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ 4722 + 640, 0, 1, 4) 5146 4723 5147 4724 #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) 5148 4725 #define HSCH_SYS_CLK_PER_100PS_SET(x)\ ··· 5152 4725 #define HSCH_SYS_CLK_PER_100PS_GET(x)\ 5153 4726 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) 5154 4727 5155 - /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 5156 - #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\ 5157 - 0, 1, 161664, g, 4, 32, 0, r, 4, 4) 4728 + /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 4729 + #define HSCH_HSCH_TIMER_CFG(g, r) \ 4730 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ 4731 + 32, 0, r, 4, 4) 5158 4732 5159 4733 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) 5160 4734 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ ··· 5163 4735 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ 5164 4736 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 5165 4737 5166 - /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 5167 - #define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\ 5168 - 0, 1, 161664, g, 4, 32, 16, r, 4, 4) 4738 + /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 4739 + #define HSCH_HSCH_LEAK_CFG(g, r) \ 4740 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ 4741 + 32, 16, r, 4, 4) 5169 4742 5170 - #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1) 4743 + #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST\ 4744 + GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1) 5171 4745 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ 5172 - FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 4746 + spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 5173 4747 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ 5174 - FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 4748 + spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 5175 4749 5176 4750 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) 5177 4751 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ ··· 5181 4751 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ 5182 4752 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 5183 4753 5184 - /* HSCH:SYSTEM:FLUSH_CTRL */ 5185 - #define HSCH_FLUSH_CTRL __REG(TARGET_HSCH,\ 5186 - 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4) 4754 + /* HSCH:SYSTEM:FLUSH_CTRL */ 4755 + #define HSCH_FLUSH_CTRL \ 4756 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \ 4757 + 1, 4) 5187 4758 5188 4759 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) 5189 4760 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ ··· 5204 4773 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ 5205 4774 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) 5206 4775 5207 - #define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18) 4776 + #define HSCH_FLUSH_CTRL_FLUSH_PORT\ 4777 + GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18) 5208 4778 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ 5209 - FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 4779 + spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 5210 4780 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ 5211 - FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 4781 + spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 5212 4782 5213 4783 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) 5214 4784 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ ··· 5223 4791 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ 5224 4792 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) 5225 4793 5226 - #define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0) 4794 + #define HSCH_FLUSH_CTRL_FLUSH_HIER\ 4795 + GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0) 5227 4796 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ 5228 - FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 4797 + spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 5229 4798 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ 5230 - FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 4799 + spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 5231 4800 5232 - /* HSCH:SYSTEM:PORT_MODE */ 5233 - #define HSCH_PORT_MODE(r) __REG(TARGET_HSCH,\ 5234 - 0, 1, 184000, 0, 1, 312, 8, r, 70, 4) 4801 + /* HSCH:SYSTEM:PORT_MODE */ 4802 + #define HSCH_PORT_MODE(r) \ 4803 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \ 4804 + regs->rcnt[RC_HSCH_PORT_MODE], 4) 5235 4805 5236 4806 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) 5237 4807 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ ··· 5265 4831 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ 5266 4832 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 5267 4833 5268 - /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 5269 - #define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH,\ 5270 - 0, 1, 184000, 0, 1, 312, 288, r, 5, 4) 4834 + /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 4835 + #define HSCH_OUTB_SHARE_ENA(r) \ 4836 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288, \ 4837 + r, 5, 4) 5271 4838 5272 4839 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) 5273 4840 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ ··· 5276 4841 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ 5277 4842 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 5278 4843 5279 - /* HSCH:MMGT:RESET_CFG */ 5280 - #define HSCH_RESET_CFG __REG(TARGET_HSCH,\ 5281 - 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4) 4844 + /* HSCH:MMGT:RESET_CFG */ 4845 + #define HSCH_RESET_CFG \ 4846 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \ 4847 + 4) 5282 4848 5283 4849 #define HSCH_RESET_CFG_CORE_ENA BIT(0) 5284 4850 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ ··· 5287 4851 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ 5288 4852 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) 5289 4853 5290 - /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 5291 - #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH,\ 5292 - 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4) 4854 + /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 4855 + #define HSCH_TAS_STATEMACHINE_CFG \ 4856 + __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1, \ 4857 + regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4) 5293 4858 5294 4859 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) 5295 4860 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ ··· 5298 4861 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ 5299 4862 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 5300 4863 5301 - /* LRN:COMMON:COMMON_ACCESS_CTRL */ 5302 - #define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN,\ 5303 - 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 4864 + /* LRN:COMMON:COMMON_ACCESS_CTRL */ 4865 + #define LRN_COMMON_ACCESS_CTRL \ 4866 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 5304 4867 5305 4868 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) 5306 4869 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ ··· 5314 4877 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ 5315 4878 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 5316 4879 5317 - #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5) 4880 + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW\ 4881 + GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5) 5318 4882 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ 5319 - FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 4883 + spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 5320 4884 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ 5321 - FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 4885 + spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 5322 4886 5323 4887 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) 5324 4888 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ ··· 5333 4895 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ 5334 4896 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 5335 4897 5336 - /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 5337 - #define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN,\ 5338 - 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 4898 + /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 4899 + #define LRN_MAC_ACCESS_CFG_0 \ 4900 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 5339 4901 5340 4902 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) 5341 4903 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ ··· 5349 4911 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ 5350 4912 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 5351 4913 5352 - /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 5353 - #define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN,\ 5354 - 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 4914 + /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 4915 + #define LRN_MAC_ACCESS_CFG_1 \ 4916 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 5355 4917 5356 - /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 5357 - #define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN,\ 5358 - 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 4918 + /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 4919 + #define LRN_MAC_ACCESS_CFG_2 \ 4920 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 5359 4921 5360 4922 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) 5361 4923 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ ··· 5429 4991 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ 5430 4992 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 5431 4993 5432 - /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 5433 - #define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN,\ 5434 - 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 4994 + /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 4995 + #define LRN_MAC_ACCESS_CFG_3 \ 4996 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 5435 4997 5436 - #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0) 4998 + #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX\ 4999 + GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0) 5437 5000 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ 5438 - FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5001 + spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5439 5002 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ 5440 - FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5003 + spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5441 5004 5442 - /* LRN:COMMON:SCAN_NEXT_CFG */ 5443 - #define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN,\ 5444 - 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 5005 + /* LRN:COMMON:SCAN_NEXT_CFG */ 5006 + #define LRN_SCAN_NEXT_CFG \ 5007 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 5445 5008 5446 5009 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) 5447 5010 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ ··· 5534 5095 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ 5535 5096 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5536 5097 5537 - /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 5538 - #define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN,\ 5539 - 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 5098 + /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 5099 + #define LRN_SCAN_NEXT_CFG_1 \ 5100 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 5540 5101 5541 5102 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) 5542 5103 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ ··· 5550 5111 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ 5551 5112 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5552 5113 5553 - /* LRN:COMMON:AUTOAGE_CFG */ 5554 - #define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN,\ 5555 - 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 5114 + /* LRN:COMMON:AUTOAGE_CFG */ 5115 + #define LRN_AUTOAGE_CFG(r) \ 5116 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 5556 5117 5557 5118 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) 5558 5119 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ ··· 5566 5127 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ 5567 5128 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5568 5129 5569 - /* LRN:COMMON:AUTOAGE_CFG_1 */ 5570 - #define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN,\ 5571 - 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 5130 + /* LRN:COMMON:AUTOAGE_CFG_1 */ 5131 + #define LRN_AUTOAGE_CFG_1 \ 5132 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 5572 5133 5573 5134 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) 5574 5135 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ ··· 5612 5173 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ 5613 5174 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5614 5175 5615 - /* LRN:COMMON:AUTOAGE_CFG_2 */ 5616 - #define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN,\ 5617 - 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 5176 + /* LRN:COMMON:AUTOAGE_CFG_2 */ 5177 + #define LRN_AUTOAGE_CFG_2 \ 5178 + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 5618 5179 5619 - #define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4) 5180 + #define LRN_AUTOAGE_CFG_2_NEXT_ROW\ 5181 + GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4) 5620 5182 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ 5621 - FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5183 + spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5622 5184 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ 5623 - FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5185 + spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5624 5186 5625 5187 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) 5626 5188 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ ··· 5629 5189 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ 5630 5190 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5631 5191 5632 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 5633 - #define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP,\ 5634 - 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 5192 + /* SPARX5 ONLY */ 5193 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 5194 + #define PCEP_RCTRL_2_OUT_0 \ 5195 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 5635 5196 5636 5197 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) 5637 5198 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ ··· 5694 5253 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ 5695 5254 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5696 5255 5697 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 5698 - #define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP,\ 5699 - 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 5256 + /* SPARX5 ONLY */ 5257 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 5258 + #define PCEP_ADDR_LWR_OUT_0 \ 5259 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 5700 5260 5701 5261 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) 5702 5262 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ ··· 5711 5269 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ 5712 5270 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5713 5271 5714 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 5715 - #define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP,\ 5716 - 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 5272 + /* SPARX5 ONLY */ 5273 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 5274 + #define PCEP_ADDR_UPR_OUT_0 \ 5275 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 5717 5276 5718 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5719 - #define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP,\ 5720 - 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 5277 + /* SPARX5 ONLY */ 5278 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5279 + #define PCEP_ADDR_LIM_OUT_0 \ 5280 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 5721 5281 5722 5282 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) 5723 5283 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ ··· 5733 5289 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ 5734 5290 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5735 5291 5736 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 5737 - #define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP,\ 5738 - 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 5292 + /* SPARX5 ONLY */ 5293 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 5294 + #define PCEP_ADDR_LWR_TGT_OUT_0 \ 5295 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 5739 5296 5740 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 5741 - #define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP,\ 5742 - 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 5297 + /* SPARX5 ONLY */ 5298 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 5299 + #define PCEP_ADDR_UPR_TGT_OUT_0 \ 5300 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 5743 5301 5744 - /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5745 - #define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP,\ 5746 - 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 5302 + /* SPARX5 ONLY */ 5303 + /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5304 + #define PCEP_ADDR_UPR_LIM_OUT_0 \ 5305 + __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 5747 5306 5748 5307 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) 5749 5308 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ ··· 5760 5313 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ 5761 5314 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5762 5315 5763 - /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5764 - #define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR,\ 5765 - t, 12, 0, 0, 1, 56, 0, 0, 1, 4) 5316 + /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5317 + #define PCS10G_BR_PCS_CFG(t) \ 5318 + __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0, \ 5319 + 0, 1, 4) 5766 5320 5767 5321 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) 5768 5322 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ ··· 5837 5389 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5838 5390 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5839 5391 5840 - /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5841 - #define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR,\ 5842 - t, 12, 0, 0, 1, 56, 4, 0, 1, 4) 5392 + /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5393 + #define PCS10G_BR_PCS_SD_CFG(t) \ 5394 + __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4, \ 5395 + 0, 1, 4) 5843 5396 5844 5397 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5845 5398 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ ··· 5860 5411 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5861 5412 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5862 5413 5863 - /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5864 - #define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR,\ 5865 - t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 5414 + /* SPARX5 ONLY */ 5415 + /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5416 + #define PCS25G_BR_PCS_CFG(t) \ 5417 + __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 5866 5418 5867 5419 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) 5868 5420 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ ··· 5937 5487 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5938 5488 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5939 5489 5940 - /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5941 - #define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR,\ 5942 - t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 5490 + /* SPARX5 ONLY */ 5491 + /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5492 + #define PCS25G_BR_PCS_SD_CFG(t) \ 5493 + __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 5943 5494 5944 5495 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5945 5496 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ ··· 5960 5509 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5961 5510 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5962 5511 5963 - /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5964 - #define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR,\ 5965 - t, 13, 0, 0, 1, 56, 0, 0, 1, 4) 5512 + /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5513 + #define PCS5G_BR_PCS_CFG(t) \ 5514 + __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \ 5515 + 1, 4) 5966 5516 5967 5517 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) 5968 5518 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ ··· 6037 5585 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 6038 5586 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6039 5587 6040 - /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 6041 - #define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR,\ 6042 - t, 13, 0, 0, 1, 56, 4, 0, 1, 4) 5588 + /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5589 + #define PCS5G_BR_PCS_SD_CFG(t) \ 5590 + __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \ 5591 + 1, 4) 6043 5592 6044 5593 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) 6045 5594 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ ··· 6060 5607 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 6061 5608 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 6062 5609 6063 - /* PORT_CONF:HW_CFG:DEV5G_MODES */ 6064 - #define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF,\ 6065 - 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 5610 + /* PORT_CONF:HW_CFG:DEV5G_MODES */ 5611 + #define PORT_CONF_DEV5G_MODES \ 5612 + __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 6066 5613 5614 + /* SPARX5 ONLY */ 6067 5615 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) 6068 5616 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ 6069 5617 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 6070 5618 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ 6071 5619 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 6072 5620 5621 + /* SPARX5 ONLY */ 6073 5622 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) 6074 5623 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ 6075 5624 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 6076 5625 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ 6077 5626 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 6078 5627 5628 + /* SPARX5 ONLY */ 6079 5629 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) 6080 5630 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ 6081 5631 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 6082 5632 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ 6083 5633 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 6084 5634 5635 + /* SPARX5 ONLY */ 6085 5636 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) 6086 5637 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ 6087 5638 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 6088 5639 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ 6089 5640 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 6090 5641 5642 + /* SPARX5 ONLY */ 6091 5643 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) 6092 5644 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ 6093 5645 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 6094 5646 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ 6095 5647 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 6096 5648 5649 + /* SPARX5 ONLY */ 6097 5650 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) 6098 5651 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ 6099 5652 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 6100 5653 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ 6101 5654 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 6102 5655 5656 + /* SPARX5 ONLY */ 6103 5657 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) 6104 5658 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ 6105 5659 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 6106 5660 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ 6107 5661 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 6108 5662 5663 + /* SPARX5 ONLY */ 6109 5664 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) 6110 5665 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ 6111 5666 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 6112 5667 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ 6113 5668 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 6114 5669 5670 + /* SPARX5 ONLY */ 6115 5671 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) 6116 5672 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ 6117 5673 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) ··· 6133 5671 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ 6134 5672 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 6135 5673 5674 + /* SPARX5 ONLY */ 6136 5675 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) 6137 5676 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ 6138 5677 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 6139 5678 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ 6140 5679 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 6141 5680 5681 + /* SPARX5 ONLY */ 6142 5682 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) 6143 5683 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ 6144 5684 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 6145 5685 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ 6146 5686 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 6147 5687 5688 + /* SPARX5 ONLY */ 6148 5689 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) 6149 5690 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ 6150 5691 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 6151 5692 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ 6152 5693 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 6153 5694 6154 - /* PORT_CONF:HW_CFG:DEV10G_MODES */ 6155 - #define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF,\ 6156 - 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 5695 + /* PORT_CONF:HW_CFG:DEV10G_MODES */ 5696 + #define PORT_CONF_DEV10G_MODES \ 5697 + __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 6157 5698 6158 5699 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) 6159 5700 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ ··· 6164 5699 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ 6165 5700 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 6166 5701 5702 + /* SPARX5 ONLY */ 6167 5703 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) 6168 5704 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ 6169 5705 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 6170 5706 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ 6171 5707 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 6172 5708 5709 + /* SPARX5 ONLY */ 6173 5710 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) 6174 5711 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ 6175 5712 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 6176 5713 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ 6177 5714 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 6178 5715 5716 + /* SPARX5 ONLY */ 6179 5717 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) 6180 5718 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ 6181 5719 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 6182 5720 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ 6183 5721 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 6184 5722 5723 + /* SPARX5 ONLY */ 6185 5724 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) 6186 5725 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ 6187 5726 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 6188 5727 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ 6189 5728 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 6190 5729 5730 + /* SPARX5 ONLY */ 6191 5731 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) 6192 5732 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ 6193 5733 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 6194 5734 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ 6195 5735 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 6196 5736 5737 + /* SPARX5 ONLY */ 6197 5738 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) 6198 5739 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ 6199 5740 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 6200 5741 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ 6201 5742 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 6202 5743 5744 + /* SPARX5 ONLY */ 6203 5745 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) 6204 5746 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ 6205 5747 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 6206 5748 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ 6207 5749 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 6208 5750 5751 + /* SPARX5 ONLY */ 6209 5752 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) 6210 5753 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ 6211 5754 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 6212 5755 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ 6213 5756 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 6214 5757 5758 + /* SPARX5 ONLY */ 6215 5759 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) 6216 5760 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ 6217 5761 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 6218 5762 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ 6219 5763 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 6220 5764 5765 + /* SPARX5 ONLY */ 6221 5766 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) 6222 5767 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ 6223 5768 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 6224 5769 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ 6225 5770 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 6226 5771 5772 + /* SPARX5 ONLY */ 6227 5773 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) 6228 5774 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ 6229 5775 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 6230 5776 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ 6231 5777 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 6232 5778 6233 - /* PORT_CONF:HW_CFG:DEV25G_MODES */ 6234 - #define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF,\ 6235 - 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 5779 + /* SPARX5 ONLY */ 5780 + /* PORT_CONF:HW_CFG:DEV25G_MODES */ 5781 + #define PORT_CONF_DEV25G_MODES \ 5782 + __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 6236 5783 6237 5784 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) 6238 5785 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ ··· 6294 5817 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ 6295 5818 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 6296 5819 6297 - /* PORT_CONF:HW_CFG:QSGMII_ENA */ 6298 - #define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF,\ 6299 - 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 5820 + /* PORT_CONF:HW_CFG:QSGMII_ENA */ 5821 + #define PORT_CONF_QSGMII_ENA \ 5822 + __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 6300 5823 6301 5824 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) 6302 5825 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ ··· 6334 5857 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ 6335 5858 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 6336 5859 5860 + /* SPARX5 ONLY */ 6337 5861 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) 6338 5862 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ 6339 5863 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 6340 5864 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ 6341 5865 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 6342 5866 5867 + /* SPARX5 ONLY */ 6343 5868 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) 6344 5869 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ 6345 5870 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 6346 5871 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ 6347 5872 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 6348 5873 5874 + /* SPARX5 ONLY */ 6349 5875 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) 6350 5876 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ 6351 5877 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 6352 5878 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ 6353 5879 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 6354 5880 5881 + /* SPARX5 ONLY */ 6355 5882 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) 6356 5883 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ 6357 5884 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 6358 5885 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ 6359 5886 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 6360 5887 5888 + /* SPARX5 ONLY */ 6361 5889 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) 6362 5890 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ 6363 5891 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 6364 5892 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ 6365 5893 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 6366 5894 5895 + /* SPARX5 ONLY */ 6367 5896 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) 6368 5897 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ 6369 5898 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 6370 5899 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ 6371 5900 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 6372 5901 6373 - /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 6374 - #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\ 6375 - 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 5902 + /* SPARX5 ONLY */ 5903 + /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 5904 + #define PORT_CONF_USGMII_CFG(g) \ 5905 + __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 6376 5906 6377 5907 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) 6378 5908 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ ··· 6423 5939 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ 6424 5940 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 6425 5941 6426 - /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 6427 - #define PTP_PTP_PIN_INTR __REG(TARGET_PTP,\ 6428 - 0, 1, 320, 0, 1, 16, 0, 0, 1, 4) 5942 + /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 5943 + #define PTP_PTP_PIN_INTR \ 5944 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\ 5945 + 4) 6429 5946 6430 - #define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0) 5947 + #define PTP_PTP_PIN_INTR_INTR_PTP\ 5948 + GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0) 6431 5949 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ 6432 - FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x) 5950 + spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x) 6433 5951 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ 6434 - FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x) 5952 + spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x) 6435 5953 6436 - /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 6437 - #define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP,\ 6438 - 0, 1, 320, 0, 1, 16, 4, 0, 1, 4) 5954 + /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 5955 + #define PTP_PTP_PIN_INTR_ENA \ 5956 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\ 5957 + 4) 6439 5958 6440 - #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0) 5959 + #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA\ 5960 + GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0) 6441 5961 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ 6442 - FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 5962 + spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 6443 5963 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ 6444 - FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 5964 + spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 6445 5965 6446 - /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 6447 - #define PTP_PTP_INTR_IDENT __REG(TARGET_PTP,\ 6448 - 0, 1, 320, 0, 1, 16, 8, 0, 1, 4) 5966 + /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 5967 + #define PTP_PTP_INTR_IDENT \ 5968 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\ 5969 + 4) 6449 5970 6450 - #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0) 5971 + #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT\ 5972 + GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0) 6451 5973 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ 6452 - FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 5974 + spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 6453 5975 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ 6454 - FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 5976 + spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 6455 5977 6456 - /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 6457 - #define PTP_PTP_DOM_CFG __REG(TARGET_PTP,\ 6458 - 0, 1, 320, 0, 1, 16, 12, 0, 1, 4) 5978 + /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 5979 + #define PTP_PTP_DOM_CFG \ 5980 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0, \ 5981 + 1, 4) 6459 5982 6460 5983 #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) 6461 5984 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ ··· 6488 5997 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ 6489 5998 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 6490 5999 6491 - /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 6492 - #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\ 6493 - 0, 1, 336, g, 3, 28, 0, r, 2, 4) 6000 + /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 6001 + #define PTP_CLK_PER_CFG(g, r) \ 6002 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6003 + 0, r, 2, 4) 6494 6004 6495 - /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 6496 - #define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\ 6497 - 0, 1, 336, g, 3, 28, 8, 0, 1, 4) 6005 + /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 6006 + #define PTP_PTP_CUR_NSEC(g) \ 6007 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6008 + 8, 0, 1, 4) 6498 6009 6499 6010 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) 6500 6011 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ ··· 6504 6011 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ 6505 6012 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6506 6013 6507 - /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 6508 - #define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\ 6509 - 0, 1, 336, g, 3, 28, 12, 0, 1, 4) 6014 + /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 6015 + #define PTP_PTP_CUR_NSEC_FRAC(g) \ 6016 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6017 + 12, 0, 1, 4) 6510 6018 6511 6019 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) 6512 6020 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ ··· 6515 6021 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ 6516 6022 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6517 6023 6518 - /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 6519 - #define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\ 6520 - 0, 1, 336, g, 3, 28, 16, 0, 1, 4) 6024 + /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 6025 + #define PTP_PTP_CUR_SEC_LSB(g) \ 6026 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6027 + 16, 0, 1, 4) 6521 6028 6522 - /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 6523 - #define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\ 6524 - 0, 1, 336, g, 3, 28, 20, 0, 1, 4) 6029 + /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 6030 + #define PTP_PTP_CUR_SEC_MSB(g) \ 6031 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6032 + 20, 0, 1, 4) 6525 6033 6526 6034 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) 6527 6035 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ ··· 6531 6035 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ 6532 6036 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6533 6037 6534 - /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 6535 - #define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\ 6536 - 0, 1, 336, g, 3, 28, 24, 0, 1, 4) 6038 + /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 6039 + #define PTP_NTP_CUR_NSEC(g) \ 6040 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6041 + 24, 0, 1, 4) 6537 6042 6538 - /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 6539 - #define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\ 6540 - 0, 1, 0, g, 5, 64, 0, 0, 1, 4) 6043 + /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 6044 + #define PTP_PTP_PIN_CFG(g) \ 6045 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\ 6046 + 4) 6541 6047 6542 - #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26) 6048 + #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION\ 6049 + GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION]) 6543 6050 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ 6544 - FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6051 + spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6545 6052 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ 6546 - FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6053 + spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6547 6054 6548 - #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24) 6055 + #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC\ 6056 + GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC]) 6549 6057 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ 6550 - FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6058 + spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6551 6059 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ 6552 - FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6060 + spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6553 6061 6554 - #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23) 6062 + #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL\ 6063 + BIT(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL]) 6555 6064 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ 6556 - FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6065 + spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6557 6066 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ 6558 - FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6067 + spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6559 6068 6560 - #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21) 6069 + #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT\ 6070 + GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21) 6561 6071 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ 6562 - FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6072 + spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6563 6073 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ 6564 - FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6074 + spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6565 6075 6566 6076 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) 6567 6077 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ ··· 6599 6097 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ 6600 6098 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6601 6099 6602 - /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 6603 - #define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\ 6604 - 0, 1, 0, g, 5, 64, 4, 0, 1, 4) 6100 + /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 6101 + #define PTP_PTP_TOD_SEC_MSB(g) \ 6102 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\ 6103 + 4) 6605 6104 6606 6105 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) 6607 6106 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ ··· 6610 6107 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ 6611 6108 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6612 6109 6613 - /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 6614 - #define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\ 6615 - 0, 1, 0, g, 5, 64, 8, 0, 1, 4) 6110 + /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 6111 + #define PTP_PTP_TOD_SEC_LSB(g) \ 6112 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\ 6113 + 4) 6616 6114 6617 - /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 6618 - #define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\ 6619 - 0, 1, 0, g, 5, 64, 12, 0, 1, 4) 6115 + /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 6116 + #define PTP_PTP_TOD_NSEC(g) \ 6117 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0, \ 6118 + 1, 4) 6620 6119 6621 6120 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) 6622 6121 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ ··· 6626 6121 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ 6627 6122 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6628 6123 6629 - /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 6630 - #define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\ 6631 - 0, 1, 0, g, 5, 64, 16, 0, 1, 4) 6124 + /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 6125 + #define PTP_PTP_TOD_NSEC_FRAC(g) \ 6126 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0, \ 6127 + 1, 4) 6632 6128 6633 6129 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) 6634 6130 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ ··· 6637 6131 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ 6638 6132 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6639 6133 6640 - /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 6641 - #define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\ 6642 - 0, 1, 0, g, 5, 64, 20, 0, 1, 4) 6134 + /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 6135 + #define PTP_NTP_NSEC(g) \ 6136 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0, \ 6137 + 1, 4) 6643 6138 6644 - /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 6645 - #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 6646 - 0, 1, 0, g, 5, 64, 24, 0, 1, 4) 6139 + /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 6140 + #define PTP_PIN_WF_HIGH_PERIOD(g) \ 6141 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0, \ 6142 + 1, 4) 6647 6143 6648 6144 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) 6649 6145 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ ··· 6653 6145 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ 6654 6146 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6655 6147 6656 - /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 6657 - #define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 6658 - 0, 1, 0, g, 5, 64, 28, 0, 1, 4) 6148 + /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 6149 + #define PTP_PIN_WF_LOW_PERIOD(g) \ 6150 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0, \ 6151 + 1, 4) 6659 6152 6660 6153 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) 6661 6154 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ ··· 6664 6155 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ 6665 6156 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6666 6157 6667 - /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 6668 - #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\ 6669 - 0, 1, 0, g, 5, 64, 32, 0, 1, 4) 6158 + /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 6159 + #define PTP_PIN_IOBOUNCH_DELAY(g) \ 6160 + __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0, \ 6161 + 1, 4) 6670 6162 6671 6163 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) 6672 6164 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ ··· 6681 6171 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ 6682 6172 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6683 6173 6684 - /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 6685 - #define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\ 6686 - 0, 1, 420, g, 5, 8, 0, 0, 1, 4) 6174 + /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 6175 + #define PTP_PHAD_CTRL(g) \ 6176 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ 6177 + regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ 6178 + regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) 6687 6179 6688 - #define PTP_PHAD_CTRL_PHAD_ENA BIT(7) 6180 + #define PTP_PHAD_CTRL_PHAD_ENA\ 6181 + BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_ENA]) 6689 6182 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ 6690 - FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x) 6183 + spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x) 6691 6184 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ 6692 - FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x) 6185 + spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x) 6693 6186 6694 - #define PTP_PHAD_CTRL_PHAD_FAILED BIT(6) 6187 + #define PTP_PHAD_CTRL_PHAD_FAILED\ 6188 + BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_FAILED]) 6695 6189 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ 6696 - FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x) 6190 + spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x) 6697 6191 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ 6698 - FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x) 6192 + spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x) 6699 6193 6194 + /* SPARX5 ONLY */ 6700 6195 #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) 6701 6196 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ 6702 6197 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) ··· 6714 6199 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ 6715 6200 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) 6716 6201 6717 - /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 6718 - #define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\ 6719 - 0, 1, 420, g, 5, 8, 4, 0, 1, 4) 6202 + /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 6203 + #define PTP_PHAD_CYC_STAT(g) \ 6204 + __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ 6205 + regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ 6206 + regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) 6720 6207 6721 - /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 6722 - #define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD,\ 6723 - 0, 1, 0, 0, 1, 340, 0, r, 70, 4) 6208 + /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 6209 + #define QFWD_SWITCH_PORT_MODE(r) \ 6210 + __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ 6211 + regs->rcnt[RC_QFWD_SWITCH_PORT_MODE], 4) 6724 6212 6725 6213 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) 6726 6214 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ ··· 6779 6261 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ 6780 6262 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6781 6263 6782 - /* QFWD:SYSTEM:FRAME_COPY_CFG */ 6783 - #define QFWD_FRAME_COPY_CFG(r)\ 6264 + /* QFWD:SYSTEM:FRAME_COPY_CFG */ 6265 + #define QFWD_FRAME_COPY_CFG(r) \ 6784 6266 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4) 6785 6267 6786 - #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL GENMASK(12, 6) 6268 + #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL\ 6269 + GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6) 6787 6270 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ 6788 - FIELD_PREP(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6271 + spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6789 6272 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ 6790 - FIELD_GET(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6273 + spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6791 6274 6792 - /* QRES:RES_CTRL:RES_CFG */ 6793 - #define QRES_RES_CFG(g) __REG(TARGET_QRES,\ 6794 - 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 6275 + /* QRES:RES_CTRL:RES_CFG */ 6276 + #define QRES_RES_CFG(g) \ 6277 + __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 6795 6278 6796 - #define QRES_RES_CFG_WM_HIGH GENMASK(11, 0) 6279 + #define QRES_RES_CFG_WM_HIGH\ 6280 + GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0) 6797 6281 #define QRES_RES_CFG_WM_HIGH_SET(x)\ 6798 - FIELD_PREP(QRES_RES_CFG_WM_HIGH, x) 6282 + spx5_field_prep(QRES_RES_CFG_WM_HIGH, x) 6799 6283 #define QRES_RES_CFG_WM_HIGH_GET(x)\ 6800 - FIELD_GET(QRES_RES_CFG_WM_HIGH, x) 6284 + spx5_field_get(QRES_RES_CFG_WM_HIGH, x) 6801 6285 6802 - /* QRES:RES_CTRL:RES_STAT */ 6803 - #define QRES_RES_STAT(g) __REG(TARGET_QRES,\ 6804 - 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 6286 + /* QRES:RES_CTRL:RES_STAT */ 6287 + #define QRES_RES_STAT(g) \ 6288 + __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 6805 6289 6806 - #define QRES_RES_STAT_MAXUSE GENMASK(20, 0) 6290 + #define QRES_RES_STAT_MAXUSE\ 6291 + GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0) 6807 6292 #define QRES_RES_STAT_MAXUSE_SET(x)\ 6808 - FIELD_PREP(QRES_RES_STAT_MAXUSE, x) 6293 + spx5_field_prep(QRES_RES_STAT_MAXUSE, x) 6809 6294 #define QRES_RES_STAT_MAXUSE_GET(x)\ 6810 - FIELD_GET(QRES_RES_STAT_MAXUSE, x) 6295 + spx5_field_get(QRES_RES_STAT_MAXUSE, x) 6811 6296 6812 - /* QRES:RES_CTRL:RES_STAT_CUR */ 6813 - #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\ 6814 - 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 6297 + /* QRES:RES_CTRL:RES_STAT_CUR */ 6298 + #define QRES_RES_STAT_CUR(g) \ 6299 + __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 6815 6300 6816 - #define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0) 6301 + #define QRES_RES_STAT_CUR_INUSE\ 6302 + GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0) 6817 6303 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ 6818 - FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x) 6304 + spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x) 6819 6305 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ 6820 - FIELD_GET(QRES_RES_STAT_CUR_INUSE, x) 6306 + spx5_field_get(QRES_RES_STAT_CUR_INUSE, x) 6821 6307 6822 - /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 6823 - #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS,\ 6824 - 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 6308 + /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 6309 + #define QS_XTR_GRP_CFG(r) \ 6310 + __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 6825 6311 6826 6312 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 6827 6313 #define QS_XTR_GRP_CFG_MODE_SET(x)\ ··· 6845 6323 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 6846 6324 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 6847 6325 6848 - /* DEVCPU_QS:XTR:XTR_RD */ 6849 - #define QS_XTR_RD(r) __REG(TARGET_QS,\ 6850 - 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 6326 + /* DEVCPU_QS:XTR:XTR_RD */ 6327 + #define QS_XTR_RD(r) \ 6328 + __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 6851 6329 6852 - /* DEVCPU_QS:XTR:XTR_FLUSH */ 6853 - #define QS_XTR_FLUSH __REG(TARGET_QS,\ 6854 - 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 6330 + /* DEVCPU_QS:XTR:XTR_FLUSH */ 6331 + #define QS_XTR_FLUSH \ 6332 + __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 6855 6333 6856 6334 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) 6857 6335 #define QS_XTR_FLUSH_FLUSH_SET(x)\ ··· 6859 6337 #define QS_XTR_FLUSH_FLUSH_GET(x)\ 6860 6338 FIELD_GET(QS_XTR_FLUSH_FLUSH, x) 6861 6339 6862 - /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 6863 - #define QS_XTR_DATA_PRESENT __REG(TARGET_QS,\ 6864 - 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 6340 + /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 6341 + #define QS_XTR_DATA_PRESENT \ 6342 + __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 6865 6343 6866 6344 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) 6867 6345 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ ··· 6869 6347 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ 6870 6348 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 6871 6349 6872 - /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 6873 - #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS,\ 6874 - 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 6350 + /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 6351 + #define QS_INJ_GRP_CFG(r) \ 6352 + __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 6875 6353 6876 6354 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 6877 6355 #define QS_INJ_GRP_CFG_MODE_SET(x)\ ··· 6885 6363 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 6886 6364 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 6887 6365 6888 - /* DEVCPU_QS:INJ:INJ_WR */ 6889 - #define QS_INJ_WR(r) __REG(TARGET_QS,\ 6890 - 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 6366 + /* DEVCPU_QS:INJ:INJ_WR */ 6367 + #define QS_INJ_WR(r) \ 6368 + __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 6891 6369 6892 - /* DEVCPU_QS:INJ:INJ_CTRL */ 6893 - #define QS_INJ_CTRL(r) __REG(TARGET_QS,\ 6894 - 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 6370 + /* DEVCPU_QS:INJ:INJ_CTRL */ 6371 + #define QS_INJ_CTRL(r) \ 6372 + __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 6895 6373 6896 6374 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 6897 6375 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ ··· 6923 6401 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 6924 6402 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 6925 6403 6926 - /* DEVCPU_QS:INJ:INJ_STATUS */ 6927 - #define QS_INJ_STATUS __REG(TARGET_QS,\ 6928 - 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 6404 + /* DEVCPU_QS:INJ:INJ_STATUS */ 6405 + #define QS_INJ_STATUS \ 6406 + __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 6929 6407 6930 6408 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 6931 6409 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ ··· 6945 6423 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ 6946 6424 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 6947 6425 6948 - /* QSYS:PAUSE_CFG:PAUSE_CFG */ 6949 - #define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS,\ 6950 - 0, 1, 544, 0, 1, 1128, 0, r, 70, 4) 6426 + /* QSYS:PAUSE_CFG:PAUSE_CFG */ 6427 + #define QSYS_PAUSE_CFG(r) \ 6428 + __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \ 6429 + r, regs->rcnt[RC_QSYS_PAUSE_CFG], 4) 6951 6430 6952 - #define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14) 6431 + #define QSYS_PAUSE_CFG_PAUSE_START\ 6432 + GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14) 6953 6433 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ 6954 - FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x) 6434 + spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x) 6955 6435 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ 6956 - FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x) 6436 + spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x) 6957 6437 6958 - #define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2) 6438 + #define QSYS_PAUSE_CFG_PAUSE_STOP\ 6439 + GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2) 6959 6440 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 6960 - FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6441 + spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6961 6442 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 6962 - FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6443 + spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6963 6444 6964 6445 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) 6965 6446 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ ··· 6976 6451 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ 6977 6452 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 6978 6453 6979 - /* QSYS:PAUSE_CFG:ATOP */ 6980 - #define QSYS_ATOP(r) __REG(TARGET_QSYS,\ 6981 - 0, 1, 544, 0, 1, 1128, 284, r, 70, 4) 6454 + /* QSYS:PAUSE_CFG:ATOP */ 6455 + #define QSYS_ATOP(r) \ 6456 + __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 6457 + 284, r, regs->rcnt[RC_QSYS_ATOP], 4) 6982 6458 6983 - #define QSYS_ATOP_ATOP GENMASK(11, 0) 6459 + #define QSYS_ATOP_ATOP\ 6460 + GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0) 6984 6461 #define QSYS_ATOP_ATOP_SET(x)\ 6985 - FIELD_PREP(QSYS_ATOP_ATOP, x) 6462 + spx5_field_prep(QSYS_ATOP_ATOP, x) 6986 6463 #define QSYS_ATOP_ATOP_GET(x)\ 6987 - FIELD_GET(QSYS_ATOP_ATOP, x) 6464 + spx5_field_get(QSYS_ATOP_ATOP, x) 6988 6465 6989 - /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 6990 - #define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS,\ 6991 - 0, 1, 544, 0, 1, 1128, 564, r, 70, 4) 6466 + /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 6467 + #define QSYS_FWD_PRESSURE(r) \ 6468 + __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 6469 + 564, r, regs->rcnt[RC_QSYS_FWD_PRESSURE], 4) 6992 6470 6993 6471 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) 6994 6472 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ ··· 7005 6477 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ 7006 6478 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 7007 6479 7008 - /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 7009 - #define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS,\ 7010 - 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4) 6480 + /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 6481 + #define QSYS_ATOP_TOT_CFG \ 6482 + __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 6483 + 844, 0, 1, 4) 7011 6484 7012 - #define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0) 6485 + #define QSYS_ATOP_TOT_CFG_ATOP_TOT\ 6486 + GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0) 7013 6487 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ 7014 - FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 6488 + spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 7015 6489 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ 7016 - FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 6490 + spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 7017 6491 7018 - /* QSYS:CALCFG:CAL_AUTO */ 7019 - #define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS,\ 7020 - 0, 1, 2304, 0, 1, 40, 0, r, 7, 4) 6492 + /* QSYS:CALCFG:CAL_AUTO */ 6493 + #define QSYS_CAL_AUTO(r) \ 6494 + __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r, \ 6495 + regs->rcnt[RC_QSYS_CAL_AUTO], 4) 7021 6496 7022 6497 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) 7023 6498 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ ··· 7028 6497 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ 7029 6498 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) 7030 6499 7031 - /* QSYS:CALCFG:CAL_CTRL */ 7032 - #define QSYS_CAL_CTRL __REG(TARGET_QSYS,\ 7033 - 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4) 6500 + /* QSYS:CALCFG:CAL_CTRL */ 6501 + #define QSYS_CAL_CTRL \ 6502 + __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \ 6503 + 1, 4) 7034 6504 7035 6505 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) 7036 6506 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ ··· 7051 6519 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ 7052 6520 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 7053 6521 7054 - /* QSYS:RAM_CTRL:RAM_INIT */ 7055 - #define QSYS_RAM_INIT __REG(TARGET_QSYS,\ 7056 - 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4) 6522 + /* QSYS:RAM_CTRL:RAM_INIT */ 6523 + #define QSYS_RAM_INIT \ 6524 + __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \ 6525 + 1, 4) 7057 6526 7058 6527 #define QSYS_RAM_INIT_RAM_INIT BIT(1) 7059 6528 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ ··· 7068 6535 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7069 6536 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 7070 6537 7071 - /* REW:COMMON:OWN_UPSID */ 7072 - #define REW_OWN_UPSID(r) __REG(TARGET_REW,\ 7073 - 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4) 6538 + /* REW:COMMON:OWN_UPSID */ 6539 + #define REW_OWN_UPSID(r) \ 6540 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r, \ 6541 + regs->rcnt[RC_REW_OWN_UPSID], 4) 7074 6542 7075 6543 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 7076 6544 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ ··· 7079 6545 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ 7080 6546 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) 7081 6547 7082 - /* REW:COMMON:RTAG_ETAG_CTRL */ 7083 - #define REW_RTAG_ETAG_CTRL(r) __REG(TARGET_REW,\ 7084 - 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4) 6548 + /* REW:COMMON:RTAG_ETAG_CTRL */ 6549 + #define REW_RTAG_ETAG_CTRL(r) \ 6550 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\ 6551 + regs->rcnt[RC_REW_RTAG_ETAG_CTRL], 4) 7085 6552 7086 - #define REW_RTAG_ETAG_CTRL_IPE_TBL GENMASK(9, 3) 6553 + #define REW_RTAG_ETAG_CTRL_IPE_TBL\ 6554 + GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3) 7087 6555 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ 7088 - FIELD_PREP(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 6556 + spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 7089 6557 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ 7090 - FIELD_GET(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 6558 + spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 7091 6559 7092 6560 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1) 7093 6561 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ ··· 7103 6567 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ 7104 6568 FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 7105 6569 7106 - /* REW:COMMON:ES0_CTRL */ 7107 - #define REW_ES0_CTRL __REG(TARGET_REW,\ 7108 - 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4) 6570 + /* REW:COMMON:ES0_CTRL */ 6571 + #define REW_ES0_CTRL \ 6572 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\ 6573 + 1, 4) 7109 6574 7110 6575 #define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5) 7111 6576 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ ··· 7144 6607 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ 7145 6608 FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x) 7146 6609 7147 - /* REW:PORT:PORT_VLAN_CFG */ 7148 - #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\ 7149 - 0, 1, 360448, g, 70, 256, 0, 0, 1, 4) 6610 + /* REW:PORT:PORT_VLAN_CFG */ 6611 + #define REW_PORT_VLAN_CFG(g) \ 6612 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6613 + regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4) 7150 6614 7151 6615 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) 7152 6616 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ ··· 7167 6629 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 7168 6630 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 7169 6631 7170 - /* REW:PORT:PCP_MAP_DE0 */ 7171 - #define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\ 7172 - 0, 1, 360448, g, 70, 256, 4, r, 8, 4) 6632 + /* REW:PORT:PCP_MAP_DE0 */ 6633 + #define REW_PCP_MAP_DE0(g, r) \ 6634 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6635 + regs->gcnt[GC_REW_PORT], 256, 4, r, 8, 4) 7173 6636 7174 6637 #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) 7175 6638 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ ··· 7178 6639 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ 7179 6640 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) 7180 6641 7181 - /* REW:PORT:PCP_MAP_DE1 */ 7182 - #define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\ 7183 - 0, 1, 360448, g, 70, 256, 36, r, 8, 4) 6642 + /* REW:PORT:PCP_MAP_DE1 */ 6643 + #define REW_PCP_MAP_DE1(g, r) \ 6644 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6645 + regs->gcnt[GC_REW_PORT], 256, 36, r, 8, 4) 7184 6646 7185 6647 #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) 7186 6648 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ ··· 7189 6649 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ 7190 6650 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) 7191 6651 7192 - /* REW:PORT:DEI_MAP_DE0 */ 7193 - #define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\ 7194 - 0, 1, 360448, g, 70, 256, 68, r, 8, 4) 6652 + /* REW:PORT:DEI_MAP_DE0 */ 6653 + #define REW_DEI_MAP_DE0(g, r) \ 6654 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6655 + regs->gcnt[GC_REW_PORT], 256, 68, r, 8, 4) 7195 6656 7196 6657 #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) 7197 6658 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ ··· 7200 6659 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ 7201 6660 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) 7202 6661 7203 - /* REW:PORT:DEI_MAP_DE1 */ 7204 - #define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\ 7205 - 0, 1, 360448, g, 70, 256, 100, r, 8, 4) 6662 + /* REW:PORT:DEI_MAP_DE1 */ 6663 + #define REW_DEI_MAP_DE1(g, r) \ 6664 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6665 + regs->gcnt[GC_REW_PORT], 256, 100, r, 8, 4) 7206 6666 7207 6667 #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) 7208 6668 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ ··· 7211 6669 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ 7212 6670 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) 7213 6671 7214 - /* REW:PORT:TAG_CTRL */ 7215 - #define REW_TAG_CTRL(g) __REG(TARGET_REW,\ 7216 - 0, 1, 360448, g, 70, 256, 132, 0, 1, 4) 6672 + /* REW:PORT:TAG_CTRL */ 6673 + #define REW_TAG_CTRL(g) \ 6674 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6675 + regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4) 7217 6676 7218 6677 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) 7219 6678 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ ··· 7252 6709 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ 7253 6710 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) 7254 6711 7255 - /* REW:PORT:DSCP_MAP */ 7256 - #define REW_DSCP_MAP(g) __REG(TARGET_REW,\ 7257 - 0, 1, 360448, g, 70, 256, 136, 0, 1, 4) 6712 + /* REW:PORT:DSCP_MAP */ 6713 + #define REW_DSCP_MAP(g) \ 6714 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 6715 + regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4) 7258 6716 7259 6717 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) 7260 6718 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ ··· 7269 6725 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ 7270 6726 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 7271 6727 7272 - /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 7273 - #define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW,\ 7274 - 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 6728 + /* SPARX5 ONLY */ 6729 + /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 6730 + #define REW_PTP_TWOSTEP_CTRL \ 6731 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 7275 6732 7276 6733 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 7277 6734 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ ··· 7310 6765 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 7311 6766 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 7312 6767 7313 - /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 7314 - #define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW,\ 7315 - 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 6768 + /* SPARX5 ONLY */ 6769 + /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 6770 + #define REW_PTP_TWOSTEP_STAMP \ 6771 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 7316 6772 7317 6773 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) 7318 6774 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ ··· 7321 6775 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 7322 6776 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 7323 6777 7324 - /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 7325 - #define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW,\ 7326 - 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 6778 + /* SPARX5 ONLY */ 6779 + /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 6780 + #define REW_PTP_TWOSTEP_STAMP_SUBNS \ 6781 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 7327 6782 7328 6783 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) 7329 6784 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ ··· 7332 6785 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ 7333 6786 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 7334 6787 7335 - /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 7336 - #define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW,\ 7337 - 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 6788 + /* SPARX5 ONLY */ 6789 + /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 6790 + #define REW_PTP_RSRV_NOT_ZERO \ 6791 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 7338 6792 7339 - /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 7340 - #define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW,\ 7341 - 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 6793 + /* SPARX5 ONLY */ 6794 + /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 6795 + #define REW_PTP_RSRV_NOT_ZERO1 \ 6796 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 7342 6797 7343 - /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 7344 - #define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW,\ 7345 - 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 6798 + /* SPARX5 ONLY */ 6799 + /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 6800 + #define REW_PTP_RSRV_NOT_ZERO2 \ 6801 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 7346 6802 7347 6803 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) 7348 6804 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ ··· 7353 6803 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ 7354 6804 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 7355 6805 7356 - /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 7357 - #define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW,\ 7358 - 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 6806 + /* SPARX5 ONLY */ 6807 + /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 6808 + #define REW_PTP_GEN_STAMP_FMT(r) \ 6809 + __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 7359 6810 7360 6811 #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) 7361 6812 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ ··· 7370 6819 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ 7371 6820 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 7372 6821 7373 - /* REW:RAM_CTRL:RAM_INIT */ 7374 - #define REW_RAM_INIT __REG(TARGET_REW,\ 7375 - 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4) 6822 + /* REW:RAM_CTRL:RAM_INIT */ 6823 + #define REW_RAM_INIT \ 6824 + __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 6825 + 4) 7376 6826 7377 6827 #define REW_RAM_INIT_RAM_INIT BIT(1) 7378 6828 #define REW_RAM_INIT_RAM_INIT_SET(x)\ ··· 7387 6835 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7388 6836 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) 7389 6837 7390 - /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7391 - #define VCAP_ES0_CTRL __REG(TARGET_VCAP_ES0,\ 7392 - 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 6838 + /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 6839 + #define VCAP_ES0_CTRL \ 6840 + __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7393 6841 7394 6842 #define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22) 7395 6843 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ ··· 7439 6887 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7440 6888 FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 7441 6889 7442 - /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ 7443 - #define VCAP_ES0_CFG __REG(TARGET_VCAP_ES0,\ 7444 - 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 6890 + /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ 6891 + #define VCAP_ES0_CFG \ 6892 + __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7445 6893 7446 6894 #define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16) 7447 6895 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ ··· 7455 6903 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ 7456 6904 FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x) 7457 6905 7458 - /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7459 - #define VCAP_ES0_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES0,\ 7460 - 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 6906 + /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 6907 + #define VCAP_ES0_VCAP_ENTRY_DAT(r) \ 6908 + __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7461 6909 7462 - /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7463 - #define VCAP_ES0_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES0,\ 7464 - 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 6910 + /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 6911 + #define VCAP_ES0_VCAP_MASK_DAT(r) \ 6912 + __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7465 6913 7466 - /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7467 - #define VCAP_ES0_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES0,\ 7468 - 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 6914 + /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 6915 + #define VCAP_ES0_VCAP_ACTION_DAT(r) \ 6916 + __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7469 6917 7470 - /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7471 - #define VCAP_ES0_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES0,\ 7472 - 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 6918 + /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 6919 + #define VCAP_ES0_VCAP_CNT_DAT(r) \ 6920 + __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7473 6921 7474 - /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7475 - #define VCAP_ES0_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES0,\ 7476 - 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 6922 + /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 6923 + #define VCAP_ES0_VCAP_CNT_FW_DAT \ 6924 + __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7477 6925 7478 - /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7479 - #define VCAP_ES0_VCAP_TG_DAT __REG(TARGET_VCAP_ES0,\ 7480 - 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 6926 + /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ 6927 + #define VCAP_ES0_VCAP_TG_DAT \ 6928 + __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7481 6929 7482 - /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7483 - #define VCAP_ES0_IDX __REG(TARGET_VCAP_ES0,\ 7484 - 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 6930 + /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ 6931 + #define VCAP_ES0_IDX \ 6932 + __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7485 6933 7486 6934 #define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0) 7487 6935 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ ··· 7489 6937 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ 7490 6938 FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x) 7491 6939 7492 - /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7493 - #define VCAP_ES0_MAP __REG(TARGET_VCAP_ES0,\ 7494 - 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 6940 + /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ 6941 + #define VCAP_ES0_MAP \ 6942 + __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7495 6943 7496 6944 #define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0) 7497 6945 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ ··· 7499 6947 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ 7500 6948 FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x) 7501 6949 7502 - /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ 7503 - #define VCAP_ES0_VCAP_STICKY __REG(TARGET_VCAP_ES0,\ 7504 - 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 6950 + /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ 6951 + #define VCAP_ES0_VCAP_STICKY \ 6952 + __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7505 6953 7506 6954 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7507 6955 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ ··· 7509 6957 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7510 6958 FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7511 6959 7512 - /* VCAP_ES0:VCAP_CONST:VCAP_VER */ 7513 - #define VCAP_ES0_VCAP_VER __REG(TARGET_VCAP_ES0,\ 7514 - 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 6960 + /* VCAP_ES0:VCAP_CONST:VCAP_VER */ 6961 + #define VCAP_ES0_VCAP_VER \ 6962 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7515 6963 7516 - /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ 7517 - #define VCAP_ES0_ENTRY_WIDTH __REG(TARGET_VCAP_ES0,\ 7518 - 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 6964 + /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ 6965 + #define VCAP_ES0_ENTRY_WIDTH \ 6966 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7519 6967 7520 - /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ 7521 - #define VCAP_ES0_ENTRY_CNT __REG(TARGET_VCAP_ES0,\ 7522 - 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 6968 + /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ 6969 + #define VCAP_ES0_ENTRY_CNT \ 6970 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7523 6971 7524 - /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ 7525 - #define VCAP_ES0_ENTRY_SWCNT __REG(TARGET_VCAP_ES0,\ 7526 - 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 6972 + /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ 6973 + #define VCAP_ES0_ENTRY_SWCNT \ 6974 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7527 6975 7528 - /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ 7529 - #define VCAP_ES0_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES0,\ 7530 - 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 6976 + /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ 6977 + #define VCAP_ES0_ENTRY_TG_WIDTH \ 6978 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7531 6979 7532 - /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ 7533 - #define VCAP_ES0_ACTION_DEF_CNT __REG(TARGET_VCAP_ES0,\ 7534 - 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 6980 + /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ 6981 + #define VCAP_ES0_ACTION_DEF_CNT \ 6982 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7535 6983 7536 - /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ 7537 - #define VCAP_ES0_ACTION_WIDTH __REG(TARGET_VCAP_ES0,\ 7538 - 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 6984 + /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ 6985 + #define VCAP_ES0_ACTION_WIDTH \ 6986 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7539 6987 7540 - /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ 7541 - #define VCAP_ES0_CNT_WIDTH __REG(TARGET_VCAP_ES0,\ 7542 - 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 6988 + /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ 6989 + #define VCAP_ES0_CNT_WIDTH \ 6990 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7543 6991 7544 - /* VCAP_ES0:VCAP_CONST:CORE_CNT */ 7545 - #define VCAP_ES0_CORE_CNT __REG(TARGET_VCAP_ES0,\ 7546 - 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 6992 + /* VCAP_ES0:VCAP_CONST:CORE_CNT */ 6993 + #define VCAP_ES0_CORE_CNT \ 6994 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7547 6995 7548 - /* VCAP_ES0:VCAP_CONST:IF_CNT */ 7549 - #define VCAP_ES0_IF_CNT __REG(TARGET_VCAP_ES0,\ 7550 - 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 6996 + /* VCAP_ES0:VCAP_CONST:IF_CNT */ 6997 + #define VCAP_ES0_IF_CNT \ 6998 + __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7551 6999 7552 - /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7553 - #define VCAP_ES2_CTRL __REG(TARGET_VCAP_ES2,\ 7554 - 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7000 + /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7001 + #define VCAP_ES2_CTRL \ 7002 + __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7555 7003 7556 7004 #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) 7557 7005 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ ··· 7601 7049 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7602 7050 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7603 7051 7604 - /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ 7605 - #define VCAP_ES2_CFG __REG(TARGET_VCAP_ES2,\ 7606 - 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7052 + /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ 7053 + #define VCAP_ES2_CFG \ 7054 + __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7607 7055 7608 7056 #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) 7609 7057 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ ··· 7617 7065 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ 7618 7066 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) 7619 7067 7620 - /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7621 - #define VCAP_ES2_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES2,\ 7622 - 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7068 + /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7069 + #define VCAP_ES2_VCAP_ENTRY_DAT(r) \ 7070 + __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7623 7071 7624 - /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7625 - #define VCAP_ES2_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES2,\ 7626 - 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7072 + /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7073 + #define VCAP_ES2_VCAP_MASK_DAT(r) \ 7074 + __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7627 7075 7628 - /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7629 - #define VCAP_ES2_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES2,\ 7630 - 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7076 + /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7077 + #define VCAP_ES2_VCAP_ACTION_DAT(r) \ 7078 + __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7631 7079 7632 - /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7633 - #define VCAP_ES2_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES2,\ 7634 - 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7080 + /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7081 + #define VCAP_ES2_VCAP_CNT_DAT(r) \ 7082 + __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7635 7083 7636 - /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7637 - #define VCAP_ES2_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES2,\ 7638 - 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7084 + /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7085 + #define VCAP_ES2_VCAP_CNT_FW_DAT \ 7086 + __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7639 7087 7640 - /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7641 - #define VCAP_ES2_VCAP_TG_DAT __REG(TARGET_VCAP_ES2,\ 7642 - 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7088 + /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7089 + #define VCAP_ES2_VCAP_TG_DAT \ 7090 + __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7643 7091 7644 - /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7645 - #define VCAP_ES2_IDX __REG(TARGET_VCAP_ES2,\ 7646 - 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7092 + /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7093 + #define VCAP_ES2_IDX \ 7094 + __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7647 7095 7648 7096 #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) 7649 7097 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ ··· 7651 7099 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ 7652 7100 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) 7653 7101 7654 - /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7655 - #define VCAP_ES2_MAP __REG(TARGET_VCAP_ES2,\ 7656 - 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7102 + /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7103 + #define VCAP_ES2_MAP \ 7104 + __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7657 7105 7658 7106 #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) 7659 7107 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ ··· 7661 7109 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ 7662 7110 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) 7663 7111 7664 - /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ 7665 - #define VCAP_ES2_VCAP_STICKY __REG(TARGET_VCAP_ES2,\ 7666 - 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7112 + /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ 7113 + #define VCAP_ES2_VCAP_STICKY \ 7114 + __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7667 7115 7668 7116 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7669 7117 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ ··· 7671 7119 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7672 7120 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7673 7121 7674 - /* VCAP_ES2:VCAP_CONST:VCAP_VER */ 7675 - #define VCAP_ES2_VCAP_VER __REG(TARGET_VCAP_ES2,\ 7676 - 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7122 + /* VCAP_ES2:VCAP_CONST:VCAP_VER */ 7123 + #define VCAP_ES2_VCAP_VER \ 7124 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7677 7125 7678 - /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ 7679 - #define VCAP_ES2_ENTRY_WIDTH __REG(TARGET_VCAP_ES2,\ 7680 - 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7126 + /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ 7127 + #define VCAP_ES2_ENTRY_WIDTH \ 7128 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7681 7129 7682 - /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ 7683 - #define VCAP_ES2_ENTRY_CNT __REG(TARGET_VCAP_ES2,\ 7684 - 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7130 + /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ 7131 + #define VCAP_ES2_ENTRY_CNT \ 7132 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7685 7133 7686 - /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ 7687 - #define VCAP_ES2_ENTRY_SWCNT __REG(TARGET_VCAP_ES2,\ 7688 - 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7134 + /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ 7135 + #define VCAP_ES2_ENTRY_SWCNT \ 7136 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7689 7137 7690 - /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ 7691 - #define VCAP_ES2_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES2,\ 7692 - 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7138 + /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ 7139 + #define VCAP_ES2_ENTRY_TG_WIDTH \ 7140 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7693 7141 7694 - /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ 7695 - #define VCAP_ES2_ACTION_DEF_CNT __REG(TARGET_VCAP_ES2,\ 7696 - 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7142 + /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ 7143 + #define VCAP_ES2_ACTION_DEF_CNT \ 7144 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7697 7145 7698 - /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ 7699 - #define VCAP_ES2_ACTION_WIDTH __REG(TARGET_VCAP_ES2,\ 7700 - 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7146 + /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ 7147 + #define VCAP_ES2_ACTION_WIDTH \ 7148 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7701 7149 7702 - /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ 7703 - #define VCAP_ES2_CNT_WIDTH __REG(TARGET_VCAP_ES2,\ 7704 - 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7150 + /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ 7151 + #define VCAP_ES2_CNT_WIDTH \ 7152 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7705 7153 7706 - /* VCAP_ES2:VCAP_CONST:CORE_CNT */ 7707 - #define VCAP_ES2_CORE_CNT __REG(TARGET_VCAP_ES2,\ 7708 - 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7154 + /* VCAP_ES2:VCAP_CONST:CORE_CNT */ 7155 + #define VCAP_ES2_CORE_CNT \ 7156 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7709 7157 7710 - /* VCAP_ES2:VCAP_CONST:IF_CNT */ 7711 - #define VCAP_ES2_IF_CNT __REG(TARGET_VCAP_ES2,\ 7712 - 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7158 + /* VCAP_ES2:VCAP_CONST:IF_CNT */ 7159 + #define VCAP_ES2_IF_CNT \ 7160 + __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7713 7161 7714 - /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7715 - #define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER,\ 7716 - 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7162 + /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7163 + #define VCAP_SUPER_CTRL \ 7164 + __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7717 7165 7718 7166 #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) 7719 7167 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ ··· 7763 7211 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7764 7212 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7765 7213 7766 - /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 7767 - #define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER,\ 7768 - 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7214 + /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 7215 + #define VCAP_SUPER_CFG \ 7216 + __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7769 7217 7770 7218 #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) 7771 7219 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ ··· 7779 7227 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ 7780 7228 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) 7781 7229 7782 - /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7783 - #define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7784 - 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7230 + /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7231 + #define VCAP_SUPER_VCAP_ENTRY_DAT(r) \ 7232 + __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7785 7233 7786 - /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7787 - #define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7788 - 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7234 + /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7235 + #define VCAP_SUPER_VCAP_MASK_DAT(r) \ 7236 + __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7789 7237 7790 - /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7791 - #define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7792 - 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7238 + /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7239 + #define VCAP_SUPER_VCAP_ACTION_DAT(r) \ 7240 + __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7793 7241 7794 - /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7795 - #define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7796 - 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7242 + /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7243 + #define VCAP_SUPER_VCAP_CNT_DAT(r) \ 7244 + __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7797 7245 7798 - /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7799 - #define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER,\ 7800 - 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7246 + /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7247 + #define VCAP_SUPER_VCAP_CNT_FW_DAT \ 7248 + __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7801 7249 7802 - /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7803 - #define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER,\ 7804 - 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7250 + /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7251 + #define VCAP_SUPER_VCAP_TG_DAT \ 7252 + __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7805 7253 7806 - /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7807 - #define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER,\ 7808 - 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7254 + /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7255 + #define VCAP_SUPER_IDX \ 7256 + __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7809 7257 7810 7258 #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) 7811 7259 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ ··· 7813 7261 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ 7814 7262 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) 7815 7263 7816 - /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7817 - #define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER,\ 7818 - 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7264 + /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7265 + #define VCAP_SUPER_MAP \ 7266 + __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7819 7267 7820 7268 #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) 7821 7269 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ ··· 7823 7271 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ 7824 7272 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) 7825 7273 7826 - /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 7827 - #define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER,\ 7828 - 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7274 + /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 7275 + #define VCAP_SUPER_VCAP_VER \ 7276 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7829 7277 7830 - /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 7831 - #define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER,\ 7832 - 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7278 + /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 7279 + #define VCAP_SUPER_ENTRY_WIDTH \ 7280 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7833 7281 7834 - /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 7835 - #define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER,\ 7836 - 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7282 + /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 7283 + #define VCAP_SUPER_ENTRY_CNT \ 7284 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7837 7285 7838 - /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 7839 - #define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER,\ 7840 - 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7286 + /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 7287 + #define VCAP_SUPER_ENTRY_SWCNT \ 7288 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7841 7289 7842 - /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 7843 - #define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER,\ 7844 - 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7290 + /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 7291 + #define VCAP_SUPER_ENTRY_TG_WIDTH \ 7292 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7845 7293 7846 - /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 7847 - #define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER,\ 7848 - 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7294 + /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 7295 + #define VCAP_SUPER_ACTION_DEF_CNT \ 7296 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7849 7297 7850 - /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 7851 - #define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER,\ 7852 - 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7298 + /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 7299 + #define VCAP_SUPER_ACTION_WIDTH \ 7300 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7853 7301 7854 - /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 7855 - #define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER,\ 7856 - 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7302 + /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 7303 + #define VCAP_SUPER_CNT_WIDTH \ 7304 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7857 7305 7858 - /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 7859 - #define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER,\ 7860 - 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7306 + /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 7307 + #define VCAP_SUPER_CORE_CNT \ 7308 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7861 7309 7862 - /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 7863 - #define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER,\ 7864 - 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7310 + /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 7311 + #define VCAP_SUPER_IF_CNT \ 7312 + __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7865 7313 7866 - /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 7867 - #define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER,\ 7868 - 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 7314 + /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 7315 + #define VCAP_SUPER_RAM_INIT \ 7316 + __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 7869 7317 7870 7318 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) 7871 7319 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ ··· 7879 7327 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7880 7328 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 7881 7329 7882 - /* VOP:RAM_CTRL:RAM_INIT */ 7883 - #define VOP_RAM_INIT __REG(TARGET_VOP,\ 7884 - 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4) 7330 + /* VOP:RAM_CTRL:RAM_INIT */ 7331 + #define VOP_RAM_INIT \ 7332 + __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 7333 + 4) 7885 7334 7886 7335 #define VOP_RAM_INIT_RAM_INIT BIT(1) 7887 7336 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ ··· 7896 7343 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7897 7344 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) 7898 7345 7899 - /* XQS:SYSTEM:STAT_CFG */ 7900 - #define XQS_STAT_CFG __REG(TARGET_XQS,\ 7901 - 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4) 7346 + /* XQS:SYSTEM:STAT_CFG */ 7347 + #define XQS_STAT_CFG \ 7348 + __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \ 7349 + 1, 4) 7902 7350 7903 7351 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) 7904 7352 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ ··· 7907 7353 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ 7908 7354 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 7909 7355 7910 - #define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5) 7356 + #define XQS_STAT_CFG_STAT_VIEW\ 7357 + GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5) 7911 7358 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ 7912 - FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x) 7359 + spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x) 7913 7360 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ 7914 - FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x) 7361 + spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x) 7915 7362 7916 7363 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) 7917 7364 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ ··· 7926 7371 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ 7927 7372 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) 7928 7373 7929 - /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 7930 - #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\ 7931 - 0, 1, 7936, g, 4, 48, 0, 0, 1, 4) 7374 + /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 7375 + #define XQS_QLIMIT_SHR_TOP_CFG(g) \ 7376 + __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\ 7377 + 1, 4) 7932 7378 7933 - #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0) 7379 + #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP\ 7380 + GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0) 7934 7381 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ 7935 - FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7382 + spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7936 7383 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ 7937 - FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7384 + spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7938 7385 7939 - /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 7940 - #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\ 7941 - 0, 1, 7936, g, 4, 48, 4, 0, 1, 4) 7386 + /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 7387 + #define XQS_QLIMIT_SHR_ATOP_CFG(g) \ 7388 + __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\ 7389 + 1, 4) 7942 7390 7943 - #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0) 7391 + #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP\ 7392 + GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0) 7944 7393 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ 7945 - FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7394 + spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7946 7395 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ 7947 - FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7396 + spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7948 7397 7949 - /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 7950 - #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\ 7951 - 0, 1, 7936, g, 4, 48, 8, 0, 1, 4) 7398 + /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 7399 + #define XQS_QLIMIT_SHR_CTOP_CFG(g) \ 7400 + __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\ 7401 + 1, 4) 7952 7402 7953 - #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0) 7403 + #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP\ 7404 + GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0) 7954 7405 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ 7955 - FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7406 + spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7956 7407 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ 7957 - FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7408 + spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7958 7409 7959 - /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 7960 - #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\ 7961 - 0, 1, 7936, g, 4, 48, 12, 0, 1, 4) 7410 + /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 7411 + #define XQS_QLIMIT_SHR_QLIM_CFG(g) \ 7412 + __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12, \ 7413 + 0, 1, 4) 7962 7414 7963 - #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0) 7415 + #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM\ 7416 + GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0) 7964 7417 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ 7965 - FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7418 + spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7966 7419 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ 7967 - FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7420 + spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7968 7421 7969 - /* XQS:STAT:CNT */ 7970 - #define XQS_CNT(g) __REG(TARGET_XQS,\ 7971 - 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 7422 + /* XQS:STAT:CNT */ 7423 + #define XQS_CNT(g) \ 7424 + __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 7972 7425 7973 7426 #endif /* _SPARX5_MAIN_REGS_H_ */
+8 -7
drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
··· 55 55 ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); 56 56 } 57 57 58 - void sparx5_set_port_ifh(void *ifh_hdr, u16 portno) 58 + void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) 59 59 { 60 60 /* VSTAX.RSV = 1. MSBit must be 1 */ 61 61 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1); ··· 68 68 /* MISC.PIPELINE_ACT */ 69 69 ifh_encode_bitfield(ifh_hdr, 1, 42, 3); 70 70 /* FWD.SRC_PORT = CPU */ 71 - ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7); 71 + ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), 72 + 46, 7); 72 73 /* FWD.SFLOW_ID (disable SFlow sampling) */ 73 74 ifh_encode_bitfield(ifh_hdr, 124, 57, 7); 74 75 /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ ··· 191 190 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); 192 191 193 192 /* Add new */ 194 - sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); 193 + sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), 194 + addr->sa_data, port->pvid); 195 195 196 196 /* Record the address */ 197 197 eth_hw_addr_set(dev, addr->sa_data); ··· 292 290 int portno; 293 291 int err; 294 292 295 - for (portno = 0; portno < SPX5_PORTS; portno++) 293 + for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) 296 294 if (sparx5->ports[portno]) { 297 295 err = register_netdev(sparx5->ports[portno]->ndev); 298 296 if (err) { ··· 311 309 struct sparx5_port *port; 312 310 int portno; 313 311 314 - for (portno = 0; portno < SPX5_PORTS; portno++) { 312 + for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) { 315 313 port = sparx5->ports[portno]; 316 314 if (port && port->phylink) { 317 315 /* Disconnect the phy */ ··· 329 327 { 330 328 int portno; 331 329 332 - for (portno = 0; portno < SPX5_PORTS; portno++) 330 + for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) 333 331 if (sparx5->ports[portno]) 334 332 unregister_netdev(sparx5->ports[portno]->ndev); 335 333 } 336 -
+5 -3
drivers/net/ethernet/microchip/sparx5/sparx5_packet.c
··· 75 75 sparx5_ifh_parse(ifh, &fi); 76 76 77 77 /* Map to port netdev */ 78 - port = fi.src_port < SPX5_PORTS ? 78 + port = fi.src_port < sparx5->data->consts->n_ports ? 79 79 sparx5->ports[fi.src_port] : NULL; 80 80 if (!port || !port->ndev) { 81 81 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); ··· 235 235 netdev_tx_t ret; 236 236 237 237 memset(ifh, 0, IFH_LEN * 4); 238 - sparx5_set_port_ifh(ifh, port->portno); 238 + sparx5_set_port_ifh(sparx5, ifh, port->portno); 239 239 240 240 if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 241 241 if (sparx5_ptp_txtstamp_request(port, skb) < 0) ··· 317 317 sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); 318 318 319 319 /* CPU ports capture setup */ 320 - for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) { 320 + for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); 321 + portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); 322 + portno++) { 321 323 /* ASM CPU port: No preamble, IFH, enable padding */ 322 324 spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) | 323 325 ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |
+11 -4
drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c
··· 5 5 { 6 6 int i; 7 7 8 - for (i = 0; i < PGID_TABLE_SIZE; i++) 8 + for (i = 0; i < spx5->data->consts->n_pgids; i++) 9 9 spx5->pgid_map[i] = SPX5_PGID_FREE; 10 10 11 11 /* Reserved for unicast, flood control, broadcast, and CPU. 12 12 * These cannot be freed. 13 13 */ 14 - for (i = 0; i <= PGID_CPU; i++) 14 + for (i = 0; i <= sparx5_get_pgid(spx5, PGID_CPU); i++) 15 15 spx5->pgid_map[i] = SPX5_PGID_RESERVED; 16 16 } 17 17 ··· 22 22 /* The multicast area starts at index 65, but the first 7 23 23 * are reserved for flood masks and CPU. Start alloc after that. 24 24 */ 25 - for (i = PGID_MCAST_START; i < PGID_TABLE_SIZE; i++) { 25 + for (i = sparx5_get_pgid(spx5, PGID_MCAST_START); 26 + i < spx5->data->consts->n_pgids; i++) { 26 27 if (spx5->pgid_map[i] == SPX5_PGID_FREE) { 27 28 spx5->pgid_map[i] = SPX5_PGID_MULTICAST; 28 29 *idx = i; ··· 36 35 37 36 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx) 38 37 { 39 - if (idx <= PGID_CPU || idx >= PGID_TABLE_SIZE) 38 + if (idx <= sparx5_get_pgid(spx5, PGID_CPU) || 39 + idx >= spx5->data->consts->n_pgids) 40 40 return -EINVAL; 41 41 42 42 if (spx5->pgid_map[idx] == SPX5_PGID_FREE) ··· 45 43 46 44 spx5->pgid_map[idx] = SPX5_PGID_FREE; 47 45 return 0; 46 + } 47 + 48 + int sparx5_get_pgid(struct sparx5 *sparx5, int pgid) 49 + { 50 + return sparx5->data->consts->n_ports + pgid; 48 51 }
+2 -1
drivers/net/ethernet/microchip/sparx5/sparx5_police.c
··· 11 11 struct sparx5_policer *pol) 12 12 { 13 13 u32 idx, pup_tokens, max_pup_tokens, burst, thres; 14 + const struct sparx5_ops *ops = sparx5->data->ops; 14 15 struct sparx5_sdlb_group *g; 15 16 u64 rate; 16 17 17 - g = &sdlb_groups[pol->group]; 18 + g = ops->get_sdlb_group(pol->group); 18 19 idx = pol->idx; 19 20 20 21 rate = pol->rate * 1000;
+44 -32
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
··· 132 132 return -EINVAL; 133 133 } 134 134 135 - dev = sparx5_to_high_dev(portno); 136 - tinst = sparx5_port_dev_index(portno); 135 + dev = sparx5_to_high_dev(sparx5, portno); 136 + tinst = sparx5_port_dev_index(sparx5, portno); 137 137 inst = spx5_inst_get(sparx5, dev, tinst); 138 138 139 139 value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0)); ··· 213 213 struct sparx5_port *port, 214 214 struct sparx5_port_config *conf) 215 215 { 216 - if ((sparx5_port_is_2g5(port->portno) && 216 + const struct sparx5_ops *ops = sparx5->data->ops; 217 + 218 + if ((ops->is_port_2g5(port->portno) && 217 219 conf->speed > SPEED_2500) || 218 - (sparx5_port_is_5g(port->portno) && 220 + (ops->is_port_5g(port->portno) && 219 221 conf->speed > SPEED_5000) || 220 - (sparx5_port_is_10g(port->portno) && 222 + (ops->is_port_10g(port->portno) && 221 223 conf->speed > SPEED_10000)) 222 224 return sparx5_port_error(port, conf, SPX5_PERR_SPEED); 223 225 ··· 228 226 return -EINVAL; 229 227 case PHY_INTERFACE_MODE_1000BASEX: 230 228 if (conf->speed != SPEED_1000 || 231 - sparx5_port_is_2g5(port->portno)) 229 + ops->is_port_2g5(port->portno)) 232 230 return sparx5_port_error(port, conf, SPX5_PERR_SPEED); 233 - if (sparx5_port_is_2g5(port->portno)) 231 + if (ops->is_port_2g5(port->portno)) 234 232 return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); 235 233 break; 236 234 case PHY_INTERFACE_MODE_2500BASEX: 237 235 if (conf->speed != SPEED_2500 || 238 - sparx5_port_is_2g5(port->portno)) 236 + ops->is_port_2g5(port->portno)) 239 237 return sparx5_port_error(port, conf, SPX5_PERR_SPEED); 240 238 break; 241 239 case PHY_INTERFACE_MODE_QSGMII: ··· 318 316 static int sparx5_port_disable(struct sparx5 *sparx5, struct sparx5_port *port, bool high_spd_dev) 319 317 { 320 318 u32 tinst = high_spd_dev ? 321 - sparx5_port_dev_index(port->portno) : port->portno; 319 + sparx5_port_dev_index(sparx5, port->portno) : port->portno; 322 320 u32 dev = high_spd_dev ? 323 - sparx5_to_high_dev(port->portno) : TARGET_DEV2G5; 321 + sparx5_to_high_dev(sparx5, port->portno) : TARGET_DEV2G5; 324 322 void __iomem *devinst = spx5_inst_get(sparx5, dev, tinst); 323 + const struct sparx5_ops *ops = sparx5->data->ops; 325 324 u32 spd = port->conf.speed; 326 325 u32 spd_prm; 327 326 int err; ··· 430 427 HSCH_FLUSH_CTRL); 431 428 432 429 if (high_spd_dev) { 433 - u32 pcs = sparx5_to_pcs_dev(port->portno); 430 + u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); 434 431 void __iomem *pcsinst = spx5_inst_get(sparx5, pcs, tinst); 435 432 436 433 /* 12: Disable 5G/10G/25 BaseR PCS */ ··· 439 436 pcsinst, 440 437 PCS10G_BR_PCS_CFG(0)); 441 438 442 - if (sparx5_port_is_25g(port->portno)) 439 + if (ops->is_port_25g(port->portno)) 443 440 /* Disable 25G PCS */ 444 441 spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0), 445 442 DEV25G_PCS25G_CFG_PCS25G_ENA, ··· 516 513 /* Configure port muxing: 517 514 * QSGMII: 4x2G5 devices 518 515 */ 519 - static int sparx5_port_mux_set(struct sparx5 *sparx5, 520 - struct sparx5_port *port, 521 - struct sparx5_port_config *conf) 516 + int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, 517 + struct sparx5_port_config *conf) 522 518 { 523 519 u32 portno = port->portno; 524 520 u32 inst; ··· 560 558 bool dtag = max_tags == SPX5_PORT_MAX_TAGS_TWO; 561 559 enum sparx5_vlan_port_type vlan_type = port->vlan_type; 562 560 bool dotag = max_tags != SPX5_PORT_MAX_TAGS_NONE; 563 - u32 dev = sparx5_to_high_dev(port->portno); 564 - u32 tinst = sparx5_port_dev_index(port->portno); 561 + u32 dev = sparx5_to_high_dev(sparx5, port->portno); 562 + u32 tinst = sparx5_port_dev_index(sparx5, port->portno); 565 563 void __iomem *inst = spx5_inst_get(sparx5, dev, tinst); 564 + const struct sparx5_ops *ops = sparx5->data->ops; 566 565 u32 etype; 567 566 568 567 etype = (vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? ··· 578 575 sparx5, 579 576 DEV2G5_MAC_TAGS_CFG(port->portno)); 580 577 581 - if (sparx5_port_is_2g5(port->portno)) 578 + if (ops->is_port_2g5(port->portno)) 582 579 return 0; 583 580 584 581 spx5_inst_rmw(DEV10G_MAC_TAGS_CFG_TAG_ID_SET(etype) | ··· 792 789 struct sparx5_port_config *conf) 793 790 { 794 791 u32 clk_spd = conf->portmode == PHY_INTERFACE_MODE_5GBASER ? 1 : 0; 795 - u32 pix = sparx5_port_dev_index(port->portno); 796 - u32 dev = sparx5_to_high_dev(port->portno); 797 - u32 pcs = sparx5_to_pcs_dev(port->portno); 792 + u32 pix = sparx5_port_dev_index(sparx5, port->portno); 793 + u32 dev = sparx5_to_high_dev(sparx5, port->portno); 794 + u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); 798 795 void __iomem *devinst; 799 796 void __iomem *pcsinst; 800 797 int err; ··· 846 843 /* Switch between 1G/2500 and 5G/10G/25G devices */ 847 844 static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) 848 845 { 849 - int bt_indx = BIT(sparx5_port_dev_index(port)); 846 + const struct sparx5_ops *ops = sparx5->data->ops; 847 + int bt_indx; 850 848 851 - if (sparx5_port_is_5g(port)) { 849 + bt_indx = BIT(ops->get_port_dev_bit(sparx5, port)); 850 + 851 + if (ops->is_port_5g(port)) { 852 852 spx5_rmw(hsd ? 0 : bt_indx, 853 853 bt_indx, 854 854 sparx5, 855 855 PORT_CONF_DEV5G_MODES); 856 - } else if (sparx5_port_is_10g(port)) { 856 + } else if (ops->is_port_10g(port)) { 857 857 spx5_rmw(hsd ? 0 : bt_indx, 858 858 bt_indx, 859 859 sparx5, 860 860 PORT_CONF_DEV10G_MODES); 861 - } else if (sparx5_port_is_25g(port)) { 861 + } else if (ops->is_port_25g(port)) { 862 862 spx5_rmw(hsd ? 0 : bt_indx, 863 863 bt_indx, 864 864 sparx5, ··· 1022 1016 { 1023 1017 u32 pause_start = sparx5_wm_enc(6 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); 1024 1018 u32 atop = sparx5_wm_enc(20 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); 1025 - u32 devhigh = sparx5_to_high_dev(port->portno); 1026 - u32 pix = sparx5_port_dev_index(port->portno); 1027 - u32 pcs = sparx5_to_pcs_dev(port->portno); 1019 + const struct sparx5_ops *ops = sparx5->data->ops; 1020 + u32 devhigh = sparx5_to_high_dev(sparx5, port->portno); 1021 + u32 pix = sparx5_port_dev_index(sparx5, port->portno); 1022 + u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); 1028 1023 bool sd_pol = port->signd_active_high; 1029 1024 bool sd_sel = !port->signd_internal; 1030 1025 bool sd_ena = port->signd_enable; ··· 1038 1031 pcsinst = spx5_inst_get(sparx5, pcs, pix); 1039 1032 1040 1033 /* Set the mux port mode */ 1041 - err = sparx5_port_mux_set(sparx5, port, conf); 1034 + err = ops->set_port_mux(sparx5, port, conf); 1042 1035 if (err) 1043 1036 return err; 1044 1037 ··· 1089 1082 if (err) 1090 1083 return err; 1091 1084 1092 - if (!sparx5_port_is_2g5(port->portno)) 1085 + if (!ops->is_port_2g5(port->portno)) 1093 1086 /* Enable shadow device */ 1094 1087 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), 1095 1088 DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, ··· 1112 1105 sparx5, 1113 1106 DEV2G5_MAC_IFG_CFG(port->portno)); 1114 1107 1115 - if (sparx5_port_is_2g5(port->portno)) 1108 + if (ops->is_port_2g5(port->portno)) 1116 1109 return 0; /* Low speed device only - return */ 1117 1110 1118 1111 /* Now setup the high speed device */ ··· 1135 1128 pcsinst, 1136 1129 PCS10G_BR_PCS_SD_CFG(0)); 1137 1130 1138 - if (sparx5_port_is_25g(port->portno)) { 1131 + if (ops->is_port_25g(port->portno)) { 1139 1132 /* Handle Signal Detect in 25G PCS */ 1140 1133 spx5_wr(DEV25G_PCS25G_SD_CFG_SD_POL_SET(sd_pol) | 1141 1134 DEV25G_PCS25G_SD_CFG_SD_SEL_SET(sd_sel) | ··· 1351 1344 sparx5, ANA_CL_VLAN_CTRL(port->portno)); 1352 1345 1353 1346 return 0; 1347 + } 1348 + 1349 + int sparx5_get_internal_port(struct sparx5 *sparx5, int port) 1350 + { 1351 + return sparx5->data->consts->n_ports + port; 1354 1352 }
+16 -7
drivers/net/ethernet/microchip/sparx5/sparx5_port.h
··· 40 40 return portno >= 56 && portno <= 63; 41 41 } 42 42 43 - static inline u32 sparx5_to_high_dev(int port) 43 + static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) 44 44 { 45 - if (sparx5_port_is_5g(port)) 45 + const struct sparx5_ops *ops = sparx5->data->ops; 46 + 47 + if (ops->is_port_5g(port)) 46 48 return TARGET_DEV5G; 47 - if (sparx5_port_is_10g(port)) 49 + if (ops->is_port_10g(port)) 48 50 return TARGET_DEV10G; 49 51 return TARGET_DEV25G; 50 52 } 51 53 52 - static inline u32 sparx5_to_pcs_dev(int port) 54 + static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) 53 55 { 54 - if (sparx5_port_is_5g(port)) 56 + const struct sparx5_ops *ops = sparx5->data->ops; 57 + 58 + if (ops->is_port_5g(port)) 55 59 return TARGET_PCS5G_BR; 56 - if (sparx5_port_is_10g(port)) 60 + if (ops->is_port_10g(port)) 57 61 return TARGET_PCS10G_BR; 58 62 return TARGET_PCS25G_BR; 59 63 } 60 64 61 - static inline int sparx5_port_dev_index(int port) 65 + static inline u32 sparx5_port_dev_mapping(struct sparx5 *sparx5, int port) 62 66 { 63 67 if (sparx5_port_is_2g5(port)) 64 68 return port; ··· 72 68 return (port >= 12 && port <= 15) ? 73 69 port - 12 : port - 44; 74 70 return (port - 56); 71 + } 72 + 73 + static inline u32 sparx5_port_dev_index(struct sparx5 *sparx5, int port) 74 + { 75 + return sparx5->data->ops->get_port_dev_index(sparx5, port); 75 76 } 76 77 77 78 int sparx5_port_init(struct sparx5 *sparx5,
+27 -22
drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c
··· 20 20 /* Pool of available stream filters */ 21 21 static struct sparx5_pool_entry sparx5_psfp_sf_pool[SPX5_PSFP_SF_CNT]; 22 22 23 - static int sparx5_psfp_sf_get(u32 *id) 23 + static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) 24 24 { 25 - return sparx5_pool_get(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); 25 + return sparx5_pool_get(sparx5_psfp_sf_pool, 26 + sparx5->data->consts->n_filters, id); 26 27 } 27 28 28 - static int sparx5_psfp_sf_put(u32 id) 29 + static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) 29 30 { 30 - return sparx5_pool_put(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); 31 + return sparx5_pool_put(sparx5_psfp_sf_pool, 32 + sparx5->data->consts->n_filters, id); 31 33 } 32 34 33 - static int sparx5_psfp_sg_get(u32 idx, u32 *id) 35 + static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) 34 36 { 35 - return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, 36 - idx, id); 37 + return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, 38 + sparx5->data->consts->n_gates, idx, id); 37 39 } 38 40 39 - static int sparx5_psfp_sg_put(u32 id) 41 + static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) 40 42 { 41 - return sparx5_pool_put(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, id); 43 + return sparx5_pool_put(sparx5_psfp_sg_pool, 44 + sparx5->data->consts->n_gates, id); 42 45 } 43 46 44 - static int sparx5_psfp_fm_get(u32 idx, u32 *id) 47 + static int sparx5_psfp_fm_get(struct sparx5 *sparx5, u32 idx, u32 *id) 45 48 { 46 - return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, idx, 47 - id); 49 + return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, 50 + sparx5->data->consts->n_sdlbs, idx, id); 48 51 } 49 52 50 - static int sparx5_psfp_fm_put(u32 id) 53 + static int sparx5_psfp_fm_put(struct sparx5 *sparx5, u32 id) 51 54 { 52 - return sparx5_pool_put(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, id); 55 + return sparx5_pool_put(sparx5_psfp_fm_pool, 56 + sparx5->data->consts->n_sdlbs, id); 53 57 } 54 58 55 59 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx) ··· 209 205 { 210 206 int ret; 211 207 212 - ret = sparx5_psfp_sf_get(id); 208 + ret = sparx5_psfp_sf_get(sparx5, id); 213 209 if (ret < 0) 214 210 return ret; 215 211 ··· 224 220 225 221 sparx5_psfp_sf_set(sparx5, id, &sf); 226 222 227 - return sparx5_psfp_sf_put(id); 223 + return sparx5_psfp_sf_put(sparx5, id); 228 224 } 229 225 230 226 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, ··· 233 229 ktime_t basetime; 234 230 int ret; 235 231 236 - ret = sparx5_psfp_sg_get(uidx, id); 232 + ret = sparx5_psfp_sg_get(sparx5, uidx, id); 237 233 if (ret < 0) 238 234 return ret; 239 235 /* Was already in use, no need to reconfigure */ ··· 257 253 const struct sparx5_psfp_sg sg = { 0 }; 258 254 int ret; 259 255 260 - ret = sparx5_psfp_sg_put(id); 256 + ret = sparx5_psfp_sg_put(sparx5, id); 261 257 if (ret < 0) 262 258 return ret; 263 259 /* Stream gate still in use ? */ ··· 274 270 int ret; 275 271 276 272 /* Get flow meter */ 277 - ret = sparx5_psfp_fm_get(uidx, &fm->pol.idx); 273 + ret = sparx5_psfp_fm_get(sparx5, uidx, &fm->pol.idx); 278 274 if (ret < 0) 279 275 return ret; 280 276 /* Was already in use, no need to reconfigure */ ··· 307 303 if (ret < 0) 308 304 return ret; 309 305 310 - ret = sparx5_psfp_fm_put(id); 306 + ret = sparx5_psfp_fm_put(sparx5, id); 311 307 if (ret < 0) 312 308 return ret; 313 309 /* Do not reset flow-meter if still in use. */ ··· 319 315 320 316 void sparx5_psfp_init(struct sparx5 *sparx5) 321 317 { 318 + const struct sparx5_ops *ops = sparx5->data->ops; 322 319 const struct sparx5_sdlb_group *group; 323 320 int i; 324 321 325 - for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { 326 - group = &sdlb_groups[i]; 322 + for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { 323 + group = ops->get_sdlb_group(i); 327 324 sparx5_sdlb_group_init(sparx5, group->max_rate, 328 325 group->min_burst, group->frame_size, i); 329 326 }
+27 -17
drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
··· 274 274 u32 nsec) 275 275 { 276 276 /* Read current PTP time to get seconds */ 277 + const struct sparx5_consts *consts = sparx5->data->consts; 277 278 unsigned long flags; 278 279 u32 curr_nsec; 279 280 ··· 286 285 PTP_PTP_PIN_CFG_PTP_PIN_ACTION | 287 286 PTP_PTP_PIN_CFG_PTP_PIN_DOM | 288 287 PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 289 - sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); 288 + sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); 290 289 291 - ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); 292 - curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); 290 + ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); 291 + curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); 293 292 294 293 ts->tv_nsec = nsec; 295 294 ··· 441 440 { 442 441 struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); 443 442 struct sparx5 *sparx5 = phc->sparx5; 443 + const struct sparx5_consts *consts; 444 444 unsigned long flags; 445 + 446 + consts = sparx5->data->consts; 445 447 446 448 spin_lock_irqsave(&sparx5->ptp_clock_lock, flags); 447 449 ··· 455 451 PTP_PTP_PIN_CFG_PTP_PIN_ACTION | 456 452 PTP_PTP_PIN_CFG_PTP_PIN_DOM | 457 453 PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 458 - sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); 454 + sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); 459 455 460 456 /* Set new value */ 461 457 spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), 462 - sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); 458 + sparx5, PTP_PTP_TOD_SEC_MSB(consts->tod_pin)); 463 459 spx5_wr(lower_32_bits(ts->tv_sec), 464 - sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); 465 - spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); 460 + sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); 461 + spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); 466 462 467 463 /* Apply new values */ 468 464 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | ··· 471 467 PTP_PTP_PIN_CFG_PTP_PIN_ACTION | 472 468 PTP_PTP_PIN_CFG_PTP_PIN_DOM | 473 469 PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 474 - sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); 470 + sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); 475 471 476 472 spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); 477 473 ··· 482 478 { 483 479 struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); 484 480 struct sparx5 *sparx5 = phc->sparx5; 481 + const struct sparx5_consts *consts; 485 482 unsigned long flags; 486 483 time64_t s; 487 484 s64 ns; 485 + 486 + consts = sparx5->data->consts; 488 487 489 488 spin_lock_irqsave(&sparx5->ptp_clock_lock, flags); 490 489 ··· 497 490 PTP_PTP_PIN_CFG_PTP_PIN_ACTION | 498 491 PTP_PTP_PIN_CFG_PTP_PIN_DOM | 499 492 PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 500 - sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); 493 + sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); 501 494 502 - s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); 495 + s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(consts->tod_pin)); 503 496 s <<= 32; 504 - s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); 505 - ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); 497 + s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); 498 + ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); 506 499 ns &= PTP_PTP_TOD_NSEC_PTP_TOD_NSEC; 507 500 508 501 spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); ··· 522 515 { 523 516 struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); 524 517 struct sparx5 *sparx5 = phc->sparx5; 518 + const struct sparx5_consts *consts; 519 + 520 + consts = sparx5->data->consts; 525 521 526 522 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { 527 523 unsigned long flags; ··· 538 528 PTP_PTP_PIN_CFG_PTP_PIN_ACTION | 539 529 PTP_PTP_PIN_CFG_PTP_PIN_DOM | 540 530 PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 541 - sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); 531 + sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); 542 532 543 533 spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), 544 - sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); 534 + sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); 545 535 546 536 /* Adjust time with the value of PTP_TOD_NSEC */ 547 537 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) | ··· 550 540 PTP_PTP_PIN_CFG_PTP_PIN_ACTION | 551 541 PTP_PTP_PIN_CFG_PTP_PIN_DOM | 552 542 PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 553 - sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); 543 + sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); 554 544 555 545 spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); 556 546 } else { ··· 640 630 /* Enable master counters */ 641 631 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); 642 632 643 - for (i = 0; i < SPX5_PORTS; i++) { 633 + for (i = 0; i < sparx5->data->consts->n_ports; i++) { 644 634 port = sparx5->ports[i]; 645 635 if (!port) 646 636 continue; ··· 656 646 struct sparx5_port *port; 657 647 int i; 658 648 659 - for (i = 0; i < SPX5_PORTS; i++) { 649 + for (i = 0; i < sparx5->data->consts->n_ports; i++) { 660 650 port = sparx5->ports[i]; 661 651 if (!port) 662 652 continue;
+7 -1
drivers/net/ethernet/microchip/sparx5/sparx5_qos.c
··· 74 74 26214200 /* 26.214 Gbps */ 75 75 }; 76 76 77 + u32 sparx5_get_hsch_max_group_rate(int grp) 78 + { 79 + return spx5_hsch_max_group_rate[grp]; 80 + } 81 + 77 82 static struct sparx5_layer layers[SPX5_HSCH_LAYER_CNT]; 78 83 79 84 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) ··· 390 385 391 386 static int sparx5_leak_groups_init(struct sparx5 *sparx5) 392 387 { 388 + const struct sparx5_ops *ops = sparx5->data->ops; 393 389 struct sparx5_layer *layer; 394 390 u32 sys_clk_per_100ps; 395 391 struct sparx5_lg *lg; ··· 403 397 layer = &layers[i]; 404 398 for (ii = 0; ii < SPX5_HSCH_LEAK_GRP_CNT; ii++) { 405 399 lg = &layer->leak_groups[ii]; 406 - lg->max_rate = spx5_hsch_max_group_rate[ii]; 400 + lg->max_rate = ops->get_hsch_max_group_rate(i); 407 401 408 402 /* Calculate the leak time in us, to serve a maximum 409 403 * rate of 'max_rate' for this group
+2
drivers/net/ethernet/microchip/sparx5/sparx5_qos.h
··· 79 79 80 80 int sparx5_tc_ets_del(struct sparx5_port *port); 81 81 82 + u32 sparx5_get_hsch_max_group_rate(int grp); 83 + 82 84 #endif /* __SPARX5_QOS_H__ */
+219
drivers/net/ethernet/microchip/sparx5/sparx5_regs.c
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* Microchip Sparx5 Switch driver 3 + * 4 + * Copyright (c) 2024 Microchip Technology Inc. 5 + */ 6 + 7 + /* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. 8 + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b 9 + */ 10 + 11 + #include "sparx5_regs.h" 12 + 13 + const unsigned int sparx5_tsize[TSIZE_LAST] = { 14 + [TC_DEV10G] = 12, 15 + [TC_DEV2G5] = 65, 16 + [TC_DEV5G] = 13, 17 + [TC_PCS10G_BR] = 12, 18 + [TC_PCS5G_BR] = 13, 19 + }; 20 + 21 + const unsigned int sparx5_raddr[RADDR_LAST] = { 22 + [RA_CPU_PROC_CTRL] = 176, 23 + [RA_GCB_SOFT_RST] = 8, 24 + [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24, 25 + }; 26 + 27 + const unsigned int sparx5_rcnt[RCNT_LAST] = { 28 + [RC_ANA_AC_OWN_UPSID] = 3, 29 + [RC_ANA_ACL_VCAP_S2_CFG] = 70, 30 + [RC_ANA_ACL_OWN_UPSID] = 3, 31 + [RC_ANA_CL_OWN_UPSID] = 3, 32 + [RC_ANA_L2_OWN_UPSID] = 3, 33 + [RC_ASM_PORT_CFG] = 67, 34 + [RC_DSM_BUF_CFG] = 67, 35 + [RC_DSM_DEV_TX_STOP_WM_CFG] = 67, 36 + [RC_DSM_RX_PAUSE_CFG] = 67, 37 + [RC_DSM_MAC_CFG] = 67, 38 + [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65, 39 + [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65, 40 + [RC_DSM_TAXI_CAL_CFG] = 9, 41 + [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65, 42 + [RC_HSCH_PORT_MODE] = 70, 43 + [RC_QFWD_SWITCH_PORT_MODE] = 70, 44 + [RC_QSYS_PAUSE_CFG] = 70, 45 + [RC_QSYS_ATOP] = 70, 46 + [RC_QSYS_FWD_PRESSURE] = 70, 47 + [RC_QSYS_CAL_AUTO] = 7, 48 + [RC_REW_OWN_UPSID] = 3, 49 + [RC_REW_RTAG_ETAG_CTRL] = 70, 50 + }; 51 + 52 + const unsigned int sparx5_gaddr[GADDR_LAST] = { 53 + [GA_ANA_AC_RAM_CTRL] = 839108, 54 + [GA_ANA_AC_PS_COMMON] = 894472, 55 + [GA_ANA_AC_MIRROR_PROBE] = 893696, 56 + [GA_ANA_AC_SRC] = 849920, 57 + [GA_ANA_AC_PGID] = 786432, 58 + [GA_ANA_AC_TSN_SF] = 839136, 59 + [GA_ANA_AC_TSN_SF_CFG] = 839680, 60 + [GA_ANA_AC_TSN_SF_STATUS] = 839072, 61 + [GA_ANA_AC_SG_ACCESS] = 839140, 62 + [GA_ANA_AC_SG_CONFIG] = 851584, 63 + [GA_ANA_AC_SG_STATUS] = 839088, 64 + [GA_ANA_AC_SG_STATUS_STICKY] = 839152, 65 + [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552, 66 + [GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776, 67 + [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792, 68 + [GA_ANA_ACL_COMMON] = 32768, 69 + [GA_ANA_ACL_KEY_SEL] = 34200, 70 + [GA_ANA_ACL_CNT_B] = 16384, 71 + [GA_ANA_ACL_STICKY] = 36408, 72 + [GA_ANA_AC_POL_POL_ALL_CFG] = 75968, 73 + [GA_ANA_AC_POL_COMMON_BDLB] = 79048, 74 + [GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056, 75 + [GA_ANA_AC_SDLB_LBGRP_TBL] = 295468, 76 + [GA_ANA_CL_PORT] = 131072, 77 + [GA_ANA_CL_COMMON] = 166912, 78 + [GA_ANA_L2_COMMON] = 566024, 79 + [GA_ANA_L3_COMMON] = 493632, 80 + [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460, 81 + [GA_ASM_CFG] = 33280, 82 + [GA_ASM_PFC_TIMER_CFG] = 34716, 83 + [GA_ASM_LBK_WM_CFG] = 34744, 84 + [GA_ASM_LBK_MISC_CFG] = 34756, 85 + [GA_ASM_RAM_CTRL] = 34832, 86 + [GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504, 87 + [GA_EACL_CNT_TBL] = 122880, 88 + [GA_EACL_POL_CFG] = 150608, 89 + [GA_EACL_ES2_STICKY] = 118696, 90 + [GA_EACL_RAM_CTRL] = 118736, 91 + [GA_GCB_SIO_CTRL] = 876, 92 + [GA_HSCH_HSCH_DWRR] = 162816, 93 + [GA_HSCH_HSCH_MISC] = 163104, 94 + [GA_HSCH_HSCH_LEAK_LISTS] = 161664, 95 + [GA_HSCH_SYSTEM] = 184000, 96 + [GA_HSCH_MMGT] = 162368, 97 + [GA_HSCH_TAS_CONFIG] = 162384, 98 + [GA_PTP_PTP_CFG] = 320, 99 + [GA_PTP_PTP_TOD_DOMAINS] = 336, 100 + [GA_PTP_PHASE_DETECTOR_CTRL] = 420, 101 + [GA_QSYS_CALCFG] = 2304, 102 + [GA_QSYS_RAM_CTRL] = 2344, 103 + [GA_REW_COMMON] = 387264, 104 + [GA_REW_PORT] = 360448, 105 + [GA_REW_VOE_PORT_LM_CNT] = 393216, 106 + [GA_REW_RAM_CTRL] = 378696, 107 + [GA_VOP_RAM_CTRL] = 279176, 108 + [GA_XQS_SYSTEM] = 6768, 109 + [GA_XQS_QLIMIT_SHR] = 7936, 110 + }; 111 + 112 + const unsigned int sparx5_gcnt[GCNT_LAST] = { 113 + [GC_ANA_AC_SRC] = 102, 114 + [GC_ANA_AC_PGID] = 3290, 115 + [GC_ANA_AC_TSN_SF_CFG] = 1024, 116 + [GC_ANA_AC_STAT_CNT_CFG_PORT] = 70, 117 + [GC_ANA_ACL_KEY_SEL] = 134, 118 + [GC_ANA_ACL_CNT_A] = 4096, 119 + [GC_ANA_ACL_CNT_B] = 4096, 120 + [GC_ANA_AC_SDLB_LBGRP_TBL] = 10, 121 + [GC_ANA_AC_SDLB_LBSET_TBL] = 4616, 122 + [GC_ANA_CL_PORT] = 70, 123 + [GC_ANA_L2_ISDX_LIMIT] = 1536, 124 + [GC_ANA_L2_ISDX] = 4096, 125 + [GC_ANA_L3_VLAN] = 5120, 126 + [GC_ASM_DEV_STATISTICS] = 65, 127 + [GC_EACL_ES2_KEY_SELECT_PROFILE] = 138, 128 + [GC_EACL_CNT_TBL] = 2048, 129 + [GC_GCB_SIO_CTRL] = 3, 130 + [GC_HSCH_HSCH_CFG] = 5040, 131 + [GC_HSCH_HSCH_DWRR] = 72, 132 + [GC_PTP_PTP_PINS] = 5, 133 + [GC_PTP_PHASE_DETECTOR_CTRL] = 5, 134 + [GC_REW_PORT] = 70, 135 + [GC_REW_VOE_PORT_LM_CNT] = 520, 136 + }; 137 + 138 + const unsigned int sparx5_gsize[GSIZE_LAST] = { 139 + [GW_ANA_AC_SRC] = 16, 140 + [GW_ANA_L2_COMMON] = 700, 141 + [GW_ASM_CFG] = 1088, 142 + [GW_CPU_CPU_REGS] = 204, 143 + [GW_FDMA_FDMA] = 428, 144 + [GW_GCB_CHIP_REGS] = 424, 145 + [GW_HSCH_TAS_CONFIG] = 12, 146 + [GW_PTP_PHASE_DETECTOR_CTRL] = 8, 147 + [GW_QSYS_PAUSE_CFG] = 1128, 148 + }; 149 + 150 + const unsigned int sparx5_fpos[FPOS_LAST] = { 151 + [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 12, 152 + [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 11, 153 + [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 10, 154 + [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 9, 155 + [FP_CPU_PROC_CTRL_VINITHI] = 8, 156 + [FP_CPU_PROC_CTRL_CFGTE] = 7, 157 + [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6, 158 + [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5, 159 + [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1, 160 + [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7, 161 + [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6, 162 + [FP_FDMA_CH_CFG_CH_INJ_PORT] = 5, 163 + [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 26, 164 + [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 24, 165 + [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 23, 166 + [FP_PTP_PHAD_CTRL_PHAD_ENA] = 7, 167 + [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 6, 168 + }; 169 + 170 + const unsigned int sparx5_fsize[FSIZE_LAST] = { 171 + [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 32, 172 + [FW_ANA_AC_SRC_CFG_PORT_MASK] = 32, 173 + [FW_ANA_AC_PGID_CFG_PORT_MASK] = 32, 174 + [FW_ANA_AC_TSN_SF_PORT_NUM] = 9, 175 + [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 10, 176 + [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 10, 177 + [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 10, 178 + [FW_ANA_AC_PORT_SGE_CFG_MASK] = 16, 179 + [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 13, 180 + [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 5, 181 + [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 13, 182 + [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 13, 183 + [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 4, 184 + [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 13, 185 + [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 32, 186 + [FW_ANA_L2_DLB_CFG_DLB_IDX] = 13, 187 + [FW_ANA_L2_TSN_CFG_TSN_SFID] = 10, 188 + [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 32, 189 + [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 4, 190 + [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 9, 191 + [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 7, 192 + [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 16, 193 + [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 7, 194 + [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 13, 195 + [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 16, 196 + [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 7, 197 + [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 16, 198 + [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 14, 199 + [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 11, 200 + [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 14, 201 + [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 5, 202 + [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 5, 203 + [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 5, 204 + [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 2, 205 + [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 7, 206 + [FW_QRES_RES_CFG_WM_HIGH] = 12, 207 + [FW_QRES_RES_STAT_MAXUSE] = 21, 208 + [FW_QRES_RES_STAT_CUR_INUSE] = 21, 209 + [FW_QSYS_PAUSE_CFG_PAUSE_START] = 12, 210 + [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 12, 211 + [FW_QSYS_ATOP_ATOP] = 12, 212 + [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 12, 213 + [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 7, 214 + [FW_XQS_STAT_CFG_STAT_VIEW] = 13, 215 + [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 15, 216 + [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 15, 217 + [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 15, 218 + [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 15, 219 + };
+244
drivers/net/ethernet/microchip/sparx5/sparx5_regs.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 + /* Microchip Sparx5 Switch driver 3 + * 4 + * Copyright (c) 2024 Microchip Technology Inc. 5 + */ 6 + 7 + /* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. 8 + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b 9 + */ 10 + 11 + #ifndef _SPARX5_REGS_H_ 12 + #define _SPARX5_REGS_H_ 13 + 14 + /* These enumerated values are used to index the platform specific structs 15 + * containing the addresses, counts, size and positions, of register groups, 16 + * registers and fields. 17 + */ 18 + 19 + enum sparx5_tsize_enum { 20 + TC_DEV10G, 21 + TC_DEV2G5, 22 + TC_DEV5G, 23 + TC_PCS10G_BR, 24 + TC_PCS5G_BR, 25 + TSIZE_LAST, 26 + }; 27 + 28 + enum sparx5_raddr_enum { 29 + RA_CPU_PROC_CTRL, 30 + RA_GCB_SOFT_RST, 31 + RA_GCB_HW_SGPIO_TO_SD_MAP_CFG, 32 + RADDR_LAST, 33 + }; 34 + 35 + enum sparx5_rcnt_enum { 36 + RC_ANA_AC_OWN_UPSID, 37 + RC_ANA_ACL_VCAP_S2_CFG, 38 + RC_ANA_ACL_OWN_UPSID, 39 + RC_ANA_CL_OWN_UPSID, 40 + RC_ANA_L2_OWN_UPSID, 41 + RC_ASM_PORT_CFG, 42 + RC_DSM_BUF_CFG, 43 + RC_DSM_DEV_TX_STOP_WM_CFG, 44 + RC_DSM_RX_PAUSE_CFG, 45 + RC_DSM_MAC_CFG, 46 + RC_DSM_MAC_ADDR_BASE_HIGH_CFG, 47 + RC_DSM_MAC_ADDR_BASE_LOW_CFG, 48 + RC_DSM_TAXI_CAL_CFG, 49 + RC_GCB_HW_SGPIO_TO_SD_MAP_CFG, 50 + RC_HSCH_PORT_MODE, 51 + RC_QFWD_SWITCH_PORT_MODE, 52 + RC_QSYS_PAUSE_CFG, 53 + RC_QSYS_ATOP, 54 + RC_QSYS_FWD_PRESSURE, 55 + RC_QSYS_CAL_AUTO, 56 + RC_REW_OWN_UPSID, 57 + RC_REW_RTAG_ETAG_CTRL, 58 + RCNT_LAST, 59 + }; 60 + 61 + enum sparx5_gaddr_enum { 62 + GA_ANA_AC_RAM_CTRL, 63 + GA_ANA_AC_PS_COMMON, 64 + GA_ANA_AC_MIRROR_PROBE, 65 + GA_ANA_AC_SRC, 66 + GA_ANA_AC_PGID, 67 + GA_ANA_AC_TSN_SF, 68 + GA_ANA_AC_TSN_SF_CFG, 69 + GA_ANA_AC_TSN_SF_STATUS, 70 + GA_ANA_AC_SG_ACCESS, 71 + GA_ANA_AC_SG_CONFIG, 72 + GA_ANA_AC_SG_STATUS, 73 + GA_ANA_AC_SG_STATUS_STICKY, 74 + GA_ANA_AC_STAT_GLOBAL_CFG_PORT, 75 + GA_ANA_AC_STAT_CNT_CFG_PORT, 76 + GA_ANA_AC_STAT_GLOBAL_CFG_ACL, 77 + GA_ANA_ACL_COMMON, 78 + GA_ANA_ACL_KEY_SEL, 79 + GA_ANA_ACL_CNT_B, 80 + GA_ANA_ACL_STICKY, 81 + GA_ANA_AC_POL_POL_ALL_CFG, 82 + GA_ANA_AC_POL_COMMON_BDLB, 83 + GA_ANA_AC_POL_COMMON_BUM_SLB, 84 + GA_ANA_AC_SDLB_LBGRP_TBL, 85 + GA_ANA_CL_PORT, 86 + GA_ANA_CL_COMMON, 87 + GA_ANA_L2_COMMON, 88 + GA_ANA_L3_COMMON, 89 + GA_ANA_L3_VLAN_ARP_L3MC_STICKY, 90 + GA_ASM_CFG, 91 + GA_ASM_PFC_TIMER_CFG, 92 + GA_ASM_LBK_WM_CFG, 93 + GA_ASM_LBK_MISC_CFG, 94 + GA_ASM_RAM_CTRL, 95 + GA_EACL_ES2_KEY_SELECT_PROFILE, 96 + GA_EACL_CNT_TBL, 97 + GA_EACL_POL_CFG, 98 + GA_EACL_ES2_STICKY, 99 + GA_EACL_RAM_CTRL, 100 + GA_GCB_SIO_CTRL, 101 + GA_HSCH_HSCH_DWRR, 102 + GA_HSCH_HSCH_MISC, 103 + GA_HSCH_HSCH_LEAK_LISTS, 104 + GA_HSCH_SYSTEM, 105 + GA_HSCH_MMGT, 106 + GA_HSCH_TAS_CONFIG, 107 + GA_PTP_PTP_CFG, 108 + GA_PTP_PTP_TOD_DOMAINS, 109 + GA_PTP_PHASE_DETECTOR_CTRL, 110 + GA_QSYS_CALCFG, 111 + GA_QSYS_RAM_CTRL, 112 + GA_REW_COMMON, 113 + GA_REW_PORT, 114 + GA_REW_VOE_PORT_LM_CNT, 115 + GA_REW_RAM_CTRL, 116 + GA_VOP_RAM_CTRL, 117 + GA_XQS_SYSTEM, 118 + GA_XQS_QLIMIT_SHR, 119 + GADDR_LAST, 120 + }; 121 + 122 + enum sparx5_gcnt_enum { 123 + GC_ANA_AC_SRC, 124 + GC_ANA_AC_PGID, 125 + GC_ANA_AC_TSN_SF_CFG, 126 + GC_ANA_AC_STAT_CNT_CFG_PORT, 127 + GC_ANA_ACL_KEY_SEL, 128 + GC_ANA_ACL_CNT_A, 129 + GC_ANA_ACL_CNT_B, 130 + GC_ANA_AC_SDLB_LBGRP_TBL, 131 + GC_ANA_AC_SDLB_LBSET_TBL, 132 + GC_ANA_CL_PORT, 133 + GC_ANA_L2_ISDX_LIMIT, 134 + GC_ANA_L2_ISDX, 135 + GC_ANA_L3_VLAN, 136 + GC_ASM_DEV_STATISTICS, 137 + GC_EACL_ES2_KEY_SELECT_PROFILE, 138 + GC_EACL_CNT_TBL, 139 + GC_GCB_SIO_CTRL, 140 + GC_HSCH_HSCH_CFG, 141 + GC_HSCH_HSCH_DWRR, 142 + GC_PTP_PTP_PINS, 143 + GC_PTP_PHASE_DETECTOR_CTRL, 144 + GC_REW_PORT, 145 + GC_REW_VOE_PORT_LM_CNT, 146 + GCNT_LAST, 147 + }; 148 + 149 + enum sparx5_gsize_enum { 150 + GW_ANA_AC_SRC, 151 + GW_ANA_L2_COMMON, 152 + GW_ASM_CFG, 153 + GW_CPU_CPU_REGS, 154 + GW_FDMA_FDMA, 155 + GW_GCB_CHIP_REGS, 156 + GW_HSCH_TAS_CONFIG, 157 + GW_PTP_PHASE_DETECTOR_CTRL, 158 + GW_QSYS_PAUSE_CFG, 159 + GSIZE_LAST, 160 + }; 161 + 162 + enum sparx5_fpos_enum { 163 + FP_CPU_PROC_CTRL_AARCH64_MODE_ENA, 164 + FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, 165 + FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, 166 + FP_CPU_PROC_CTRL_BE_EXCEP_MODE, 167 + FP_CPU_PROC_CTRL_VINITHI, 168 + FP_CPU_PROC_CTRL_CFGTE, 169 + FP_CPU_PROC_CTRL_CP15S_DISABLE, 170 + FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, 171 + FP_CPU_PROC_CTRL_L2_FLUSH_REQ, 172 + FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, 173 + FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, 174 + FP_FDMA_CH_CFG_CH_INJ_PORT, 175 + FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION, 176 + FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC, 177 + FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, 178 + FP_PTP_PHAD_CTRL_PHAD_ENA, 179 + FP_PTP_PHAD_CTRL_PHAD_FAILED, 180 + FPOS_LAST, 181 + }; 182 + 183 + enum sparx5_fsize_enum { 184 + FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK, 185 + FW_ANA_AC_SRC_CFG_PORT_MASK, 186 + FW_ANA_AC_PGID_CFG_PORT_MASK, 187 + FW_ANA_AC_TSN_SF_PORT_NUM, 188 + FW_ANA_AC_TSN_SF_CFG_TSN_SGID, 189 + FW_ANA_AC_TSN_SF_STATUS_TSN_SFID, 190 + FW_ANA_AC_SG_ACCESS_CTRL_SGID, 191 + FW_ANA_AC_PORT_SGE_CFG_MASK, 192 + FW_ANA_AC_SDLB_XLB_START_LBSET_START, 193 + FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, 194 + FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, 195 + FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, 196 + FW_ANA_AC_SDLB_XLB_NEXT_LBGRP, 197 + FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, 198 + FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA, 199 + FW_ANA_L2_DLB_CFG_DLB_IDX, 200 + FW_ANA_L2_TSN_CFG_TSN_SFID, 201 + FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK, 202 + FW_FDMA_CH_CFG_CH_DCB_DB_CNT, 203 + FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, 204 + FW_HSCH_SE_CFG_SE_DWRR_CNT, 205 + FW_HSCH_SE_CONNECT_SE_LEAK_LINK, 206 + FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT, 207 + FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX, 208 + FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST, 209 + FW_HSCH_FLUSH_CTRL_FLUSH_PORT, 210 + FW_HSCH_FLUSH_CTRL_FLUSH_HIER, 211 + FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, 212 + FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, 213 + FW_LRN_AUTOAGE_CFG_2_NEXT_ROW, 214 + FW_PTP_PTP_PIN_INTR_INTR_PTP, 215 + FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, 216 + FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, 217 + FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT, 218 + FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, 219 + FW_QRES_RES_CFG_WM_HIGH, 220 + FW_QRES_RES_STAT_MAXUSE, 221 + FW_QRES_RES_STAT_CUR_INUSE, 222 + FW_QSYS_PAUSE_CFG_PAUSE_START, 223 + FW_QSYS_PAUSE_CFG_PAUSE_STOP, 224 + FW_QSYS_ATOP_ATOP, 225 + FW_QSYS_ATOP_TOT_CFG_ATOP_TOT, 226 + FW_REW_RTAG_ETAG_CTRL_IPE_TBL, 227 + FW_XQS_STAT_CFG_STAT_VIEW, 228 + FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, 229 + FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, 230 + FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, 231 + FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, 232 + FSIZE_LAST, 233 + }; 234 + 235 + extern const unsigned int sparx5_tsize[TSIZE_LAST]; 236 + extern const unsigned int sparx5_raddr[RADDR_LAST]; 237 + extern const unsigned int sparx5_rcnt[RCNT_LAST]; 238 + extern const unsigned int sparx5_gaddr[GADDR_LAST]; 239 + extern const unsigned int sparx5_gcnt[GCNT_LAST]; 240 + extern const unsigned int sparx5_gsize[GSIZE_LAST]; 241 + extern const unsigned int sparx5_fpos[FPOS_LAST]; 242 + extern const unsigned int sparx5_fsize[FSIZE_LAST]; 243 + 244 + #endif /* _SPARX5_REGS_H_ */
+11 -4
drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c
··· 20 20 { 5000000ULL, 8192 / 8, 64 } /* 5 M */ 21 21 }; 22 22 23 + struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx) 24 + { 25 + return &sdlb_groups[idx]; 26 + } 27 + 23 28 int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) 24 29 { 25 30 u32 clk_per_100ps; ··· 183 178 184 179 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst) 185 180 { 181 + const struct sparx5_ops *ops = sparx5->data->ops; 186 182 const struct sparx5_sdlb_group *group; 187 183 u64 rate_bps; 188 184 int i, count; 189 185 190 186 rate_bps = rate * 1000; 191 187 192 - for (i = SPX5_SDLB_GROUP_CNT - 1; i >= 0; i--) { 193 - group = &sdlb_groups[i]; 188 + for (i = sparx5->data->consts->n_lb_groups - 1; i >= 0; i--) { 189 + group = ops->get_sdlb_group(i); 194 190 195 191 count = sparx5_sdlb_group_get_count(sparx5, i); 196 192 ··· 214 208 u32 itr, next; 215 209 int i; 216 210 217 - for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { 211 + for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { 218 212 if (sparx5_sdlb_group_is_empty(sparx5, i)) 219 213 continue; 220 214 ··· 309 303 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, 310 304 u32 frame_size, u32 idx) 311 305 { 306 + const struct sparx5_ops *ops = sparx5->data->ops; 312 307 u32 thres_shift, mask = 0x01, power = 0; 313 308 struct sparx5_sdlb_group *group; 314 309 u64 max_token; 315 310 316 - group = &sdlb_groups[idx]; 311 + group = ops->get_sdlb_group(idx); 317 312 318 313 /* Number of positions to right-shift LB's threshold value. */ 319 314 while ((min_burst & mask) == 0) {
+23 -10
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
··· 32 32 static void sparx5_port_update_mcast_ip_flood(struct sparx5_port *port, bool flood_flag) 33 33 { 34 34 bool should_flood = flood_flag || port->is_mrouter; 35 + struct sparx5 *sparx5 = port->sparx5; 35 36 int pgid; 36 37 37 - for (pgid = PGID_IPV4_MC_DATA; pgid <= PGID_IPV6_MC_CTRL; pgid++) 38 + for (pgid = sparx5_get_pgid(sparx5, PGID_IPV4_MC_DATA); 39 + pgid <= sparx5_get_pgid(sparx5, PGID_IPV6_MC_CTRL); pgid++) 38 40 sparx5_pgid_update_mask(port, pgid, should_flood); 39 41 } 40 42 41 43 static void sparx5_port_attr_bridge_flags(struct sparx5_port *port, 42 44 struct switchdev_brport_flags flags) 43 45 { 46 + struct sparx5 *sparx5 = port->sparx5; 47 + 44 48 if (flags.mask & BR_MCAST_FLOOD) { 45 - sparx5_pgid_update_mask(port, PGID_MC_FLOOD, !!(flags.val & BR_MCAST_FLOOD)); 49 + sparx5_pgid_update_mask(port, 50 + sparx5_get_pgid(sparx5, PGID_MC_FLOOD), 51 + !!(flags.val & BR_MCAST_FLOOD)); 46 52 sparx5_port_update_mcast_ip_flood(port, !!(flags.val & BR_MCAST_FLOOD)); 47 53 } 48 54 49 55 if (flags.mask & BR_FLOOD) 50 - sparx5_pgid_update_mask(port, PGID_UC_FLOOD, !!(flags.val & BR_FLOOD)); 56 + sparx5_pgid_update_mask(port, 57 + sparx5_get_pgid(sparx5, PGID_UC_FLOOD), 58 + !!(flags.val & BR_FLOOD)); 51 59 if (flags.mask & BR_BCAST_FLOOD) 52 - sparx5_pgid_update_mask(port, PGID_BCAST, !!(flags.val & BR_BCAST_FLOOD)); 60 + sparx5_pgid_update_mask(port, 61 + sparx5_get_pgid(sparx5, PGID_BCAST), 62 + !!(flags.val & BR_BCAST_FLOOD)); 53 63 } 54 64 55 65 static void sparx5_attr_stp_state_set(struct sparx5_port *port, ··· 229 219 port->vid = NULL_VID; 230 220 231 221 /* Forward frames to CPU */ 232 - sparx5_mact_learn(sparx5, PGID_CPU, port->ndev->dev_addr, 0); 222 + sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), 223 + port->ndev->dev_addr, 0); 233 224 234 225 /* Port enters in host more therefore restore mc list */ 235 226 __dev_mc_sync(port->ndev, sparx5_mc_sync, sparx5_mc_unsync); ··· 265 254 u16 vid = port->pvid; 266 255 267 256 if (up) 268 - sparx5_mact_learn(sparx5, PGID_CPU, port->ndev->dev_addr, vid); 257 + sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), 258 + port->ndev->dev_addr, vid); 269 259 else 270 260 sparx5_mact_forget(sparx5, port->ndev->dev_addr, vid); 271 261 ··· 342 330 switch (switchdev_work->event) { 343 331 case SWITCHDEV_FDB_ADD_TO_DEVICE: 344 332 if (host_addr) 345 - sparx5_add_mact_entry(sparx5, dev, PGID_CPU, 333 + sparx5_add_mact_entry(sparx5, dev, 334 + sparx5_get_pgid(sparx5, PGID_CPU), 346 335 fdb_info->addr, vid); 347 336 else 348 337 sparx5_add_mact_entry(sparx5, port->ndev, port->portno, ··· 431 418 switchdev_blocking_nb); 432 419 433 420 /* Flood broadcast to CPU */ 434 - sparx5_mact_learn(sparx5, PGID_BCAST, dev->broadcast, 435 - v->vid); 421 + sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_BCAST), 422 + dev->broadcast, v->vid); 436 423 return 0; 437 424 } 438 425 ··· 560 547 561 548 /* Add any mrouter ports to the new entry */ 562 549 if (is_new && ether_addr_is_ip_mcast(v->addr)) 563 - for (i = 0; i < SPX5_PORTS; i++) 550 + for (i = 0; i < spx5->data->consts->n_ports; i++) 564 551 if (spx5->ports[i] && spx5->ports[i]->is_mrouter) 565 552 sparx5_pgid_update_mask(spx5->ports[i], 566 553 entry->pgid_idx,
+4 -4
drivers/net/ethernet/microchip/sparx5/sparx5_tc.c
··· 60 60 cb, ndev, ndev, false); 61 61 } 62 62 63 - static void sparx5_tc_get_layer_and_idx(u32 parent, u32 portno, u32 *layer, 64 - u32 *idx) 63 + static void sparx5_tc_get_layer_and_idx(struct sparx5 *sparx5, u32 parent, 64 + u32 portno, u32 *layer, u32 *idx) 65 65 { 66 66 if (parent == TC_H_ROOT) { 67 67 *layer = 2; ··· 90 90 struct sparx5_port *port = netdev_priv(ndev); 91 91 u32 layer, se_idx; 92 92 93 - sparx5_tc_get_layer_and_idx(qopt->parent, port->portno, &layer, 94 - &se_idx); 93 + sparx5_tc_get_layer_and_idx(port->sparx5, qopt->parent, port->portno, 94 + &layer, &se_idx); 95 95 96 96 switch (qopt->command) { 97 97 case TC_TBF_REPLACE:
+3 -1
drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c
··· 785 785 * allocate a stream gate that is always open. 786 786 */ 787 787 if (sg_idx < 0) { 788 - sg_idx = sparx5_pool_idx_to_id(SPX5_PSFP_SG_OPEN); 788 + /* Always-open stream gate is always the last */ 789 + sg_idx = sparx5_pool_idx_to_id(sparx5->data->consts->n_gates - 790 + 1); 789 791 sg->ipv = 0; /* Disabled */ 790 792 sg->cycletime = SPX5_PSFP_SG_CYCLE_TIME_DEFAULT; 791 793 sg->num_entries = 1;
+31 -16
drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
··· 16 16 17 17 /* Output mask to respective registers */ 18 18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); 19 - spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); 20 - spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); 19 + if (is_sparx5(sparx5)) { 20 + spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); 21 + spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); 22 + } 21 23 22 24 return 0; 23 25 } ··· 143 141 void sparx5_pgid_clear(struct sparx5 *spx5, int pgid) 144 142 { 145 143 spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); 146 - spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); 147 - spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); 144 + if (is_sparx5(spx5)) { 145 + spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); 146 + spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); 147 + } 148 148 } 149 149 150 150 void sparx5_pgid_read_mask(struct sparx5 *spx5, int pgid, u32 portmask[3]) 151 151 { 152 152 portmask[0] = spx5_rd(spx5, ANA_AC_PGID_CFG(pgid)); 153 - portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); 154 - portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); 153 + if (is_sparx5(spx5)) { 154 + portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); 155 + portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); 156 + } 155 157 } 156 158 157 159 void sparx5_update_fwd(struct sparx5 *sparx5) ··· 168 162 bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS); 169 163 170 164 /* Update flood masks */ 171 - for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) { 165 + for (port = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); 166 + port <= sparx5_get_pgid(sparx5, PGID_BCAST); port++) { 172 167 spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); 173 - spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); 174 - spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); 168 + if (is_sparx5(sparx5)) { 169 + spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); 170 + spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); 171 + } 175 172 } 176 173 177 174 /* Update SRC masks */ 178 - for (port = 0; port < SPX5_PORTS; port++) { 175 + for (port = 0; port < sparx5->data->consts->n_ports; port++) { 179 176 if (test_bit(port, sparx5->bridge_fwd_mask)) { 180 177 /* Allow to send to all bridged but self */ 181 178 bitmap_copy(workmask, sparx5->bridge_fwd_mask, SPX5_PORTS); 182 179 clear_bit(port, workmask); 183 180 bitmap_to_arr32(mask, workmask, SPX5_PORTS); 184 181 spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); 185 - spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); 186 - spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); 182 + if (is_sparx5(sparx5)) { 183 + spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); 184 + spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); 185 + } 187 186 } else { 188 187 spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); 189 - spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); 190 - spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); 188 + if (is_sparx5(sparx5)) { 189 + spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); 190 + spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); 191 + } 191 192 } 192 193 } 193 194 ··· 205 192 206 193 /* Apply learning mask */ 207 194 spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG); 208 - spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); 209 - spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2); 195 + if (is_sparx5(sparx5)) { 196 + spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); 197 + spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2); 198 + } 210 199 } 211 200 212 201 void sparx5_vlan_port_apply(struct sparx5 *sparx5,