drm/amdgpu: add the GC 10.3 VRS registers

+2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h

··· 2727 2727 #define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 2728 2728 #define mmDB_RESERVED_REG_1_DEFAULT 0x00000000 2729 2729 #define mmDB_RESERVED_REG_3_DEFAULT 0x00000000 2730 + #define mmDB_VRS_OVERRIDE_CNTL_DEFAULT 0x00000000 2730 2731 #define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000 2731 2732 #define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000 2732 2733 #define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000 ··· 3063 3062 #define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000 3064 3063 #define mmPA_STEREO_CNTL_DEFAULT 0x00000000 3065 3064 #define mmPA_STATE_STEREO_X_DEFAULT 0x00000000 3065 + #define mmPA_CL_VRS_CNTL_DEFAULT 0x00000000 3066 3066 #define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000 3067 3067 #define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000 3068 3068 #define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000

+4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

··· 5379 5379 #define mmDB_RESERVED_REG_1_BASE_IDX 1 5380 5380 #define mmDB_RESERVED_REG_3 0x0017 5381 5381 #define mmDB_RESERVED_REG_3_BASE_IDX 1 5382 + #define mmDB_VRS_OVERRIDE_CNTL 0x0019 5383 + #define mmDB_VRS_OVERRIDE_CNTL_BASE_IDX 1 5382 5384 #define mmDB_Z_READ_BASE_HI 0x001a 5383 5385 #define mmDB_Z_READ_BASE_HI_BASE_IDX 1 5384 5386 #define mmDB_STENCIL_READ_BASE_HI 0x001b ··· 6051 6049 #define mmPA_STEREO_CNTL_BASE_IDX 1 6052 6050 #define mmPA_STATE_STEREO_X 0x0211 6053 6051 #define mmPA_STATE_STEREO_X_BASE_IDX 1 6052 + #define mmPA_CL_VRS_CNTL 0x0212 6053 + #define mmPA_CL_VRS_CNTL_BASE_IDX 1 6054 6054 #define mmPA_SU_POINT_SIZE 0x0280 6055 6055 #define mmPA_SU_POINT_SIZE_BASE_IDX 1 6056 6056 #define mmPA_SU_POINT_MINMAX 0x0281

+50

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

··· 9777 9777 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3 9778 9778 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 9779 9779 #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 9780 + #define DB_EXCEPTION_CONTROL__FORCE_VRS_RATE_FINE__SHIFT 0x10 9780 9781 #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18 9781 9782 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L 9782 9783 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L ··· 9785 9784 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L 9786 9785 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L 9787 9786 #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L 9787 + #define DB_EXCEPTION_CONTROL__FORCE_VRS_RATE_FINE_MASK 0x00FF0000L 9788 9788 #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L 9789 9789 //DB_DFSM_CONFIG 9790 9790 #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 ··· 10078 10076 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 10079 10077 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 10080 10078 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a 10079 + #define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT__SHIFT 0x1c 10081 10080 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x1e 10082 10081 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT 0x1f 10083 10082 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L ··· 10106 10103 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L 10107 10104 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L 10108 10105 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L 10106 + #define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT_MASK 0x10000000L 10109 10107 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK 0x40000000L 10110 10108 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK 0x80000000L 10111 10109 //CB_HW_CONTROL 10112 10110 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0 10111 + #define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT 0x1 10113 10112 #define CB_HW_CONTROL__DISABLE_FILLRATE_OPT_FIX_WITH_CFC__SHIFT 0x3 10114 10113 #define CB_HW_CONTROL__DISABLE_POST_DCC_WITH_CFC_FIX__SHIFT 0x4 10114 + #define CB_HW_CONTROL__DISABLE_COMPRESS_1FRAG_WHEN_VRS_RATE_HINT_EN__SHIFT 0x5 10115 10115 #define CB_HW_CONTROL__RMI_CREDITS__SHIFT 0x6 10116 10116 #define CB_HW_CONTROL__CHICKEN_BITS__SHIFT 0xc 10117 10117 #define CB_HW_CONTROL__DISABLE_FMASK_MULTI_MGCG_DOMAINS__SHIFT 0xf ··· 10135 10129 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e 10136 10130 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f 10137 10131 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L 10132 + #define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK 0x00000002L 10138 10133 #define CB_HW_CONTROL__DISABLE_FILLRATE_OPT_FIX_WITH_CFC_MASK 0x00000008L 10139 10134 #define CB_HW_CONTROL__DISABLE_POST_DCC_WITH_CFC_FIX_MASK 0x00000010L 10135 + #define CB_HW_CONTROL__DISABLE_COMPRESS_1FRAG_WHEN_VRS_RATE_HINT_EN_MASK 0x00000020L 10140 10136 #define CB_HW_CONTROL__RMI_CREDITS_MASK 0x00000FC0L 10141 10137 #define CB_HW_CONTROL__CHICKEN_BITS_MASK 0x00007000L 10142 10138 #define CB_HW_CONTROL__DISABLE_FMASK_MULTI_MGCG_DOMAINS_MASK 0x00008000L ··· 19889 19881 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 19890 19882 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 19891 19883 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 19884 + #define DB_RENDER_OVERRIDE2__FORCE_VRS_RATE_FINE__SHIFT 0x1a 19892 19885 #define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT 0x1b 19893 19886 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L 19894 19887 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL ··· 19907 19898 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L 19908 19899 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L 19909 19900 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L 19901 + #define DB_RENDER_OVERRIDE2__FORCE_VRS_RATE_FINE_MASK 0x04000000L 19910 19902 #define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK 0x18000000L 19911 19903 //DB_HTILE_DATA_BASE 19912 19904 #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 ··· 20031 20021 //DB_RESERVED_REG_3 20032 20022 #define DB_RESERVED_REG_3__FIELD_1__SHIFT 0x0 20033 20023 #define DB_RESERVED_REG_3__FIELD_1_MASK 0x003FFFFFL 20024 + //DB_VRS_OVERRIDE_CNTL 20025 + #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT 0x0 20026 + #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_X__SHIFT 0x4 20027 + #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_Y__SHIFT 0x6 20028 + #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK 0x00000007L 20029 + #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_X_MASK 0x00000030L 20030 + #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_Y_MASK 0x000000C0L 20034 20031 //DB_Z_READ_BASE_HI 20035 20032 #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 20036 20033 #define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL ··· 22615 22598 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 22616 22599 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 22617 22600 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b 22601 + #define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT 0x1c 22618 22602 #define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT 0x1d 22619 22603 #define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT 0x1e 22620 22604 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L ··· 22645 22627 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L 22646 22628 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L 22647 22629 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L 22630 + #define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK 0x10000000L 22648 22631 #define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK 0x20000000L 22649 22632 #define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK 0x40000000L 22650 22633 //PA_CL_NANINF_CNTL ··· 22759 22740 //PA_STATE_STEREO_X 22760 22741 #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 22761 22742 #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL 22743 + //PA_CL_VRS_CNTL 22744 + #define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT 0x0 22745 + #define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT 0x3 22746 + #define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT 0x6 22747 + #define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT 0x9 22748 + #define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT 0xd 22749 + #define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT 0xe 22750 + #define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK 0x00000007L 22751 + #define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK 0x00000038L 22752 + #define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK 0x000001C0L 22753 + #define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK 0x00000E00L 22754 + #define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK 0x00002000L 22755 + #define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK 0x00004000L 22762 22756 //PA_SU_POINT_SIZE 22763 22757 #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 22764 22758 #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 ··· 23120 23088 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 23121 23089 #define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 23122 23090 #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 23091 + #define DB_HTILE_SURFACE__VRS_HTILE_ENCODING__SHIFT 0x13 23123 23092 #define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L 23124 23093 #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L 23125 23094 #define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L ··· 23130 23097 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L 23131 23098 #define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L 23132 23099 #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L 23100 + #define DB_HTILE_SURFACE__VRS_HTILE_ENCODING_MASK 0x00180000L 23133 23101 //DB_SRESULTS_COMPARE_STATE0 23134 23102 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 23135 23103 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 ··· 24988 24954 #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 24989 24955 #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 24990 24956 #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 24957 + #define CB_COLOR0_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 24991 24958 #define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 24992 24959 #define CB_COLOR0_ATTRIB3__META_LINEAR_MASK 0x00002000L 24993 24960 #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 24997 24962 #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 24998 24963 #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 24999 24964 #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 24965 + #define CB_COLOR0_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25000 24966 //CB_COLOR1_ATTRIB3 25001 24967 #define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25002 24968 #define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25007 24971 #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25008 24972 #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25009 24973 #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 24974 + #define CB_COLOR1_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25010 24975 #define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25011 24976 #define CB_COLOR1_ATTRIB3__META_LINEAR_MASK 0x00002000L 25012 24977 #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25016 24979 #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25017 24980 #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25018 24981 #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 24982 + #define CB_COLOR1_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25019 24983 //CB_COLOR2_ATTRIB3 25020 24984 #define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25021 24985 #define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25026 24988 #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25027 24989 #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25028 24990 #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 24991 + #define CB_COLOR2_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25029 24992 #define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25030 24993 #define CB_COLOR2_ATTRIB3__META_LINEAR_MASK 0x00002000L 25031 24994 #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25035 24996 #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25036 24997 #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25037 24998 #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 24999 + #define CB_COLOR2_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25038 25000 //CB_COLOR3_ATTRIB3 25039 25001 #define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25040 25002 #define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25045 25005 #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25046 25006 #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25047 25007 #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 25008 + #define CB_COLOR3_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25048 25009 #define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25049 25010 #define CB_COLOR3_ATTRIB3__META_LINEAR_MASK 0x00002000L 25050 25011 #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25054 25013 #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25055 25014 #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25056 25015 #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 25016 + #define CB_COLOR3_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25057 25017 //CB_COLOR4_ATTRIB3 25058 25018 #define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25059 25019 #define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25064 25022 #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25065 25023 #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25066 25024 #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 25025 + #define CB_COLOR4_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25067 25026 #define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25068 25027 #define CB_COLOR4_ATTRIB3__META_LINEAR_MASK 0x00002000L 25069 25028 #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25073 25030 #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25074 25031 #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25075 25032 #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 25033 + #define CB_COLOR4_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25076 25034 //CB_COLOR5_ATTRIB3 25077 25035 #define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25078 25036 #define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25083 25039 #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25084 25040 #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25085 25041 #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 25042 + #define CB_COLOR5_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25086 25043 #define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25087 25044 #define CB_COLOR5_ATTRIB3__META_LINEAR_MASK 0x00002000L 25088 25045 #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25092 25047 #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25093 25048 #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25094 25049 #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 25050 + #define CB_COLOR5_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25095 25051 //CB_COLOR6_ATTRIB3 25096 25052 #define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25097 25053 #define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25102 25056 #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25103 25057 #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25104 25058 #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 25059 + #define CB_COLOR6_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25105 25060 #define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25106 25061 #define CB_COLOR6_ATTRIB3__META_LINEAR_MASK 0x00002000L 25107 25062 #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25111 25064 #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25112 25065 #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25113 25066 #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 25067 + #define CB_COLOR6_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25114 25068 //CB_COLOR7_ATTRIB3 25115 25069 #define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 25116 25070 #define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT 0xd ··· 25121 25073 #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a 25122 25074 #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b 25123 25075 #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e 25076 + #define CB_COLOR7_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f 25124 25077 #define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL 25125 25078 #define CB_COLOR7_ATTRIB3__META_LINEAR_MASK 0x00002000L 25126 25079 #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L ··· 25130 25081 #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L 25131 25082 #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L 25132 25083 #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L 25084 + #define CB_COLOR7_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L 25133 25085 25134 25086 25135 25087 // addressBlock: gc_gfxudec