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kernel os linux

NVMe: Add nvme-scsi.c

Translates SCSI commands in SG_IO ioctl to NVMe commands.
Uses the scsi-nvme translation spec from nvmexpress.org as reference.

Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>

authored by

Vishal Verma and committed by
Matthew Wilcox
5d0f6131 f8ebf840

+2997 -18
+1 -1
drivers/block/Makefile
··· 42 42 43 43 obj-$(CONFIG_BLK_DEV_RSXX) += rsxx/ 44 44 45 - nvme-y := nvme-core.o 45 + nvme-y := nvme-core.o nvme-scsi.o 46 46 swim_mod-y := swim.o swim_asm.o
+20 -17
drivers/block/nvme-core.c
··· 39 39 #include <linux/sched.h> 40 40 #include <linux/slab.h> 41 41 #include <linux/types.h> 42 - 42 + #include <scsi/sg.h> 43 43 #include <asm-generic/io-64-nonatomic-lo-hi.h> 44 44 45 45 #define NVME_Q_DEPTH 1024 ··· 224 224 return ctx; 225 225 } 226 226 227 - static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) 227 + struct nvme_queue *get_nvmeq(struct nvme_dev *dev) 228 228 { 229 229 return dev->queues[get_cpu() + 1]; 230 230 } 231 231 232 - static void put_nvmeq(struct nvme_queue *nvmeq) 232 + void put_nvmeq(struct nvme_queue *nvmeq) 233 233 { 234 234 put_cpu(); 235 235 } ··· 290 290 return iod; 291 291 } 292 292 293 - static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) 293 + void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) 294 294 { 295 295 const int last_prp = PAGE_SIZE / 8 - 1; 296 296 int i; ··· 339 339 } 340 340 341 341 /* length is in bytes. gfp flags indicates whether we may sleep. */ 342 - static int nvme_setup_prps(struct nvme_dev *dev, 343 - struct nvme_common_command *cmd, struct nvme_iod *iod, 344 - int total_len, gfp_t gfp) 342 + int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, 343 + struct nvme_iod *iod, int total_len, gfp_t gfp) 345 344 { 346 345 struct dma_pool *pool; 347 346 int length = total_len; ··· 511 512 return 0; 512 513 } 513 514 514 - static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) 515 + int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) 515 516 { 516 517 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, 517 518 special_completion, NVME_IO_TIMEOUT); ··· 714 715 * Returns 0 on success. If the result is negative, it's a Linux error code; 715 716 * if the result is positive, it's an NVM Express status code 716 717 */ 717 - static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, 718 - struct nvme_command *cmd, u32 *result, unsigned timeout) 718 + int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 719 + u32 *result, unsigned timeout) 719 720 { 720 721 int cmdid; 721 722 struct sync_cmd_info cmdinfo; ··· 744 745 return cmdinfo.status; 745 746 } 746 747 747 - static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, 748 + int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, 748 749 u32 *result) 749 750 { 750 751 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); ··· 817 818 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 818 819 } 819 820 820 - static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, 821 + int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, 821 822 dma_addr_t dma_addr) 822 823 { 823 824 struct nvme_command c; ··· 831 832 return nvme_submit_admin_cmd(dev, &c, NULL); 832 833 } 833 834 834 - static int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, 835 + int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, 835 836 dma_addr_t dma_addr, u32 *result) 836 837 { 837 838 struct nvme_command c; ··· 845 846 return nvme_submit_admin_cmd(dev, &c, result); 846 847 } 847 848 848 - static int nvme_set_features(struct nvme_dev *dev, unsigned fid, 849 - unsigned dword11, dma_addr_t dma_addr, u32 *result) 849 + int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, 850 + dma_addr_t dma_addr, u32 *result) 850 851 { 851 852 struct nvme_command c; 852 853 ··· 1064 1065 return result; 1065 1066 } 1066 1067 1067 - static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, 1068 + struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, 1068 1069 unsigned long addr, unsigned length) 1069 1070 { 1070 1071 int i, err, count, nents, offset; ··· 1120 1121 return ERR_PTR(err); 1121 1122 } 1122 1123 1123 - static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, 1124 + void nvme_unmap_user_pages(struct nvme_dev *dev, int write, 1124 1125 struct nvme_iod *iod) 1125 1126 { 1126 1127 int i; ··· 1256 1257 return nvme_user_admin_cmd(ns->dev, (void __user *)arg); 1257 1258 case NVME_IOCTL_SUBMIT_IO: 1258 1259 return nvme_submit_io(ns, (void __user *)arg); 1260 + case SG_GET_VERSION_NUM: 1261 + return nvme_sg_get_version_num((void __user *)arg); 1262 + case SG_IO: 1263 + return nvme_sg_io(ns, (void __user *)arg); 1259 1264 default: 1260 1265 return -ENOTTY; 1261 1266 }
+2941
drivers/block/nvme-scsi.c
··· 1 + /* 2 + * NVM Express device driver 3 + * Copyright (c) 2011, Intel Corporation. 4 + * 5 + * This program is free software; you can redistribute it and/or modify it 6 + * under the terms and conditions of the GNU General Public License, 7 + * version 2, as published by the Free Software Foundation. 8 + * 9 + * This program is distributed in the hope it will be useful, but WITHOUT 10 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 + * more details. 13 + * 14 + * You should have received a copy of the GNU General Public License along with 15 + * this program; if not, write to the Free Software Foundation, Inc., 16 + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 + */ 18 + 19 + /* 20 + * Refer to the SCSI-NVMe Translation spec for details on how 21 + * each command is translated. 22 + */ 23 + 24 + #include <linux/nvme.h> 25 + #include <linux/bio.h> 26 + #include <linux/bitops.h> 27 + #include <linux/blkdev.h> 28 + #include <linux/delay.h> 29 + #include <linux/errno.h> 30 + #include <linux/fs.h> 31 + #include <linux/genhd.h> 32 + #include <linux/idr.h> 33 + #include <linux/init.h> 34 + #include <linux/interrupt.h> 35 + #include <linux/io.h> 36 + #include <linux/kdev_t.h> 37 + #include <linux/kthread.h> 38 + #include <linux/kernel.h> 39 + #include <linux/mm.h> 40 + #include <linux/module.h> 41 + #include <linux/moduleparam.h> 42 + #include <linux/pci.h> 43 + #include <linux/poison.h> 44 + #include <linux/sched.h> 45 + #include <linux/slab.h> 46 + #include <linux/types.h> 47 + #include <linux/version.h> 48 + #include <scsi/sg.h> 49 + #include <scsi/scsi.h> 50 + 51 + 52 + static int sg_version_num = 30534; /* 2 digits for each component */ 53 + 54 + #define SNTI_TRANSLATION_SUCCESS 0 55 + #define SNTI_INTERNAL_ERROR 1 56 + 57 + /* VPD Page Codes */ 58 + #define VPD_SUPPORTED_PAGES 0x00 59 + #define VPD_SERIAL_NUMBER 0x80 60 + #define VPD_DEVICE_IDENTIFIERS 0x83 61 + #define VPD_EXTENDED_INQUIRY 0x86 62 + #define VPD_BLOCK_DEV_CHARACTERISTICS 0xB1 63 + 64 + /* CDB offsets */ 65 + #define REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET 6 66 + #define REPORT_LUNS_SR_OFFSET 2 67 + #define READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET 10 68 + #define REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET 4 69 + #define REQUEST_SENSE_DESC_OFFSET 1 70 + #define REQUEST_SENSE_DESC_MASK 0x01 71 + #define DESCRIPTOR_FORMAT_SENSE_DATA_TYPE 1 72 + #define INQUIRY_EVPD_BYTE_OFFSET 1 73 + #define INQUIRY_PAGE_CODE_BYTE_OFFSET 2 74 + #define INQUIRY_EVPD_BIT_MASK 1 75 + #define INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET 3 76 + #define START_STOP_UNIT_CDB_IMMED_OFFSET 1 77 + #define START_STOP_UNIT_CDB_IMMED_MASK 0x1 78 + #define START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET 3 79 + #define START_STOP_UNIT_CDB_POWER_COND_MOD_MASK 0xF 80 + #define START_STOP_UNIT_CDB_POWER_COND_OFFSET 4 81 + #define START_STOP_UNIT_CDB_POWER_COND_MASK 0xF0 82 + #define START_STOP_UNIT_CDB_NO_FLUSH_OFFSET 4 83 + #define START_STOP_UNIT_CDB_NO_FLUSH_MASK 0x4 84 + #define START_STOP_UNIT_CDB_START_OFFSET 4 85 + #define START_STOP_UNIT_CDB_START_MASK 0x1 86 + #define WRITE_BUFFER_CDB_MODE_OFFSET 1 87 + #define WRITE_BUFFER_CDB_MODE_MASK 0x1F 88 + #define WRITE_BUFFER_CDB_BUFFER_ID_OFFSET 2 89 + #define WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET 3 90 + #define WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET 6 91 + #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET 1 92 + #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK 0xC0 93 + #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT 6 94 + #define FORMAT_UNIT_CDB_LONG_LIST_OFFSET 1 95 + #define FORMAT_UNIT_CDB_LONG_LIST_MASK 0x20 96 + #define FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET 1 97 + #define FORMAT_UNIT_CDB_FORMAT_DATA_MASK 0x10 98 + #define FORMAT_UNIT_SHORT_PARM_LIST_LEN 4 99 + #define FORMAT_UNIT_LONG_PARM_LIST_LEN 8 100 + #define FORMAT_UNIT_PROT_INT_OFFSET 3 101 + #define FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET 0 102 + #define FORMAT_UNIT_PROT_FIELD_USAGE_MASK 0x07 103 + 104 + /* Misc. defines */ 105 + #define NIBBLE_SHIFT 4 106 + #define FIXED_SENSE_DATA 0x70 107 + #define DESC_FORMAT_SENSE_DATA 0x72 108 + #define FIXED_SENSE_DATA_ADD_LENGTH 10 109 + #define LUN_ENTRY_SIZE 8 110 + #define LUN_DATA_HEADER_SIZE 8 111 + #define ALL_LUNS_RETURNED 0x02 112 + #define ALL_WELL_KNOWN_LUNS_RETURNED 0x01 113 + #define RESTRICTED_LUNS_RETURNED 0x00 114 + #define NVME_POWER_STATE_START_VALID 0x00 115 + #define NVME_POWER_STATE_ACTIVE 0x01 116 + #define NVME_POWER_STATE_IDLE 0x02 117 + #define NVME_POWER_STATE_STANDBY 0x03 118 + #define NVME_POWER_STATE_LU_CONTROL 0x07 119 + #define POWER_STATE_0 0 120 + #define POWER_STATE_1 1 121 + #define POWER_STATE_2 2 122 + #define POWER_STATE_3 3 123 + #define DOWNLOAD_SAVE_ACTIVATE 0x05 124 + #define DOWNLOAD_SAVE_DEFER_ACTIVATE 0x0E 125 + #define ACTIVATE_DEFERRED_MICROCODE 0x0F 126 + #define FORMAT_UNIT_IMMED_MASK 0x2 127 + #define FORMAT_UNIT_IMMED_OFFSET 1 128 + #define KELVIN_TEMP_FACTOR 273 129 + #define FIXED_FMT_SENSE_DATA_SIZE 18 130 + #define DESC_FMT_SENSE_DATA_SIZE 8 131 + 132 + /* SCSI/NVMe defines and bit masks */ 133 + #define INQ_STANDARD_INQUIRY_PAGE 0x00 134 + #define INQ_SUPPORTED_VPD_PAGES_PAGE 0x00 135 + #define INQ_UNIT_SERIAL_NUMBER_PAGE 0x80 136 + #define INQ_DEVICE_IDENTIFICATION_PAGE 0x83 137 + #define INQ_EXTENDED_INQUIRY_DATA_PAGE 0x86 138 + #define INQ_BDEV_CHARACTERISTICS_PAGE 0xB1 139 + #define INQ_SERIAL_NUMBER_LENGTH 0x14 140 + #define INQ_NUM_SUPPORTED_VPD_PAGES 5 141 + #define VERSION_SPC_4 0x06 142 + #define ACA_UNSUPPORTED 0 143 + #define STANDARD_INQUIRY_LENGTH 36 144 + #define ADDITIONAL_STD_INQ_LENGTH 31 145 + #define EXTENDED_INQUIRY_DATA_PAGE_LENGTH 0x3C 146 + #define RESERVED_FIELD 0 147 + 148 + /* SCSI READ/WRITE Defines */ 149 + #define IO_CDB_WP_MASK 0xE0 150 + #define IO_CDB_WP_SHIFT 5 151 + #define IO_CDB_FUA_MASK 0x8 152 + #define IO_6_CDB_LBA_OFFSET 0 153 + #define IO_6_CDB_LBA_MASK 0x001FFFFF 154 + #define IO_6_CDB_TX_LEN_OFFSET 4 155 + #define IO_6_DEFAULT_TX_LEN 256 156 + #define IO_10_CDB_LBA_OFFSET 2 157 + #define IO_10_CDB_TX_LEN_OFFSET 7 158 + #define IO_10_CDB_WP_OFFSET 1 159 + #define IO_10_CDB_FUA_OFFSET 1 160 + #define IO_12_CDB_LBA_OFFSET 2 161 + #define IO_12_CDB_TX_LEN_OFFSET 6 162 + #define IO_12_CDB_WP_OFFSET 1 163 + #define IO_12_CDB_FUA_OFFSET 1 164 + #define IO_16_CDB_FUA_OFFSET 1 165 + #define IO_16_CDB_WP_OFFSET 1 166 + #define IO_16_CDB_LBA_OFFSET 2 167 + #define IO_16_CDB_TX_LEN_OFFSET 10 168 + 169 + /* Mode Sense/Select defines */ 170 + #define MODE_PAGE_INFO_EXCEP 0x1C 171 + #define MODE_PAGE_CACHING 0x08 172 + #define MODE_PAGE_CONTROL 0x0A 173 + #define MODE_PAGE_POWER_CONDITION 0x1A 174 + #define MODE_PAGE_RETURN_ALL 0x3F 175 + #define MODE_PAGE_BLK_DES_LEN 0x08 176 + #define MODE_PAGE_LLBAA_BLK_DES_LEN 0x10 177 + #define MODE_PAGE_CACHING_LEN 0x14 178 + #define MODE_PAGE_CONTROL_LEN 0x0C 179 + #define MODE_PAGE_POW_CND_LEN 0x28 180 + #define MODE_PAGE_INF_EXC_LEN 0x0C 181 + #define MODE_PAGE_ALL_LEN 0x54 182 + #define MODE_SENSE6_MPH_SIZE 4 183 + #define MODE_SENSE6_ALLOC_LEN_OFFSET 4 184 + #define MODE_SENSE_PAGE_CONTROL_OFFSET 2 185 + #define MODE_SENSE_PAGE_CONTROL_MASK 0xC0 186 + #define MODE_SENSE_PAGE_CODE_OFFSET 2 187 + #define MODE_SENSE_PAGE_CODE_MASK 0x3F 188 + #define MODE_SENSE_LLBAA_OFFSET 1 189 + #define MODE_SENSE_LLBAA_MASK 0x10 190 + #define MODE_SENSE_LLBAA_SHIFT 4 191 + #define MODE_SENSE_DBD_OFFSET 1 192 + #define MODE_SENSE_DBD_MASK 8 193 + #define MODE_SENSE_DBD_SHIFT 3 194 + #define MODE_SENSE10_MPH_SIZE 8 195 + #define MODE_SENSE10_ALLOC_LEN_OFFSET 7 196 + #define MODE_SELECT_CDB_PAGE_FORMAT_OFFSET 1 197 + #define MODE_SELECT_CDB_SAVE_PAGES_OFFSET 1 198 + #define MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET 4 199 + #define MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET 7 200 + #define MODE_SELECT_CDB_PAGE_FORMAT_MASK 0x10 201 + #define MODE_SELECT_CDB_SAVE_PAGES_MASK 0x1 202 + #define MODE_SELECT_6_BD_OFFSET 3 203 + #define MODE_SELECT_10_BD_OFFSET 6 204 + #define MODE_SELECT_10_LLBAA_OFFSET 4 205 + #define MODE_SELECT_10_LLBAA_MASK 1 206 + #define MODE_SELECT_6_MPH_SIZE 4 207 + #define MODE_SELECT_10_MPH_SIZE 8 208 + #define CACHING_MODE_PAGE_WCE_MASK 0x04 209 + #define MODE_SENSE_BLK_DESC_ENABLED 0 210 + #define MODE_SENSE_BLK_DESC_COUNT 1 211 + #define MODE_SELECT_PAGE_CODE_MASK 0x3F 212 + #define SHORT_DESC_BLOCK 8 213 + #define LONG_DESC_BLOCK 16 214 + #define MODE_PAGE_POW_CND_LEN_FIELD 0x26 215 + #define MODE_PAGE_INF_EXC_LEN_FIELD 0x0A 216 + #define MODE_PAGE_CACHING_LEN_FIELD 0x12 217 + #define MODE_PAGE_CONTROL_LEN_FIELD 0x0A 218 + #define MODE_SENSE_PC_CURRENT_VALUES 0 219 + 220 + /* Log Sense defines */ 221 + #define LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE 0x00 222 + #define LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH 0x07 223 + #define LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE 0x2F 224 + #define LOG_PAGE_TEMPERATURE_PAGE 0x0D 225 + #define LOG_SENSE_CDB_SP_OFFSET 1 226 + #define LOG_SENSE_CDB_SP_NOT_ENABLED 0 227 + #define LOG_SENSE_CDB_PC_OFFSET 2 228 + #define LOG_SENSE_CDB_PC_MASK 0xC0 229 + #define LOG_SENSE_CDB_PC_SHIFT 6 230 + #define LOG_SENSE_CDB_PC_CUMULATIVE_VALUES 1 231 + #define LOG_SENSE_CDB_PAGE_CODE_MASK 0x3F 232 + #define LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET 7 233 + #define REMAINING_INFO_EXCP_PAGE_LENGTH 0x8 234 + #define LOG_INFO_EXCP_PAGE_LENGTH 0xC 235 + #define REMAINING_TEMP_PAGE_LENGTH 0xC 236 + #define LOG_TEMP_PAGE_LENGTH 0x10 237 + #define LOG_TEMP_UNKNOWN 0xFF 238 + #define SUPPORTED_LOG_PAGES_PAGE_LENGTH 0x3 239 + 240 + /* Read Capacity defines */ 241 + #define READ_CAP_10_RESP_SIZE 8 242 + #define READ_CAP_16_RESP_SIZE 32 243 + 244 + /* NVMe Namespace and Command Defines */ 245 + #define NVME_GET_SMART_LOG_PAGE 0x02 246 + #define NVME_GET_FEAT_TEMP_THRESH 0x04 247 + #define BYTES_TO_DWORDS 4 248 + #define NVME_MAX_FIRMWARE_SLOT 7 249 + 250 + /* Report LUNs defines */ 251 + #define REPORT_LUNS_FIRST_LUN_OFFSET 8 252 + 253 + /* SCSI ADDITIONAL SENSE Codes */ 254 + 255 + #define SCSI_ASC_NO_SENSE 0x00 256 + #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03 257 + #define SCSI_ASC_LUN_NOT_READY 0x04 258 + #define SCSI_ASC_WARNING 0x0B 259 + #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10 260 + #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10 261 + #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10 262 + #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 263 + #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D 264 + #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20 265 + #define SCSI_ASC_ILLEGAL_COMMAND 0x20 266 + #define SCSI_ASC_ILLEGAL_BLOCK 0x21 267 + #define SCSI_ASC_INVALID_CDB 0x24 268 + #define SCSI_ASC_INVALID_LUN 0x25 269 + #define SCSI_ASC_INVALID_PARAMETER 0x26 270 + #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31 271 + #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44 272 + 273 + /* SCSI ADDITIONAL SENSE Code Qualifiers */ 274 + 275 + #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00 276 + #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01 277 + #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01 278 + #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02 279 + #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03 280 + #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04 281 + #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08 282 + #define SCSI_ASCQ_INVALID_LUN_ID 0x09 283 + 284 + /** 285 + * DEVICE_SPECIFIC_PARAMETER in mode parameter header (see sbc2r16) to 286 + * enable DPOFUA support type 0x10 value. 287 + */ 288 + #define DEVICE_SPECIFIC_PARAMETER 0 289 + #define VPD_ID_DESCRIPTOR_LENGTH sizeof(VPD_IDENTIFICATION_DESCRIPTOR) 290 + 291 + /* MACROs to extract information from CDBs */ 292 + 293 + #define GET_OPCODE(cdb) cdb[0] 294 + 295 + #define GET_U8_FROM_CDB(cdb, index) (cdb[index] << 0) 296 + 297 + #define GET_U16_FROM_CDB(cdb, index) ((cdb[index] << 8) | (cdb[index + 1] << 0)) 298 + 299 + #define GET_U24_FROM_CDB(cdb, index) ((cdb[index] << 16) | \ 300 + (cdb[index + 1] << 8) | \ 301 + (cdb[index + 2] << 0)) 302 + 303 + #define GET_U32_FROM_CDB(cdb, index) ((cdb[index] << 24) | \ 304 + (cdb[index + 1] << 16) | \ 305 + (cdb[index + 2] << 8) | \ 306 + (cdb[index + 3] << 0)) 307 + 308 + #define GET_U64_FROM_CDB(cdb, index) ((((u64)cdb[index]) << 56) | \ 309 + (((u64)cdb[index + 1]) << 48) | \ 310 + (((u64)cdb[index + 2]) << 40) | \ 311 + (((u64)cdb[index + 3]) << 32) | \ 312 + (((u64)cdb[index + 4]) << 24) | \ 313 + (((u64)cdb[index + 5]) << 16) | \ 314 + (((u64)cdb[index + 6]) << 8) | \ 315 + (((u64)cdb[index + 7]) << 0)) 316 + 317 + /* Inquiry Helper Macros */ 318 + #define GET_INQ_EVPD_BIT(cdb) \ 319 + ((GET_U8_FROM_CDB(cdb, INQUIRY_EVPD_BYTE_OFFSET) & \ 320 + INQUIRY_EVPD_BIT_MASK) ? 1 : 0) 321 + 322 + #define GET_INQ_PAGE_CODE(cdb) \ 323 + (GET_U8_FROM_CDB(cdb, INQUIRY_PAGE_CODE_BYTE_OFFSET)) 324 + 325 + #define GET_INQ_ALLOC_LENGTH(cdb) \ 326 + (GET_U16_FROM_CDB(cdb, INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET)) 327 + 328 + /* Report LUNs Helper Macros */ 329 + #define GET_REPORT_LUNS_ALLOC_LENGTH(cdb) \ 330 + (GET_U32_FROM_CDB(cdb, REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET)) 331 + 332 + /* Read Capacity Helper Macros */ 333 + #define GET_READ_CAP_16_ALLOC_LENGTH(cdb) \ 334 + (GET_U32_FROM_CDB(cdb, READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET)) 335 + 336 + #define IS_READ_CAP_16(cdb) \ 337 + ((cdb[0] == SERVICE_ACTION_IN && cdb[1] == SAI_READ_CAPACITY_16) ? 1 : 0) 338 + 339 + /* Request Sense Helper Macros */ 340 + #define GET_REQUEST_SENSE_ALLOC_LENGTH(cdb) \ 341 + (GET_U8_FROM_CDB(cdb, REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET)) 342 + 343 + /* Mode Sense Helper Macros */ 344 + #define GET_MODE_SENSE_DBD(cdb) \ 345 + ((GET_U8_FROM_CDB(cdb, MODE_SENSE_DBD_OFFSET) & MODE_SENSE_DBD_MASK) >> \ 346 + MODE_SENSE_DBD_SHIFT) 347 + 348 + #define GET_MODE_SENSE_LLBAA(cdb) \ 349 + ((GET_U8_FROM_CDB(cdb, MODE_SENSE_LLBAA_OFFSET) & \ 350 + MODE_SENSE_LLBAA_MASK) >> MODE_SENSE_LLBAA_SHIFT) 351 + 352 + #define GET_MODE_SENSE_MPH_SIZE(cdb10) \ 353 + (cdb10 ? MODE_SENSE10_MPH_SIZE : MODE_SENSE6_MPH_SIZE) 354 + 355 + 356 + /* Struct to gather data that needs to be extracted from a SCSI CDB. 357 + Not conforming to any particular CDB variant, but compatible with all. */ 358 + 359 + struct nvme_trans_io_cdb { 360 + u8 fua; 361 + u8 prot_info; 362 + u64 lba; 363 + u32 xfer_len; 364 + }; 365 + 366 + 367 + /* Internal Helper Functions */ 368 + 369 + 370 + /* Copy data to userspace memory */ 371 + 372 + static int nvme_trans_copy_to_user(struct sg_io_hdr *hdr, void *from, 373 + unsigned long n) 374 + { 375 + int res = SNTI_TRANSLATION_SUCCESS; 376 + unsigned long not_copied; 377 + int i; 378 + void *index = from; 379 + size_t remaining = n; 380 + size_t xfer_len; 381 + 382 + if (hdr->iovec_count > 0) { 383 + struct sg_iovec *sgl = hdr->dxferp; 384 + 385 + for (i = 0; i < hdr->iovec_count; i++) { 386 + xfer_len = min(remaining, sgl[i].iov_len); 387 + not_copied = copy_to_user(__user sgl[i].iov_base, index, 388 + xfer_len); 389 + if (not_copied) { 390 + res = -EFAULT; 391 + break; 392 + } 393 + index += xfer_len; 394 + remaining -= xfer_len; 395 + if (remaining == 0) 396 + break; 397 + } 398 + return res; 399 + } 400 + not_copied = copy_to_user(__user hdr->dxferp, from, n); 401 + if (not_copied) 402 + res = -EFAULT; 403 + return res; 404 + } 405 + 406 + /* Copy data from userspace memory */ 407 + 408 + static int nvme_trans_copy_from_user(struct sg_io_hdr *hdr, void *to, 409 + unsigned long n) 410 + { 411 + int res = SNTI_TRANSLATION_SUCCESS; 412 + unsigned long not_copied; 413 + int i; 414 + void *index = to; 415 + size_t remaining = n; 416 + size_t xfer_len; 417 + 418 + if (hdr->iovec_count > 0) { 419 + struct sg_iovec *sgl = hdr->dxferp; 420 + 421 + for (i = 0; i < hdr->iovec_count; i++) { 422 + xfer_len = min(remaining, sgl[i].iov_len); 423 + not_copied = copy_from_user(index, 424 + __user sgl[i].iov_base, xfer_len); 425 + if (not_copied) { 426 + res = -EFAULT; 427 + break; 428 + } 429 + index += xfer_len; 430 + remaining -= xfer_len; 431 + if (remaining == 0) 432 + break; 433 + } 434 + return res; 435 + } 436 + 437 + not_copied = copy_from_user(to, __user hdr->dxferp, n); 438 + if (not_copied) 439 + res = -EFAULT; 440 + return res; 441 + } 442 + 443 + /* Status/Sense Buffer Writeback */ 444 + 445 + static int nvme_trans_completion(struct sg_io_hdr *hdr, u8 status, u8 sense_key, 446 + u8 asc, u8 ascq) 447 + { 448 + int res = SNTI_TRANSLATION_SUCCESS; 449 + u8 xfer_len; 450 + u8 resp[DESC_FMT_SENSE_DATA_SIZE]; 451 + 452 + if (scsi_status_is_good(status)) { 453 + hdr->status = SAM_STAT_GOOD; 454 + hdr->masked_status = GOOD; 455 + hdr->host_status = DID_OK; 456 + hdr->driver_status = DRIVER_OK; 457 + hdr->sb_len_wr = 0; 458 + } else { 459 + hdr->status = status; 460 + hdr->masked_status = status >> 1; 461 + hdr->host_status = DID_OK; 462 + hdr->driver_status = DRIVER_OK; 463 + 464 + memset(resp, 0, DESC_FMT_SENSE_DATA_SIZE); 465 + resp[0] = DESC_FORMAT_SENSE_DATA; 466 + resp[1] = sense_key; 467 + resp[2] = asc; 468 + resp[3] = ascq; 469 + 470 + xfer_len = min_t(u8, hdr->mx_sb_len, DESC_FMT_SENSE_DATA_SIZE); 471 + hdr->sb_len_wr = xfer_len; 472 + if (copy_to_user(__user hdr->sbp, resp, xfer_len) > 0) 473 + res = -EFAULT; 474 + } 475 + 476 + return res; 477 + } 478 + 479 + static int nvme_trans_status_code(struct sg_io_hdr *hdr, int nvme_sc) 480 + { 481 + u8 status, sense_key, asc, ascq; 482 + int res = SNTI_TRANSLATION_SUCCESS; 483 + 484 + /* For non-nvme (Linux) errors, simply return the error code */ 485 + if (nvme_sc < 0) 486 + return nvme_sc; 487 + 488 + /* Mask DNR, More, and reserved fields */ 489 + nvme_sc &= 0x7FF; 490 + 491 + switch (nvme_sc) { 492 + /* Generic Command Status */ 493 + case NVME_SC_SUCCESS: 494 + status = SAM_STAT_GOOD; 495 + sense_key = NO_SENSE; 496 + asc = SCSI_ASC_NO_SENSE; 497 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 498 + break; 499 + case NVME_SC_INVALID_OPCODE: 500 + status = SAM_STAT_CHECK_CONDITION; 501 + sense_key = ILLEGAL_REQUEST; 502 + asc = SCSI_ASC_ILLEGAL_COMMAND; 503 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 504 + break; 505 + case NVME_SC_INVALID_FIELD: 506 + status = SAM_STAT_CHECK_CONDITION; 507 + sense_key = ILLEGAL_REQUEST; 508 + asc = SCSI_ASC_INVALID_CDB; 509 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 510 + break; 511 + case NVME_SC_DATA_XFER_ERROR: 512 + status = SAM_STAT_CHECK_CONDITION; 513 + sense_key = MEDIUM_ERROR; 514 + asc = SCSI_ASC_NO_SENSE; 515 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 516 + break; 517 + case NVME_SC_POWER_LOSS: 518 + status = SAM_STAT_TASK_ABORTED; 519 + sense_key = ABORTED_COMMAND; 520 + asc = SCSI_ASC_WARNING; 521 + ascq = SCSI_ASCQ_POWER_LOSS_EXPECTED; 522 + break; 523 + case NVME_SC_INTERNAL: 524 + status = SAM_STAT_CHECK_CONDITION; 525 + sense_key = HARDWARE_ERROR; 526 + asc = SCSI_ASC_INTERNAL_TARGET_FAILURE; 527 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 528 + break; 529 + case NVME_SC_ABORT_REQ: 530 + status = SAM_STAT_TASK_ABORTED; 531 + sense_key = ABORTED_COMMAND; 532 + asc = SCSI_ASC_NO_SENSE; 533 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 534 + break; 535 + case NVME_SC_ABORT_QUEUE: 536 + status = SAM_STAT_TASK_ABORTED; 537 + sense_key = ABORTED_COMMAND; 538 + asc = SCSI_ASC_NO_SENSE; 539 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 540 + break; 541 + case NVME_SC_FUSED_FAIL: 542 + status = SAM_STAT_TASK_ABORTED; 543 + sense_key = ABORTED_COMMAND; 544 + asc = SCSI_ASC_NO_SENSE; 545 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 546 + break; 547 + case NVME_SC_FUSED_MISSING: 548 + status = SAM_STAT_TASK_ABORTED; 549 + sense_key = ABORTED_COMMAND; 550 + asc = SCSI_ASC_NO_SENSE; 551 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 552 + break; 553 + case NVME_SC_INVALID_NS: 554 + status = SAM_STAT_CHECK_CONDITION; 555 + sense_key = ILLEGAL_REQUEST; 556 + asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID; 557 + ascq = SCSI_ASCQ_INVALID_LUN_ID; 558 + break; 559 + case NVME_SC_LBA_RANGE: 560 + status = SAM_STAT_CHECK_CONDITION; 561 + sense_key = ILLEGAL_REQUEST; 562 + asc = SCSI_ASC_ILLEGAL_BLOCK; 563 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 564 + break; 565 + case NVME_SC_CAP_EXCEEDED: 566 + status = SAM_STAT_CHECK_CONDITION; 567 + sense_key = MEDIUM_ERROR; 568 + asc = SCSI_ASC_NO_SENSE; 569 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 570 + break; 571 + case NVME_SC_NS_NOT_READY: 572 + status = SAM_STAT_CHECK_CONDITION; 573 + sense_key = NOT_READY; 574 + asc = SCSI_ASC_LUN_NOT_READY; 575 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 576 + break; 577 + 578 + /* Command Specific Status */ 579 + case NVME_SC_INVALID_FORMAT: 580 + status = SAM_STAT_CHECK_CONDITION; 581 + sense_key = ILLEGAL_REQUEST; 582 + asc = SCSI_ASC_FORMAT_COMMAND_FAILED; 583 + ascq = SCSI_ASCQ_FORMAT_COMMAND_FAILED; 584 + break; 585 + case NVME_SC_BAD_ATTRIBUTES: 586 + status = SAM_STAT_CHECK_CONDITION; 587 + sense_key = ILLEGAL_REQUEST; 588 + asc = SCSI_ASC_INVALID_CDB; 589 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 590 + break; 591 + 592 + /* Media Errors */ 593 + case NVME_SC_WRITE_FAULT: 594 + status = SAM_STAT_CHECK_CONDITION; 595 + sense_key = MEDIUM_ERROR; 596 + asc = SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT; 597 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 598 + break; 599 + case NVME_SC_READ_ERROR: 600 + status = SAM_STAT_CHECK_CONDITION; 601 + sense_key = MEDIUM_ERROR; 602 + asc = SCSI_ASC_UNRECOVERED_READ_ERROR; 603 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 604 + break; 605 + case NVME_SC_GUARD_CHECK: 606 + status = SAM_STAT_CHECK_CONDITION; 607 + sense_key = MEDIUM_ERROR; 608 + asc = SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED; 609 + ascq = SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED; 610 + break; 611 + case NVME_SC_APPTAG_CHECK: 612 + status = SAM_STAT_CHECK_CONDITION; 613 + sense_key = MEDIUM_ERROR; 614 + asc = SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED; 615 + ascq = SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED; 616 + break; 617 + case NVME_SC_REFTAG_CHECK: 618 + status = SAM_STAT_CHECK_CONDITION; 619 + sense_key = MEDIUM_ERROR; 620 + asc = SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED; 621 + ascq = SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED; 622 + break; 623 + case NVME_SC_COMPARE_FAILED: 624 + status = SAM_STAT_CHECK_CONDITION; 625 + sense_key = MISCOMPARE; 626 + asc = SCSI_ASC_MISCOMPARE_DURING_VERIFY; 627 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 628 + break; 629 + case NVME_SC_ACCESS_DENIED: 630 + status = SAM_STAT_CHECK_CONDITION; 631 + sense_key = ILLEGAL_REQUEST; 632 + asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID; 633 + ascq = SCSI_ASCQ_INVALID_LUN_ID; 634 + break; 635 + 636 + /* Unspecified/Default */ 637 + case NVME_SC_CMDID_CONFLICT: 638 + case NVME_SC_CMD_SEQ_ERROR: 639 + case NVME_SC_CQ_INVALID: 640 + case NVME_SC_QID_INVALID: 641 + case NVME_SC_QUEUE_SIZE: 642 + case NVME_SC_ABORT_LIMIT: 643 + case NVME_SC_ABORT_MISSING: 644 + case NVME_SC_ASYNC_LIMIT: 645 + case NVME_SC_FIRMWARE_SLOT: 646 + case NVME_SC_FIRMWARE_IMAGE: 647 + case NVME_SC_INVALID_VECTOR: 648 + case NVME_SC_INVALID_LOG_PAGE: 649 + default: 650 + status = SAM_STAT_CHECK_CONDITION; 651 + sense_key = ILLEGAL_REQUEST; 652 + asc = SCSI_ASC_NO_SENSE; 653 + ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 654 + break; 655 + } 656 + 657 + res = nvme_trans_completion(hdr, status, sense_key, asc, ascq); 658 + 659 + return res; 660 + } 661 + 662 + /* INQUIRY Helper Functions */ 663 + 664 + static int nvme_trans_standard_inquiry_page(struct nvme_ns *ns, 665 + struct sg_io_hdr *hdr, u8 *inq_response, 666 + int alloc_len) 667 + { 668 + struct nvme_dev *dev = ns->dev; 669 + dma_addr_t dma_addr; 670 + void *mem; 671 + struct nvme_id_ns *id_ns; 672 + int res = SNTI_TRANSLATION_SUCCESS; 673 + int nvme_sc; 674 + int xfer_len; 675 + u8 resp_data_format = 0x02; 676 + u8 protect; 677 + u8 cmdque = 0x01 << 1; 678 + 679 + mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 680 + &dma_addr, GFP_KERNEL); 681 + if (mem == NULL) { 682 + res = -ENOMEM; 683 + goto out_dma; 684 + } 685 + 686 + /* nvme ns identify - use DPS value for PROTECT field */ 687 + nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); 688 + res = nvme_trans_status_code(hdr, nvme_sc); 689 + /* 690 + * If nvme_sc was -ve, res will be -ve here. 691 + * If nvme_sc was +ve, the status would bace been translated, and res 692 + * can only be 0 or -ve. 693 + * - If 0 && nvme_sc > 0, then go into next if where res gets nvme_sc 694 + * - If -ve, return because its a Linux error. 695 + */ 696 + if (res) 697 + goto out_free; 698 + if (nvme_sc) { 699 + res = nvme_sc; 700 + goto out_free; 701 + } 702 + id_ns = mem; 703 + (id_ns->dps) ? (protect = 0x01) : (protect = 0); 704 + 705 + memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); 706 + inq_response[2] = VERSION_SPC_4; 707 + inq_response[3] = resp_data_format; /*normaca=0 | hisup=0 */ 708 + inq_response[4] = ADDITIONAL_STD_INQ_LENGTH; 709 + inq_response[5] = protect; /* sccs=0 | acc=0 | tpgs=0 | pc3=0 */ 710 + inq_response[7] = cmdque; /* wbus16=0 | sync=0 | vs=0 */ 711 + strncpy(&inq_response[8], "NVMe ", 8); 712 + strncpy(&inq_response[16], dev->model, 16); 713 + strncpy(&inq_response[32], dev->firmware_rev, 4); 714 + 715 + xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); 716 + res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); 717 + 718 + out_free: 719 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem, 720 + dma_addr); 721 + out_dma: 722 + return res; 723 + } 724 + 725 + static int nvme_trans_supported_vpd_pages(struct nvme_ns *ns, 726 + struct sg_io_hdr *hdr, u8 *inq_response, 727 + int alloc_len) 728 + { 729 + int res = SNTI_TRANSLATION_SUCCESS; 730 + int xfer_len; 731 + 732 + memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); 733 + inq_response[1] = INQ_SUPPORTED_VPD_PAGES_PAGE; /* Page Code */ 734 + inq_response[3] = INQ_NUM_SUPPORTED_VPD_PAGES; /* Page Length */ 735 + inq_response[4] = INQ_SUPPORTED_VPD_PAGES_PAGE; 736 + inq_response[5] = INQ_UNIT_SERIAL_NUMBER_PAGE; 737 + inq_response[6] = INQ_DEVICE_IDENTIFICATION_PAGE; 738 + inq_response[7] = INQ_EXTENDED_INQUIRY_DATA_PAGE; 739 + inq_response[8] = INQ_BDEV_CHARACTERISTICS_PAGE; 740 + 741 + xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); 742 + res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); 743 + 744 + return res; 745 + } 746 + 747 + static int nvme_trans_unit_serial_page(struct nvme_ns *ns, 748 + struct sg_io_hdr *hdr, u8 *inq_response, 749 + int alloc_len) 750 + { 751 + struct nvme_dev *dev = ns->dev; 752 + int res = SNTI_TRANSLATION_SUCCESS; 753 + int xfer_len; 754 + 755 + memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); 756 + inq_response[1] = INQ_UNIT_SERIAL_NUMBER_PAGE; /* Page Code */ 757 + inq_response[3] = INQ_SERIAL_NUMBER_LENGTH; /* Page Length */ 758 + strncpy(&inq_response[4], dev->serial, INQ_SERIAL_NUMBER_LENGTH); 759 + 760 + xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); 761 + res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); 762 + 763 + return res; 764 + } 765 + 766 + static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, 767 + u8 *inq_response, int alloc_len) 768 + { 769 + struct nvme_dev *dev = ns->dev; 770 + dma_addr_t dma_addr; 771 + void *mem; 772 + struct nvme_id_ctrl *id_ctrl; 773 + int res = SNTI_TRANSLATION_SUCCESS; 774 + int nvme_sc; 775 + u8 ieee[4]; 776 + int xfer_len; 777 + u32 tmp_id = cpu_to_be64(ns->ns_id); 778 + 779 + mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 780 + &dma_addr, GFP_KERNEL); 781 + if (mem == NULL) { 782 + res = -ENOMEM; 783 + goto out_dma; 784 + } 785 + 786 + /* nvme controller identify */ 787 + nvme_sc = nvme_identify(dev, 0, 1, dma_addr); 788 + res = nvme_trans_status_code(hdr, nvme_sc); 789 + if (res) 790 + goto out_free; 791 + if (nvme_sc) { 792 + res = nvme_sc; 793 + goto out_free; 794 + } 795 + id_ctrl = mem; 796 + 797 + /* Since SCSI tried to save 4 bits... [SPC-4(r34) Table 591] */ 798 + ieee[0] = id_ctrl->ieee[0] << 4; 799 + ieee[1] = id_ctrl->ieee[0] >> 4 | id_ctrl->ieee[1] << 4; 800 + ieee[2] = id_ctrl->ieee[1] >> 4 | id_ctrl->ieee[2] << 4; 801 + ieee[3] = id_ctrl->ieee[2] >> 4; 802 + 803 + memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); 804 + inq_response[1] = INQ_DEVICE_IDENTIFICATION_PAGE; /* Page Code */ 805 + inq_response[3] = 20; /* Page Length */ 806 + /* Designation Descriptor start */ 807 + inq_response[4] = 0x01; /* Proto ID=0h | Code set=1h */ 808 + inq_response[5] = 0x03; /* PIV=0b | Asso=00b | Designator Type=3h */ 809 + inq_response[6] = 0x00; /* Rsvd */ 810 + inq_response[7] = 16; /* Designator Length */ 811 + /* Designator start */ 812 + inq_response[8] = 0x60 | ieee[3]; /* NAA=6h | IEEE ID MSB, High nibble*/ 813 + inq_response[9] = ieee[2]; /* IEEE ID */ 814 + inq_response[10] = ieee[1]; /* IEEE ID */ 815 + inq_response[11] = ieee[0]; /* IEEE ID| Vendor Specific ID... */ 816 + inq_response[12] = (dev->pci_dev->vendor & 0xFF00) >> 8; 817 + inq_response[13] = (dev->pci_dev->vendor & 0x00FF); 818 + inq_response[14] = dev->serial[0]; 819 + inq_response[15] = dev->serial[1]; 820 + inq_response[16] = dev->model[0]; 821 + inq_response[17] = dev->model[1]; 822 + memcpy(&inq_response[18], &tmp_id, sizeof(u32)); 823 + /* Last 2 bytes are zero */ 824 + 825 + xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); 826 + res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); 827 + 828 + out_free: 829 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem, 830 + dma_addr); 831 + out_dma: 832 + return res; 833 + } 834 + 835 + static int nvme_trans_ext_inq_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, 836 + int alloc_len) 837 + { 838 + u8 *inq_response; 839 + int res = SNTI_TRANSLATION_SUCCESS; 840 + int nvme_sc; 841 + struct nvme_dev *dev = ns->dev; 842 + dma_addr_t dma_addr; 843 + void *mem; 844 + struct nvme_id_ctrl *id_ctrl; 845 + struct nvme_id_ns *id_ns; 846 + int xfer_len; 847 + u8 microcode = 0x80; 848 + u8 spt; 849 + u8 spt_lut[8] = {0, 0, 2, 1, 4, 6, 5, 7}; 850 + u8 grd_chk, app_chk, ref_chk, protect; 851 + u8 uask_sup = 0x20; 852 + u8 v_sup; 853 + u8 luiclr = 0x01; 854 + 855 + inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL); 856 + if (inq_response == NULL) { 857 + res = -ENOMEM; 858 + goto out_mem; 859 + } 860 + 861 + mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 862 + &dma_addr, GFP_KERNEL); 863 + if (mem == NULL) { 864 + res = -ENOMEM; 865 + goto out_dma; 866 + } 867 + 868 + /* nvme ns identify */ 869 + nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); 870 + res = nvme_trans_status_code(hdr, nvme_sc); 871 + if (res) 872 + goto out_free; 873 + if (nvme_sc) { 874 + res = nvme_sc; 875 + goto out_free; 876 + } 877 + id_ns = mem; 878 + spt = spt_lut[(id_ns->dpc) & 0x07] << 3; 879 + (id_ns->dps) ? (protect = 0x01) : (protect = 0); 880 + grd_chk = protect << 2; 881 + app_chk = protect << 1; 882 + ref_chk = protect; 883 + 884 + /* nvme controller identify */ 885 + nvme_sc = nvme_identify(dev, 0, 1, dma_addr); 886 + res = nvme_trans_status_code(hdr, nvme_sc); 887 + if (res) 888 + goto out_free; 889 + if (nvme_sc) { 890 + res = nvme_sc; 891 + goto out_free; 892 + } 893 + id_ctrl = mem; 894 + v_sup = id_ctrl->vwc; 895 + 896 + memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); 897 + inq_response[1] = INQ_EXTENDED_INQUIRY_DATA_PAGE; /* Page Code */ 898 + inq_response[2] = 0x00; /* Page Length MSB */ 899 + inq_response[3] = 0x3C; /* Page Length LSB */ 900 + inq_response[4] = microcode | spt | grd_chk | app_chk | ref_chk; 901 + inq_response[5] = uask_sup; 902 + inq_response[6] = v_sup; 903 + inq_response[7] = luiclr; 904 + inq_response[8] = 0; 905 + inq_response[9] = 0; 906 + 907 + xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); 908 + res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); 909 + 910 + out_free: 911 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem, 912 + dma_addr); 913 + out_dma: 914 + kfree(inq_response); 915 + out_mem: 916 + return res; 917 + } 918 + 919 + static int nvme_trans_bdev_char_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, 920 + int alloc_len) 921 + { 922 + u8 *inq_response; 923 + int res = SNTI_TRANSLATION_SUCCESS; 924 + int xfer_len; 925 + 926 + inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL); 927 + if (inq_response == NULL) { 928 + res = -ENOMEM; 929 + goto out_mem; 930 + } 931 + 932 + memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); 933 + inq_response[1] = INQ_BDEV_CHARACTERISTICS_PAGE; /* Page Code */ 934 + inq_response[2] = 0x00; /* Page Length MSB */ 935 + inq_response[3] = 0x3C; /* Page Length LSB */ 936 + inq_response[4] = 0x00; /* Medium Rotation Rate MSB */ 937 + inq_response[5] = 0x01; /* Medium Rotation Rate LSB */ 938 + inq_response[6] = 0x00; /* Form Factor */ 939 + 940 + xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); 941 + res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); 942 + 943 + kfree(inq_response); 944 + out_mem: 945 + return res; 946 + } 947 + 948 + /* LOG SENSE Helper Functions */ 949 + 950 + static int nvme_trans_log_supp_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr, 951 + int alloc_len) 952 + { 953 + int res = SNTI_TRANSLATION_SUCCESS; 954 + int xfer_len; 955 + u8 *log_response; 956 + 957 + log_response = kmalloc(LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH, GFP_KERNEL); 958 + if (log_response == NULL) { 959 + res = -ENOMEM; 960 + goto out_mem; 961 + } 962 + memset(log_response, 0, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH); 963 + 964 + log_response[0] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE; 965 + /* Subpage=0x00, Page Length MSB=0 */ 966 + log_response[3] = SUPPORTED_LOG_PAGES_PAGE_LENGTH; 967 + log_response[4] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE; 968 + log_response[5] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE; 969 + log_response[6] = LOG_PAGE_TEMPERATURE_PAGE; 970 + 971 + xfer_len = min(alloc_len, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH); 972 + res = nvme_trans_copy_to_user(hdr, log_response, xfer_len); 973 + 974 + kfree(log_response); 975 + out_mem: 976 + return res; 977 + } 978 + 979 + static int nvme_trans_log_info_exceptions(struct nvme_ns *ns, 980 + struct sg_io_hdr *hdr, int alloc_len) 981 + { 982 + int res = SNTI_TRANSLATION_SUCCESS; 983 + int xfer_len; 984 + u8 *log_response; 985 + struct nvme_command c; 986 + struct nvme_dev *dev = ns->dev; 987 + struct nvme_smart_log *smart_log; 988 + dma_addr_t dma_addr; 989 + void *mem; 990 + u8 temp_c; 991 + u16 temp_k; 992 + 993 + log_response = kmalloc(LOG_INFO_EXCP_PAGE_LENGTH, GFP_KERNEL); 994 + if (log_response == NULL) { 995 + res = -ENOMEM; 996 + goto out_mem; 997 + } 998 + memset(log_response, 0, LOG_INFO_EXCP_PAGE_LENGTH); 999 + 1000 + mem = dma_alloc_coherent(&dev->pci_dev->dev, 1001 + sizeof(struct nvme_smart_log), 1002 + &dma_addr, GFP_KERNEL); 1003 + if (mem == NULL) { 1004 + res = -ENOMEM; 1005 + goto out_dma; 1006 + } 1007 + 1008 + /* Get SMART Log Page */ 1009 + memset(&c, 0, sizeof(c)); 1010 + c.common.opcode = nvme_admin_get_log_page; 1011 + c.common.nsid = cpu_to_le32(0xFFFFFFFF); 1012 + c.common.prp1 = cpu_to_le64(dma_addr); 1013 + c.common.cdw10[0] = cpu_to_le32(((sizeof(struct nvme_smart_log) / 1014 + BYTES_TO_DWORDS) << 16) | NVME_GET_SMART_LOG_PAGE); 1015 + res = nvme_submit_admin_cmd(dev, &c, NULL); 1016 + if (res != NVME_SC_SUCCESS) { 1017 + temp_c = LOG_TEMP_UNKNOWN; 1018 + } else { 1019 + smart_log = mem; 1020 + temp_k = (smart_log->temperature[1] << 8) + 1021 + (smart_log->temperature[0]); 1022 + temp_c = temp_k - KELVIN_TEMP_FACTOR; 1023 + } 1024 + 1025 + log_response[0] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE; 1026 + /* Subpage=0x00, Page Length MSB=0 */ 1027 + log_response[3] = REMAINING_INFO_EXCP_PAGE_LENGTH; 1028 + /* Informational Exceptions Log Parameter 1 Start */ 1029 + /* Parameter Code=0x0000 bytes 4,5 */ 1030 + log_response[6] = 0x23; /* DU=0, TSD=1, ETC=0, TMC=0, FMT_AND_LNK=11b */ 1031 + log_response[7] = 0x04; /* PARAMETER LENGTH */ 1032 + /* Add sense Code and qualifier = 0x00 each */ 1033 + /* Use Temperature from NVMe Get Log Page, convert to C from K */ 1034 + log_response[10] = temp_c; 1035 + 1036 + xfer_len = min(alloc_len, LOG_INFO_EXCP_PAGE_LENGTH); 1037 + res = nvme_trans_copy_to_user(hdr, log_response, xfer_len); 1038 + 1039 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log), 1040 + mem, dma_addr); 1041 + out_dma: 1042 + kfree(log_response); 1043 + out_mem: 1044 + return res; 1045 + } 1046 + 1047 + static int nvme_trans_log_temperature(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1048 + int alloc_len) 1049 + { 1050 + int res = SNTI_TRANSLATION_SUCCESS; 1051 + int xfer_len; 1052 + u8 *log_response; 1053 + struct nvme_command c; 1054 + struct nvme_dev *dev = ns->dev; 1055 + struct nvme_smart_log *smart_log; 1056 + dma_addr_t dma_addr; 1057 + void *mem; 1058 + u32 feature_resp; 1059 + u8 temp_c_cur, temp_c_thresh; 1060 + u16 temp_k; 1061 + 1062 + log_response = kmalloc(LOG_TEMP_PAGE_LENGTH, GFP_KERNEL); 1063 + if (log_response == NULL) { 1064 + res = -ENOMEM; 1065 + goto out_mem; 1066 + } 1067 + memset(log_response, 0, LOG_TEMP_PAGE_LENGTH); 1068 + 1069 + mem = dma_alloc_coherent(&dev->pci_dev->dev, 1070 + sizeof(struct nvme_smart_log), 1071 + &dma_addr, GFP_KERNEL); 1072 + if (mem == NULL) { 1073 + res = -ENOMEM; 1074 + goto out_dma; 1075 + } 1076 + 1077 + /* Get SMART Log Page */ 1078 + memset(&c, 0, sizeof(c)); 1079 + c.common.opcode = nvme_admin_get_log_page; 1080 + c.common.nsid = cpu_to_le32(0xFFFFFFFF); 1081 + c.common.prp1 = cpu_to_le64(dma_addr); 1082 + c.common.cdw10[0] = cpu_to_le32(((sizeof(struct nvme_smart_log) / 1083 + BYTES_TO_DWORDS) << 16) | NVME_GET_SMART_LOG_PAGE); 1084 + res = nvme_submit_admin_cmd(dev, &c, NULL); 1085 + if (res != NVME_SC_SUCCESS) { 1086 + temp_c_cur = LOG_TEMP_UNKNOWN; 1087 + } else { 1088 + smart_log = mem; 1089 + temp_k = (smart_log->temperature[1] << 8) + 1090 + (smart_log->temperature[0]); 1091 + temp_c_cur = temp_k - KELVIN_TEMP_FACTOR; 1092 + } 1093 + 1094 + /* Get Features for Temp Threshold */ 1095 + res = nvme_get_features(dev, NVME_FEAT_TEMP_THRESH, 0, 0, 1096 + &feature_resp); 1097 + if (res != NVME_SC_SUCCESS) 1098 + temp_c_thresh = LOG_TEMP_UNKNOWN; 1099 + else 1100 + temp_c_thresh = (feature_resp & 0xFFFF) - KELVIN_TEMP_FACTOR; 1101 + 1102 + log_response[0] = LOG_PAGE_TEMPERATURE_PAGE; 1103 + /* Subpage=0x00, Page Length MSB=0 */ 1104 + log_response[3] = REMAINING_TEMP_PAGE_LENGTH; 1105 + /* Temperature Log Parameter 1 (Temperature) Start */ 1106 + /* Parameter Code = 0x0000 */ 1107 + log_response[6] = 0x01; /* Format and Linking = 01b */ 1108 + log_response[7] = 0x02; /* Parameter Length */ 1109 + /* Use Temperature from NVMe Get Log Page, convert to C from K */ 1110 + log_response[9] = temp_c_cur; 1111 + /* Temperature Log Parameter 2 (Reference Temperature) Start */ 1112 + log_response[11] = 0x01; /* Parameter Code = 0x0001 */ 1113 + log_response[12] = 0x01; /* Format and Linking = 01b */ 1114 + log_response[13] = 0x02; /* Parameter Length */ 1115 + /* Use Temperature Thresh from NVMe Get Log Page, convert to C from K */ 1116 + log_response[15] = temp_c_thresh; 1117 + 1118 + xfer_len = min(alloc_len, LOG_TEMP_PAGE_LENGTH); 1119 + res = nvme_trans_copy_to_user(hdr, log_response, xfer_len); 1120 + 1121 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log), 1122 + mem, dma_addr); 1123 + out_dma: 1124 + kfree(log_response); 1125 + out_mem: 1126 + return res; 1127 + } 1128 + 1129 + /* MODE SENSE Helper Functions */ 1130 + 1131 + static int nvme_trans_fill_mode_parm_hdr(u8 *resp, int len, u8 cdb10, u8 llbaa, 1132 + u16 mode_data_length, u16 blk_desc_len) 1133 + { 1134 + /* Quick check to make sure I don't stomp on my own memory... */ 1135 + if ((cdb10 && len < 8) || (!cdb10 && len < 4)) 1136 + return SNTI_INTERNAL_ERROR; 1137 + 1138 + if (cdb10) { 1139 + resp[0] = (mode_data_length & 0xFF00) >> 8; 1140 + resp[1] = (mode_data_length & 0x00FF); 1141 + /* resp[2] and [3] are zero */ 1142 + resp[4] = llbaa; 1143 + resp[5] = RESERVED_FIELD; 1144 + resp[6] = (blk_desc_len & 0xFF00) >> 8; 1145 + resp[7] = (blk_desc_len & 0x00FF); 1146 + } else { 1147 + resp[0] = (mode_data_length & 0x00FF); 1148 + /* resp[1] and [2] are zero */ 1149 + resp[3] = (blk_desc_len & 0x00FF); 1150 + } 1151 + 1152 + return SNTI_TRANSLATION_SUCCESS; 1153 + } 1154 + 1155 + static int nvme_trans_fill_blk_desc(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1156 + u8 *resp, int len, u8 llbaa) 1157 + { 1158 + int res = SNTI_TRANSLATION_SUCCESS; 1159 + int nvme_sc; 1160 + struct nvme_dev *dev = ns->dev; 1161 + dma_addr_t dma_addr; 1162 + void *mem; 1163 + struct nvme_id_ns *id_ns; 1164 + u8 flbas; 1165 + u32 lba_length; 1166 + 1167 + if (llbaa == 0 && len < MODE_PAGE_BLK_DES_LEN) 1168 + return SNTI_INTERNAL_ERROR; 1169 + else if (llbaa > 0 && len < MODE_PAGE_LLBAA_BLK_DES_LEN) 1170 + return SNTI_INTERNAL_ERROR; 1171 + 1172 + mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 1173 + &dma_addr, GFP_KERNEL); 1174 + if (mem == NULL) { 1175 + res = -ENOMEM; 1176 + goto out; 1177 + } 1178 + 1179 + /* nvme ns identify */ 1180 + nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); 1181 + res = nvme_trans_status_code(hdr, nvme_sc); 1182 + if (res) 1183 + goto out_dma; 1184 + if (nvme_sc) { 1185 + res = nvme_sc; 1186 + goto out_dma; 1187 + } 1188 + id_ns = mem; 1189 + flbas = (id_ns->flbas) & 0x0F; 1190 + lba_length = (1 << (id_ns->lbaf[flbas].ds)); 1191 + 1192 + if (llbaa == 0) { 1193 + u32 tmp_cap = cpu_to_be32(id_ns->ncap); 1194 + /* Byte 4 is reserved */ 1195 + u32 tmp_len = cpu_to_be32(lba_length) & 0x00FFFFFF; 1196 + 1197 + memcpy(resp, &tmp_cap, sizeof(u32)); 1198 + memcpy(&resp[4], &tmp_len, sizeof(u32)); 1199 + } else { 1200 + u64 tmp_cap = cpu_to_be64(id_ns->ncap); 1201 + u32 tmp_len = cpu_to_be32(lba_length); 1202 + 1203 + memcpy(resp, &tmp_cap, sizeof(u64)); 1204 + /* Bytes 8, 9, 10, 11 are reserved */ 1205 + memcpy(&resp[12], &tmp_len, sizeof(u32)); 1206 + } 1207 + 1208 + out_dma: 1209 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem, 1210 + dma_addr); 1211 + out: 1212 + return res; 1213 + } 1214 + 1215 + static int nvme_trans_fill_control_page(struct nvme_ns *ns, 1216 + struct sg_io_hdr *hdr, u8 *resp, 1217 + int len) 1218 + { 1219 + if (len < MODE_PAGE_CONTROL_LEN) 1220 + return SNTI_INTERNAL_ERROR; 1221 + 1222 + resp[0] = MODE_PAGE_CONTROL; 1223 + resp[1] = MODE_PAGE_CONTROL_LEN_FIELD; 1224 + resp[2] = 0x0E; /* TST=000b, TMF_ONLY=0, DPICZ=1, 1225 + * D_SENSE=1, GLTSD=1, RLEC=0 */ 1226 + resp[3] = 0x12; /* Q_ALGO_MODIFIER=1h, NUAR=0, QERR=01b */ 1227 + /* Byte 4: VS=0, RAC=0, UA_INT=0, SWP=0 */ 1228 + resp[5] = 0x40; /* ATO=0, TAS=1, ATMPE=0, RWWP=0, AUTOLOAD=0 */ 1229 + /* resp[6] and [7] are obsolete, thus zero */ 1230 + resp[8] = 0xFF; /* Busy timeout period = 0xffff */ 1231 + resp[9] = 0xFF; 1232 + /* Bytes 10,11: Extended selftest completion time = 0x0000 */ 1233 + 1234 + return SNTI_TRANSLATION_SUCCESS; 1235 + } 1236 + 1237 + static int nvme_trans_fill_caching_page(struct nvme_ns *ns, 1238 + struct sg_io_hdr *hdr, 1239 + u8 *resp, int len) 1240 + { 1241 + int res = SNTI_TRANSLATION_SUCCESS; 1242 + int nvme_sc; 1243 + struct nvme_dev *dev = ns->dev; 1244 + u32 feature_resp; 1245 + u8 vwc; 1246 + 1247 + if (len < MODE_PAGE_CACHING_LEN) 1248 + return SNTI_INTERNAL_ERROR; 1249 + 1250 + nvme_sc = nvme_get_features(dev, NVME_FEAT_VOLATILE_WC, 0, 0, 1251 + &feature_resp); 1252 + res = nvme_trans_status_code(hdr, nvme_sc); 1253 + if (res) 1254 + goto out; 1255 + if (nvme_sc) { 1256 + res = nvme_sc; 1257 + goto out; 1258 + } 1259 + vwc = feature_resp & 0x00000001; 1260 + 1261 + resp[0] = MODE_PAGE_CACHING; 1262 + resp[1] = MODE_PAGE_CACHING_LEN_FIELD; 1263 + resp[2] = vwc << 2; 1264 + 1265 + out: 1266 + return res; 1267 + } 1268 + 1269 + static int nvme_trans_fill_pow_cnd_page(struct nvme_ns *ns, 1270 + struct sg_io_hdr *hdr, u8 *resp, 1271 + int len) 1272 + { 1273 + int res = SNTI_TRANSLATION_SUCCESS; 1274 + 1275 + if (len < MODE_PAGE_POW_CND_LEN) 1276 + return SNTI_INTERNAL_ERROR; 1277 + 1278 + resp[0] = MODE_PAGE_POWER_CONDITION; 1279 + resp[1] = MODE_PAGE_POW_CND_LEN_FIELD; 1280 + /* All other bytes are zero */ 1281 + 1282 + return res; 1283 + } 1284 + 1285 + static int nvme_trans_fill_inf_exc_page(struct nvme_ns *ns, 1286 + struct sg_io_hdr *hdr, u8 *resp, 1287 + int len) 1288 + { 1289 + int res = SNTI_TRANSLATION_SUCCESS; 1290 + 1291 + if (len < MODE_PAGE_INF_EXC_LEN) 1292 + return SNTI_INTERNAL_ERROR; 1293 + 1294 + resp[0] = MODE_PAGE_INFO_EXCEP; 1295 + resp[1] = MODE_PAGE_INF_EXC_LEN_FIELD; 1296 + resp[2] = 0x88; 1297 + /* All other bytes are zero */ 1298 + 1299 + return res; 1300 + } 1301 + 1302 + static int nvme_trans_fill_all_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1303 + u8 *resp, int len) 1304 + { 1305 + int res = SNTI_TRANSLATION_SUCCESS; 1306 + u16 mode_pages_offset_1 = 0; 1307 + u16 mode_pages_offset_2, mode_pages_offset_3, mode_pages_offset_4; 1308 + 1309 + mode_pages_offset_2 = mode_pages_offset_1 + MODE_PAGE_CACHING_LEN; 1310 + mode_pages_offset_3 = mode_pages_offset_2 + MODE_PAGE_CONTROL_LEN; 1311 + mode_pages_offset_4 = mode_pages_offset_3 + MODE_PAGE_POW_CND_LEN; 1312 + 1313 + res = nvme_trans_fill_caching_page(ns, hdr, &resp[mode_pages_offset_1], 1314 + MODE_PAGE_CACHING_LEN); 1315 + if (res != SNTI_TRANSLATION_SUCCESS) 1316 + goto out; 1317 + res = nvme_trans_fill_control_page(ns, hdr, &resp[mode_pages_offset_2], 1318 + MODE_PAGE_CONTROL_LEN); 1319 + if (res != SNTI_TRANSLATION_SUCCESS) 1320 + goto out; 1321 + res = nvme_trans_fill_pow_cnd_page(ns, hdr, &resp[mode_pages_offset_3], 1322 + MODE_PAGE_POW_CND_LEN); 1323 + if (res != SNTI_TRANSLATION_SUCCESS) 1324 + goto out; 1325 + res = nvme_trans_fill_inf_exc_page(ns, hdr, &resp[mode_pages_offset_4], 1326 + MODE_PAGE_INF_EXC_LEN); 1327 + if (res != SNTI_TRANSLATION_SUCCESS) 1328 + goto out; 1329 + 1330 + out: 1331 + return res; 1332 + } 1333 + 1334 + static inline int nvme_trans_get_blk_desc_len(u8 dbd, u8 llbaa) 1335 + { 1336 + if (dbd == MODE_SENSE_BLK_DESC_ENABLED) { 1337 + /* SPC-4: len = 8 x Num_of_descriptors if llbaa = 0, 16x if 1 */ 1338 + return 8 * (llbaa + 1) * MODE_SENSE_BLK_DESC_COUNT; 1339 + } else { 1340 + return 0; 1341 + } 1342 + } 1343 + 1344 + static int nvme_trans_mode_page_create(struct nvme_ns *ns, 1345 + struct sg_io_hdr *hdr, u8 *cmd, 1346 + u16 alloc_len, u8 cdb10, 1347 + int (*mode_page_fill_func) 1348 + (struct nvme_ns *, 1349 + struct sg_io_hdr *hdr, u8 *, int), 1350 + u16 mode_pages_tot_len) 1351 + { 1352 + int res = SNTI_TRANSLATION_SUCCESS; 1353 + int xfer_len; 1354 + u8 *response; 1355 + u8 dbd, llbaa; 1356 + u16 resp_size; 1357 + int mph_size; 1358 + u16 mode_pages_offset_1; 1359 + u16 blk_desc_len, blk_desc_offset, mode_data_length; 1360 + 1361 + dbd = GET_MODE_SENSE_DBD(cmd); 1362 + llbaa = GET_MODE_SENSE_LLBAA(cmd); 1363 + mph_size = GET_MODE_SENSE_MPH_SIZE(cdb10); 1364 + blk_desc_len = nvme_trans_get_blk_desc_len(dbd, llbaa); 1365 + 1366 + resp_size = mph_size + blk_desc_len + mode_pages_tot_len; 1367 + /* Refer spc4r34 Table 440 for calculation of Mode data Length field */ 1368 + mode_data_length = 3 + (3 * cdb10) + blk_desc_len + mode_pages_tot_len; 1369 + 1370 + blk_desc_offset = mph_size; 1371 + mode_pages_offset_1 = blk_desc_offset + blk_desc_len; 1372 + 1373 + response = kmalloc(resp_size, GFP_KERNEL); 1374 + if (response == NULL) { 1375 + res = -ENOMEM; 1376 + goto out_mem; 1377 + } 1378 + memset(response, 0, resp_size); 1379 + 1380 + res = nvme_trans_fill_mode_parm_hdr(&response[0], mph_size, cdb10, 1381 + llbaa, mode_data_length, blk_desc_len); 1382 + if (res != SNTI_TRANSLATION_SUCCESS) 1383 + goto out_free; 1384 + if (blk_desc_len > 0) { 1385 + res = nvme_trans_fill_blk_desc(ns, hdr, 1386 + &response[blk_desc_offset], 1387 + blk_desc_len, llbaa); 1388 + if (res != SNTI_TRANSLATION_SUCCESS) 1389 + goto out_free; 1390 + } 1391 + res = mode_page_fill_func(ns, hdr, &response[mode_pages_offset_1], 1392 + mode_pages_tot_len); 1393 + if (res != SNTI_TRANSLATION_SUCCESS) 1394 + goto out_free; 1395 + 1396 + xfer_len = min(alloc_len, resp_size); 1397 + res = nvme_trans_copy_to_user(hdr, response, xfer_len); 1398 + 1399 + out_free: 1400 + kfree(response); 1401 + out_mem: 1402 + return res; 1403 + } 1404 + 1405 + /* Read Capacity Helper Functions */ 1406 + 1407 + static void nvme_trans_fill_read_cap(u8 *response, struct nvme_id_ns *id_ns, 1408 + u8 cdb16) 1409 + { 1410 + u8 flbas; 1411 + u32 lba_length; 1412 + u64 rlba; 1413 + u8 prot_en; 1414 + u8 p_type_lut[4] = {0, 0, 1, 2}; 1415 + u64 tmp_rlba; 1416 + u32 tmp_rlba_32; 1417 + u32 tmp_len; 1418 + 1419 + flbas = (id_ns->flbas) & 0x0F; 1420 + lba_length = (1 << (id_ns->lbaf[flbas].ds)); 1421 + rlba = le64_to_cpup(&id_ns->nsze) - 1; 1422 + (id_ns->dps) ? (prot_en = 0x01) : (prot_en = 0); 1423 + 1424 + if (!cdb16) { 1425 + if (rlba > 0xFFFFFFFF) 1426 + rlba = 0xFFFFFFFF; 1427 + tmp_rlba_32 = cpu_to_be32(rlba); 1428 + tmp_len = cpu_to_be32(lba_length); 1429 + memcpy(response, &tmp_rlba_32, sizeof(u32)); 1430 + memcpy(&response[4], &tmp_len, sizeof(u32)); 1431 + } else { 1432 + tmp_rlba = cpu_to_be64(rlba); 1433 + tmp_len = cpu_to_be32(lba_length); 1434 + memcpy(response, &tmp_rlba, sizeof(u64)); 1435 + memcpy(&response[8], &tmp_len, sizeof(u32)); 1436 + response[12] = (p_type_lut[id_ns->dps & 0x3] << 1) | prot_en; 1437 + /* P_I_Exponent = 0x0 | LBPPBE = 0x0 */ 1438 + /* LBPME = 0 | LBPRZ = 0 | LALBA = 0x00 */ 1439 + /* Bytes 16-31 - Reserved */ 1440 + } 1441 + } 1442 + 1443 + /* Start Stop Unit Helper Functions */ 1444 + 1445 + static int nvme_trans_power_state(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1446 + u8 pc, u8 pcmod, u8 start) 1447 + { 1448 + int res = SNTI_TRANSLATION_SUCCESS; 1449 + int nvme_sc; 1450 + struct nvme_dev *dev = ns->dev; 1451 + dma_addr_t dma_addr; 1452 + void *mem; 1453 + struct nvme_id_ctrl *id_ctrl; 1454 + int lowest_pow_st; /* max npss = lowest power consumption */ 1455 + unsigned ps_desired = 0; 1456 + 1457 + /* NVMe Controller Identify */ 1458 + mem = dma_alloc_coherent(&dev->pci_dev->dev, 1459 + sizeof(struct nvme_id_ctrl), 1460 + &dma_addr, GFP_KERNEL); 1461 + if (mem == NULL) { 1462 + res = -ENOMEM; 1463 + goto out; 1464 + } 1465 + nvme_sc = nvme_identify(dev, 0, 1, dma_addr); 1466 + res = nvme_trans_status_code(hdr, nvme_sc); 1467 + if (res) 1468 + goto out_dma; 1469 + if (nvme_sc) { 1470 + res = nvme_sc; 1471 + goto out_dma; 1472 + } 1473 + id_ctrl = mem; 1474 + lowest_pow_st = id_ctrl->npss - 1; 1475 + 1476 + switch (pc) { 1477 + case NVME_POWER_STATE_START_VALID: 1478 + /* Action unspecified if POWER CONDITION MODIFIER != 0 */ 1479 + if (pcmod == 0 && start == 0x1) 1480 + ps_desired = POWER_STATE_0; 1481 + if (pcmod == 0 && start == 0x0) 1482 + ps_desired = lowest_pow_st; 1483 + break; 1484 + case NVME_POWER_STATE_ACTIVE: 1485 + /* Action unspecified if POWER CONDITION MODIFIER != 0 */ 1486 + if (pcmod == 0) 1487 + ps_desired = POWER_STATE_0; 1488 + break; 1489 + case NVME_POWER_STATE_IDLE: 1490 + /* Action unspecified if POWER CONDITION MODIFIER != [0,1,2] */ 1491 + /* min of desired state and (lps-1) because lps is STOP */ 1492 + if (pcmod == 0x0) 1493 + ps_desired = min(POWER_STATE_1, (lowest_pow_st - 1)); 1494 + else if (pcmod == 0x1) 1495 + ps_desired = min(POWER_STATE_2, (lowest_pow_st - 1)); 1496 + else if (pcmod == 0x2) 1497 + ps_desired = min(POWER_STATE_3, (lowest_pow_st - 1)); 1498 + break; 1499 + case NVME_POWER_STATE_STANDBY: 1500 + /* Action unspecified if POWER CONDITION MODIFIER != [0,1] */ 1501 + if (pcmod == 0x0) 1502 + ps_desired = max(0, (lowest_pow_st - 2)); 1503 + else if (pcmod == 0x1) 1504 + ps_desired = max(0, (lowest_pow_st - 1)); 1505 + break; 1506 + case NVME_POWER_STATE_LU_CONTROL: 1507 + default: 1508 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1509 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 1510 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1511 + break; 1512 + } 1513 + nvme_sc = nvme_set_features(dev, NVME_FEAT_POWER_MGMT, ps_desired, 0, 1514 + NULL); 1515 + res = nvme_trans_status_code(hdr, nvme_sc); 1516 + if (res) 1517 + goto out_dma; 1518 + if (nvme_sc) 1519 + res = nvme_sc; 1520 + out_dma: 1521 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem, 1522 + dma_addr); 1523 + out: 1524 + return res; 1525 + } 1526 + 1527 + /* Write Buffer Helper Functions */ 1528 + /* Also using this for Format Unit with hdr passed as NULL, and buffer_id, 0 */ 1529 + 1530 + static int nvme_trans_send_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1531 + u8 opcode, u32 tot_len, u32 offset, 1532 + u8 buffer_id) 1533 + { 1534 + int res = SNTI_TRANSLATION_SUCCESS; 1535 + int nvme_sc; 1536 + struct nvme_dev *dev = ns->dev; 1537 + struct nvme_command c; 1538 + struct nvme_iod *iod = NULL; 1539 + unsigned length; 1540 + 1541 + memset(&c, 0, sizeof(c)); 1542 + c.common.opcode = opcode; 1543 + if (opcode == nvme_admin_download_fw) { 1544 + if (hdr->iovec_count > 0) { 1545 + /* Assuming SGL is not allowed for this command */ 1546 + res = nvme_trans_completion(hdr, 1547 + SAM_STAT_CHECK_CONDITION, 1548 + ILLEGAL_REQUEST, 1549 + SCSI_ASC_INVALID_CDB, 1550 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1551 + goto out; 1552 + } 1553 + iod = nvme_map_user_pages(dev, DMA_TO_DEVICE, 1554 + (unsigned long)hdr->dxferp, tot_len); 1555 + if (IS_ERR(iod)) { 1556 + res = PTR_ERR(iod); 1557 + goto out; 1558 + } 1559 + length = nvme_setup_prps(dev, &c.common, iod, tot_len, 1560 + GFP_KERNEL); 1561 + if (length != tot_len) { 1562 + res = -ENOMEM; 1563 + goto out_unmap; 1564 + } 1565 + 1566 + c.dlfw.numd = (tot_len/BYTES_TO_DWORDS) - 1; 1567 + c.dlfw.offset = offset/BYTES_TO_DWORDS; 1568 + } else if (opcode == nvme_admin_activate_fw) { 1569 + c.common.cdw10[0] = buffer_id; 1570 + /* AA=01b Replace & activate at reset */ 1571 + c.common.cdw10[0] |= 0x00000008; 1572 + } 1573 + 1574 + nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL); 1575 + res = nvme_trans_status_code(hdr, nvme_sc); 1576 + if (res) 1577 + goto out_unmap; 1578 + if (nvme_sc) 1579 + res = nvme_sc; 1580 + 1581 + out_unmap: 1582 + if (opcode == nvme_admin_download_fw) { 1583 + nvme_unmap_user_pages(dev, DMA_TO_DEVICE, iod); 1584 + nvme_free_iod(dev, iod); 1585 + } 1586 + out: 1587 + return res; 1588 + } 1589 + 1590 + /* Mode Select Helper Functions */ 1591 + 1592 + static inline void nvme_trans_modesel_get_bd_len(u8 *parm_list, u8 cdb10, 1593 + u16 *bd_len, u8 *llbaa) 1594 + { 1595 + if (cdb10) { 1596 + /* 10 Byte CDB */ 1597 + *bd_len = (parm_list[MODE_SELECT_10_BD_OFFSET] << 8) + 1598 + parm_list[MODE_SELECT_10_BD_OFFSET + 1]; 1599 + *llbaa = parm_list[MODE_SELECT_10_LLBAA_OFFSET] && 1600 + MODE_SELECT_10_LLBAA_MASK; 1601 + } else { 1602 + /* 6 Byte CDB */ 1603 + *bd_len = parm_list[MODE_SELECT_6_BD_OFFSET]; 1604 + } 1605 + } 1606 + 1607 + static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list, 1608 + u16 idx, u16 bd_len, u8 llbaa) 1609 + { 1610 + u16 bd_num; 1611 + 1612 + bd_num = bd_len / ((llbaa == 0) ? 1613 + SHORT_DESC_BLOCK : LONG_DESC_BLOCK); 1614 + /* Store block descriptor info if a FORMAT UNIT comes later */ 1615 + /* TODO Saving 1st BD info; what to do if multiple BD received? */ 1616 + if (llbaa == 0) { 1617 + /* Standard Block Descriptor - spc4r34 7.5.5.1 */ 1618 + ns->mode_select_num_blocks = 1619 + (parm_list[idx + 1] << 16) + 1620 + (parm_list[idx + 2] << 8) + 1621 + (parm_list[idx + 3]); 1622 + 1623 + ns->mode_select_block_len = 1624 + (parm_list[idx + 5] << 16) + 1625 + (parm_list[idx + 6] << 8) + 1626 + (parm_list[idx + 7]); 1627 + } else { 1628 + /* Long LBA Block Descriptor - sbc3r27 6.4.2.3 */ 1629 + ns->mode_select_num_blocks = 1630 + (((u64)parm_list[idx + 0]) << 56) + 1631 + (((u64)parm_list[idx + 1]) << 48) + 1632 + (((u64)parm_list[idx + 2]) << 40) + 1633 + (((u64)parm_list[idx + 3]) << 32) + 1634 + (((u64)parm_list[idx + 4]) << 24) + 1635 + (((u64)parm_list[idx + 5]) << 16) + 1636 + (((u64)parm_list[idx + 6]) << 8) + 1637 + ((u64)parm_list[idx + 7]); 1638 + 1639 + ns->mode_select_block_len = 1640 + (parm_list[idx + 12] << 24) + 1641 + (parm_list[idx + 13] << 16) + 1642 + (parm_list[idx + 14] << 8) + 1643 + (parm_list[idx + 15]); 1644 + } 1645 + } 1646 + 1647 + static u16 nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1648 + u8 *mode_page, u8 page_code) 1649 + { 1650 + int res = SNTI_TRANSLATION_SUCCESS; 1651 + int nvme_sc; 1652 + struct nvme_dev *dev = ns->dev; 1653 + unsigned dword11; 1654 + 1655 + switch (page_code) { 1656 + case MODE_PAGE_CACHING: 1657 + dword11 = ((mode_page[2] & CACHING_MODE_PAGE_WCE_MASK) ? 1 : 0); 1658 + nvme_sc = nvme_set_features(dev, NVME_FEAT_VOLATILE_WC, dword11, 1659 + 0, NULL); 1660 + res = nvme_trans_status_code(hdr, nvme_sc); 1661 + if (res) 1662 + break; 1663 + if (nvme_sc) { 1664 + res = nvme_sc; 1665 + break; 1666 + } 1667 + break; 1668 + case MODE_PAGE_CONTROL: 1669 + break; 1670 + case MODE_PAGE_POWER_CONDITION: 1671 + /* Verify the OS is not trying to set timers */ 1672 + if ((mode_page[2] & 0x01) != 0 || (mode_page[3] & 0x0F) != 0) { 1673 + res = nvme_trans_completion(hdr, 1674 + SAM_STAT_CHECK_CONDITION, 1675 + ILLEGAL_REQUEST, 1676 + SCSI_ASC_INVALID_PARAMETER, 1677 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1678 + if (!res) 1679 + res = SNTI_INTERNAL_ERROR; 1680 + break; 1681 + } 1682 + break; 1683 + default: 1684 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1685 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 1686 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1687 + if (!res) 1688 + res = SNTI_INTERNAL_ERROR; 1689 + break; 1690 + } 1691 + 1692 + return res; 1693 + } 1694 + 1695 + static int nvme_trans_modesel_data(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1696 + u8 *cmd, u16 parm_list_len, u8 pf, 1697 + u8 sp, u8 cdb10) 1698 + { 1699 + int res = SNTI_TRANSLATION_SUCCESS; 1700 + u8 *parm_list; 1701 + u16 bd_len; 1702 + u8 llbaa = 0; 1703 + u16 index, saved_index; 1704 + u8 page_code; 1705 + u16 mp_size; 1706 + 1707 + /* Get parm list from data-in/out buffer */ 1708 + parm_list = kmalloc(parm_list_len, GFP_KERNEL); 1709 + if (parm_list == NULL) { 1710 + res = -ENOMEM; 1711 + goto out; 1712 + } 1713 + 1714 + res = nvme_trans_copy_from_user(hdr, parm_list, parm_list_len); 1715 + if (res != SNTI_TRANSLATION_SUCCESS) 1716 + goto out_mem; 1717 + 1718 + nvme_trans_modesel_get_bd_len(parm_list, cdb10, &bd_len, &llbaa); 1719 + index = (cdb10) ? (MODE_SELECT_10_MPH_SIZE) : (MODE_SELECT_6_MPH_SIZE); 1720 + 1721 + if (bd_len != 0) { 1722 + /* Block Descriptors present, parse */ 1723 + nvme_trans_modesel_save_bd(ns, parm_list, index, bd_len, llbaa); 1724 + index += bd_len; 1725 + } 1726 + saved_index = index; 1727 + 1728 + /* Multiple mode pages may be present; iterate through all */ 1729 + /* In 1st Iteration, don't do NVME Command, only check for CDB errors */ 1730 + do { 1731 + page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK; 1732 + mp_size = parm_list[index + 1] + 2; 1733 + if ((page_code != MODE_PAGE_CACHING) && 1734 + (page_code != MODE_PAGE_CONTROL) && 1735 + (page_code != MODE_PAGE_POWER_CONDITION)) { 1736 + res = nvme_trans_completion(hdr, 1737 + SAM_STAT_CHECK_CONDITION, 1738 + ILLEGAL_REQUEST, 1739 + SCSI_ASC_INVALID_CDB, 1740 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1741 + goto out_mem; 1742 + } 1743 + index += mp_size; 1744 + } while (index < parm_list_len); 1745 + 1746 + /* In 2nd Iteration, do the NVME Commands */ 1747 + index = saved_index; 1748 + do { 1749 + page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK; 1750 + mp_size = parm_list[index + 1] + 2; 1751 + res = nvme_trans_modesel_get_mp(ns, hdr, &parm_list[index], 1752 + page_code); 1753 + if (res != SNTI_TRANSLATION_SUCCESS) 1754 + break; 1755 + index += mp_size; 1756 + } while (index < parm_list_len); 1757 + 1758 + out_mem: 1759 + kfree(parm_list); 1760 + out: 1761 + return res; 1762 + } 1763 + 1764 + /* Format Unit Helper Functions */ 1765 + 1766 + static int nvme_trans_fmt_set_blk_size_count(struct nvme_ns *ns, 1767 + struct sg_io_hdr *hdr) 1768 + { 1769 + int res = SNTI_TRANSLATION_SUCCESS; 1770 + int nvme_sc; 1771 + struct nvme_dev *dev = ns->dev; 1772 + dma_addr_t dma_addr; 1773 + void *mem; 1774 + struct nvme_id_ns *id_ns; 1775 + u8 flbas; 1776 + 1777 + /* 1778 + * SCSI Expects a MODE SELECT would have been issued prior to 1779 + * a FORMAT UNIT, and the block size and number would be used 1780 + * from the block descriptor in it. If a MODE SELECT had not 1781 + * been issued, FORMAT shall use the current values for both. 1782 + */ 1783 + 1784 + if (ns->mode_select_num_blocks == 0 || ns->mode_select_block_len == 0) { 1785 + mem = dma_alloc_coherent(&dev->pci_dev->dev, 1786 + sizeof(struct nvme_id_ns), &dma_addr, GFP_KERNEL); 1787 + if (mem == NULL) { 1788 + res = -ENOMEM; 1789 + goto out; 1790 + } 1791 + /* nvme ns identify */ 1792 + nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); 1793 + res = nvme_trans_status_code(hdr, nvme_sc); 1794 + if (res) 1795 + goto out_dma; 1796 + if (nvme_sc) { 1797 + res = nvme_sc; 1798 + goto out_dma; 1799 + } 1800 + id_ns = mem; 1801 + 1802 + if (ns->mode_select_num_blocks == 0) 1803 + ns->mode_select_num_blocks = id_ns->ncap; 1804 + if (ns->mode_select_block_len == 0) { 1805 + flbas = (id_ns->flbas) & 0x0F; 1806 + ns->mode_select_block_len = 1807 + (1 << (id_ns->lbaf[flbas].ds)); 1808 + } 1809 + out_dma: 1810 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 1811 + mem, dma_addr); 1812 + } 1813 + out: 1814 + return res; 1815 + } 1816 + 1817 + static int nvme_trans_fmt_get_parm_header(struct sg_io_hdr *hdr, u8 len, 1818 + u8 format_prot_info, u8 *nvme_pf_code) 1819 + { 1820 + int res = SNTI_TRANSLATION_SUCCESS; 1821 + u8 *parm_list; 1822 + u8 pf_usage, pf_code; 1823 + 1824 + parm_list = kmalloc(len, GFP_KERNEL); 1825 + if (parm_list == NULL) { 1826 + res = -ENOMEM; 1827 + goto out; 1828 + } 1829 + res = nvme_trans_copy_from_user(hdr, parm_list, len); 1830 + if (res != SNTI_TRANSLATION_SUCCESS) 1831 + goto out_mem; 1832 + 1833 + if ((parm_list[FORMAT_UNIT_IMMED_OFFSET] & 1834 + FORMAT_UNIT_IMMED_MASK) != 0) { 1835 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1836 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 1837 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1838 + goto out_mem; 1839 + } 1840 + 1841 + if (len == FORMAT_UNIT_LONG_PARM_LIST_LEN && 1842 + (parm_list[FORMAT_UNIT_PROT_INT_OFFSET] & 0x0F) != 0) { 1843 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1844 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 1845 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1846 + goto out_mem; 1847 + } 1848 + pf_usage = parm_list[FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET] & 1849 + FORMAT_UNIT_PROT_FIELD_USAGE_MASK; 1850 + pf_code = (pf_usage << 2) | format_prot_info; 1851 + switch (pf_code) { 1852 + case 0: 1853 + *nvme_pf_code = 0; 1854 + break; 1855 + case 2: 1856 + *nvme_pf_code = 1; 1857 + break; 1858 + case 3: 1859 + *nvme_pf_code = 2; 1860 + break; 1861 + case 7: 1862 + *nvme_pf_code = 3; 1863 + break; 1864 + default: 1865 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1866 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 1867 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1868 + break; 1869 + } 1870 + 1871 + out_mem: 1872 + kfree(parm_list); 1873 + out: 1874 + return res; 1875 + } 1876 + 1877 + static int nvme_trans_fmt_send_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr, 1878 + u8 prot_info) 1879 + { 1880 + int res = SNTI_TRANSLATION_SUCCESS; 1881 + int nvme_sc; 1882 + struct nvme_dev *dev = ns->dev; 1883 + dma_addr_t dma_addr; 1884 + void *mem; 1885 + struct nvme_id_ns *id_ns; 1886 + u8 i; 1887 + u8 flbas, nlbaf; 1888 + u8 selected_lbaf = 0xFF; 1889 + u32 cdw10 = 0; 1890 + struct nvme_command c; 1891 + 1892 + /* Loop thru LBAF's in id_ns to match reqd lbaf, put in cdw10 */ 1893 + mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 1894 + &dma_addr, GFP_KERNEL); 1895 + if (mem == NULL) { 1896 + res = -ENOMEM; 1897 + goto out; 1898 + } 1899 + /* nvme ns identify */ 1900 + nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); 1901 + res = nvme_trans_status_code(hdr, nvme_sc); 1902 + if (res) 1903 + goto out_dma; 1904 + if (nvme_sc) { 1905 + res = nvme_sc; 1906 + goto out_dma; 1907 + } 1908 + id_ns = mem; 1909 + flbas = (id_ns->flbas) & 0x0F; 1910 + nlbaf = id_ns->nlbaf; 1911 + 1912 + for (i = 0; i < nlbaf; i++) { 1913 + if (ns->mode_select_block_len == (1 << (id_ns->lbaf[i].ds))) { 1914 + selected_lbaf = i; 1915 + break; 1916 + } 1917 + } 1918 + if (selected_lbaf > 0x0F) { 1919 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1920 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER, 1921 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1922 + } 1923 + if (ns->mode_select_num_blocks != id_ns->ncap) { 1924 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 1925 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER, 1926 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 1927 + } 1928 + 1929 + cdw10 |= prot_info << 5; 1930 + cdw10 |= selected_lbaf & 0x0F; 1931 + memset(&c, 0, sizeof(c)); 1932 + c.format.opcode = nvme_admin_format_nvm; 1933 + c.format.nsid = ns->ns_id; 1934 + c.format.cdw10 = cpu_to_le32(cdw10); 1935 + 1936 + nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL); 1937 + res = nvme_trans_status_code(hdr, nvme_sc); 1938 + if (res) 1939 + goto out_dma; 1940 + if (nvme_sc) 1941 + res = nvme_sc; 1942 + 1943 + out_dma: 1944 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem, 1945 + dma_addr); 1946 + out: 1947 + return res; 1948 + } 1949 + 1950 + /* Read/Write Helper Functions */ 1951 + 1952 + static inline void nvme_trans_get_io_cdb6(u8 *cmd, 1953 + struct nvme_trans_io_cdb *cdb_info) 1954 + { 1955 + cdb_info->fua = 0; 1956 + cdb_info->prot_info = 0; 1957 + cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_6_CDB_LBA_OFFSET) & 1958 + IO_6_CDB_LBA_MASK; 1959 + cdb_info->xfer_len = GET_U8_FROM_CDB(cmd, IO_6_CDB_TX_LEN_OFFSET); 1960 + 1961 + /* sbc3r27 sec 5.32 - TRANSFER LEN of 0 implies a 256 Block transfer */ 1962 + if (cdb_info->xfer_len == 0) 1963 + cdb_info->xfer_len = IO_6_DEFAULT_TX_LEN; 1964 + } 1965 + 1966 + static inline void nvme_trans_get_io_cdb10(u8 *cmd, 1967 + struct nvme_trans_io_cdb *cdb_info) 1968 + { 1969 + cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_10_CDB_FUA_OFFSET) & 1970 + IO_CDB_FUA_MASK; 1971 + cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_10_CDB_WP_OFFSET) & 1972 + IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT; 1973 + cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_10_CDB_LBA_OFFSET); 1974 + cdb_info->xfer_len = GET_U16_FROM_CDB(cmd, IO_10_CDB_TX_LEN_OFFSET); 1975 + } 1976 + 1977 + static inline void nvme_trans_get_io_cdb12(u8 *cmd, 1978 + struct nvme_trans_io_cdb *cdb_info) 1979 + { 1980 + cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_12_CDB_FUA_OFFSET) & 1981 + IO_CDB_FUA_MASK; 1982 + cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_12_CDB_WP_OFFSET) & 1983 + IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT; 1984 + cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_12_CDB_LBA_OFFSET); 1985 + cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_12_CDB_TX_LEN_OFFSET); 1986 + } 1987 + 1988 + static inline void nvme_trans_get_io_cdb16(u8 *cmd, 1989 + struct nvme_trans_io_cdb *cdb_info) 1990 + { 1991 + cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_16_CDB_FUA_OFFSET) & 1992 + IO_CDB_FUA_MASK; 1993 + cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_16_CDB_WP_OFFSET) & 1994 + IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT; 1995 + cdb_info->lba = GET_U64_FROM_CDB(cmd, IO_16_CDB_LBA_OFFSET); 1996 + cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_16_CDB_TX_LEN_OFFSET); 1997 + } 1998 + 1999 + static inline u32 nvme_trans_io_get_num_cmds(struct sg_io_hdr *hdr, 2000 + struct nvme_trans_io_cdb *cdb_info, 2001 + u32 max_blocks) 2002 + { 2003 + /* If using iovecs, send one nvme command per vector */ 2004 + if (hdr->iovec_count > 0) 2005 + return hdr->iovec_count; 2006 + else if (cdb_info->xfer_len > max_blocks) 2007 + return ((cdb_info->xfer_len - 1) / max_blocks) + 1; 2008 + else 2009 + return 1; 2010 + } 2011 + 2012 + static u16 nvme_trans_io_get_control(struct nvme_ns *ns, 2013 + struct nvme_trans_io_cdb *cdb_info) 2014 + { 2015 + u16 control = 0; 2016 + 2017 + /* When Protection information support is added, implement here */ 2018 + 2019 + if (cdb_info->fua > 0) 2020 + control |= NVME_RW_FUA; 2021 + 2022 + return control; 2023 + } 2024 + 2025 + static int nvme_trans_do_nvme_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2026 + struct nvme_trans_io_cdb *cdb_info, u8 is_write) 2027 + { 2028 + int res = SNTI_TRANSLATION_SUCCESS; 2029 + int nvme_sc; 2030 + struct nvme_dev *dev = ns->dev; 2031 + struct nvme_queue *nvmeq = get_nvmeq(ns->dev); 2032 + u32 num_cmds; 2033 + struct nvme_iod *iod; 2034 + u64 unit_len; 2035 + u64 unit_num_blocks; /* Number of blocks to xfer in each nvme cmd */ 2036 + u32 retcode; 2037 + u32 i = 0; 2038 + u64 nvme_offset = 0; 2039 + void *next_mapping_addr; 2040 + struct nvme_command c; 2041 + u8 opcode = (is_write ? nvme_cmd_write : nvme_cmd_read); 2042 + u16 control; 2043 + u32 max_blocks = (dev->max_hw_sectors << 9) >> ns->lba_shift; 2044 + 2045 + num_cmds = nvme_trans_io_get_num_cmds(hdr, cdb_info, max_blocks); 2046 + 2047 + /* 2048 + * This loop handles two cases. 2049 + * First, when an SGL is used in the form of an iovec list: 2050 + * - Use iov_base as the next mapping address for the nvme command_id 2051 + * - Use iov_len as the data transfer length for the command. 2052 + * Second, when we have a single buffer 2053 + * - If larger than max_blocks, split into chunks, offset 2054 + * each nvme command accordingly. 2055 + */ 2056 + for (i = 0; i < num_cmds; i++) { 2057 + memset(&c, 0, sizeof(c)); 2058 + if (hdr->iovec_count > 0) { 2059 + struct sg_iovec *sgl = hdr->dxferp; 2060 + 2061 + unit_len = sgl[i].iov_len; 2062 + unit_num_blocks = unit_len >> ns->lba_shift; 2063 + next_mapping_addr = sgl[i].iov_base; 2064 + } else { 2065 + unit_num_blocks = min((u64)max_blocks, 2066 + (cdb_info->xfer_len - nvme_offset)); 2067 + unit_len = unit_num_blocks << ns->lba_shift; 2068 + next_mapping_addr = hdr->dxferp + 2069 + ((1 << ns->lba_shift) * nvme_offset); 2070 + } 2071 + 2072 + c.rw.opcode = opcode; 2073 + c.rw.nsid = cpu_to_le32(ns->ns_id); 2074 + c.rw.slba = cpu_to_le64(cdb_info->lba + nvme_offset); 2075 + c.rw.length = cpu_to_le16(unit_num_blocks - 1); 2076 + control = nvme_trans_io_get_control(ns, cdb_info); 2077 + c.rw.control = cpu_to_le16(control); 2078 + 2079 + iod = nvme_map_user_pages(dev, 2080 + (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, 2081 + (unsigned long)next_mapping_addr, unit_len); 2082 + if (IS_ERR(iod)) { 2083 + res = PTR_ERR(iod); 2084 + goto out; 2085 + } 2086 + retcode = nvme_setup_prps(dev, &c.common, iod, unit_len, 2087 + GFP_KERNEL); 2088 + if (retcode != unit_len) { 2089 + nvme_unmap_user_pages(dev, 2090 + (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, 2091 + iod); 2092 + nvme_free_iod(dev, iod); 2093 + res = -ENOMEM; 2094 + goto out; 2095 + } 2096 + 2097 + nvme_offset += unit_num_blocks; 2098 + 2099 + nvmeq = get_nvmeq(dev); 2100 + /* 2101 + * Since nvme_submit_sync_cmd sleeps, we can't keep 2102 + * preemption disabled. We may be preempted at any 2103 + * point, and be rescheduled to a different CPU. That 2104 + * will cause cacheline bouncing, but no additional 2105 + * races since q_lock already protects against other 2106 + * CPUs. 2107 + */ 2108 + put_nvmeq(nvmeq); 2109 + nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, 2110 + NVME_IO_TIMEOUT); 2111 + if (nvme_sc != NVME_SC_SUCCESS) { 2112 + nvme_unmap_user_pages(dev, 2113 + (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, 2114 + iod); 2115 + nvme_free_iod(dev, iod); 2116 + res = nvme_trans_status_code(hdr, nvme_sc); 2117 + goto out; 2118 + } 2119 + nvme_unmap_user_pages(dev, 2120 + (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, 2121 + iod); 2122 + nvme_free_iod(dev, iod); 2123 + } 2124 + res = nvme_trans_status_code(hdr, NVME_SC_SUCCESS); 2125 + 2126 + out: 2127 + return res; 2128 + } 2129 + 2130 + 2131 + /* SCSI Command Translation Functions */ 2132 + 2133 + static int nvme_trans_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, u8 is_write, 2134 + u8 *cmd) 2135 + { 2136 + int res = SNTI_TRANSLATION_SUCCESS; 2137 + struct nvme_trans_io_cdb cdb_info; 2138 + u8 opcode = cmd[0]; 2139 + u64 xfer_bytes; 2140 + u64 sum_iov_len = 0; 2141 + struct sg_iovec *sgl; 2142 + int i; 2143 + 2144 + /* Extract Fields from CDB */ 2145 + switch (opcode) { 2146 + case WRITE_6: 2147 + case READ_6: 2148 + nvme_trans_get_io_cdb6(cmd, &cdb_info); 2149 + break; 2150 + case WRITE_10: 2151 + case READ_10: 2152 + nvme_trans_get_io_cdb10(cmd, &cdb_info); 2153 + break; 2154 + case WRITE_12: 2155 + case READ_12: 2156 + nvme_trans_get_io_cdb12(cmd, &cdb_info); 2157 + break; 2158 + case WRITE_16: 2159 + case READ_16: 2160 + nvme_trans_get_io_cdb16(cmd, &cdb_info); 2161 + break; 2162 + default: 2163 + /* Will never really reach here */ 2164 + res = SNTI_INTERNAL_ERROR; 2165 + goto out; 2166 + } 2167 + 2168 + /* Calculate total length of transfer (in bytes) */ 2169 + if (hdr->iovec_count > 0) { 2170 + sgl = hdr->dxferp; 2171 + for (i = 0; i < hdr->iovec_count; i++) { 2172 + sum_iov_len += sgl[i].iov_len; 2173 + /* IO vector sizes should be multiples of block size */ 2174 + if (sgl[i].iov_len % (1 << ns->lba_shift) != 0) { 2175 + res = nvme_trans_completion(hdr, 2176 + SAM_STAT_CHECK_CONDITION, 2177 + ILLEGAL_REQUEST, 2178 + SCSI_ASC_INVALID_PARAMETER, 2179 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2180 + goto out; 2181 + } 2182 + } 2183 + } else { 2184 + sum_iov_len = hdr->dxfer_len; 2185 + } 2186 + 2187 + /* As Per sg ioctl howto, if the lengths differ, use the lower one */ 2188 + xfer_bytes = min(((u64)hdr->dxfer_len), sum_iov_len); 2189 + 2190 + /* If block count and actual data buffer size dont match, error out */ 2191 + if (xfer_bytes != (cdb_info.xfer_len << ns->lba_shift)) { 2192 + res = -EINVAL; 2193 + goto out; 2194 + } 2195 + 2196 + /* Check for 0 length transfer - it is not illegal */ 2197 + if (cdb_info.xfer_len == 0) 2198 + goto out; 2199 + 2200 + /* Send NVMe IO Command(s) */ 2201 + res = nvme_trans_do_nvme_io(ns, hdr, &cdb_info, is_write); 2202 + if (res != SNTI_TRANSLATION_SUCCESS) 2203 + goto out; 2204 + 2205 + out: 2206 + return res; 2207 + } 2208 + 2209 + static int nvme_trans_inquiry(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2210 + u8 *cmd) 2211 + { 2212 + int res = SNTI_TRANSLATION_SUCCESS; 2213 + u8 evpd; 2214 + u8 page_code; 2215 + int alloc_len; 2216 + u8 *inq_response; 2217 + 2218 + evpd = GET_INQ_EVPD_BIT(cmd); 2219 + page_code = GET_INQ_PAGE_CODE(cmd); 2220 + alloc_len = GET_INQ_ALLOC_LENGTH(cmd); 2221 + 2222 + inq_response = kmalloc(STANDARD_INQUIRY_LENGTH, GFP_KERNEL); 2223 + if (inq_response == NULL) { 2224 + res = -ENOMEM; 2225 + goto out_mem; 2226 + } 2227 + 2228 + if (evpd == 0) { 2229 + if (page_code == INQ_STANDARD_INQUIRY_PAGE) { 2230 + res = nvme_trans_standard_inquiry_page(ns, hdr, 2231 + inq_response, alloc_len); 2232 + } else { 2233 + res = nvme_trans_completion(hdr, 2234 + SAM_STAT_CHECK_CONDITION, 2235 + ILLEGAL_REQUEST, 2236 + SCSI_ASC_INVALID_CDB, 2237 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2238 + } 2239 + } else { 2240 + switch (page_code) { 2241 + case VPD_SUPPORTED_PAGES: 2242 + res = nvme_trans_supported_vpd_pages(ns, hdr, 2243 + inq_response, alloc_len); 2244 + break; 2245 + case VPD_SERIAL_NUMBER: 2246 + res = nvme_trans_unit_serial_page(ns, hdr, inq_response, 2247 + alloc_len); 2248 + break; 2249 + case VPD_DEVICE_IDENTIFIERS: 2250 + res = nvme_trans_device_id_page(ns, hdr, inq_response, 2251 + alloc_len); 2252 + break; 2253 + case VPD_EXTENDED_INQUIRY: 2254 + res = nvme_trans_ext_inq_page(ns, hdr, alloc_len); 2255 + break; 2256 + case VPD_BLOCK_DEV_CHARACTERISTICS: 2257 + res = nvme_trans_bdev_char_page(ns, hdr, alloc_len); 2258 + break; 2259 + default: 2260 + res = nvme_trans_completion(hdr, 2261 + SAM_STAT_CHECK_CONDITION, 2262 + ILLEGAL_REQUEST, 2263 + SCSI_ASC_INVALID_CDB, 2264 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2265 + break; 2266 + } 2267 + } 2268 + kfree(inq_response); 2269 + out_mem: 2270 + return res; 2271 + } 2272 + 2273 + static int nvme_trans_log_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2274 + u8 *cmd) 2275 + { 2276 + int res = SNTI_TRANSLATION_SUCCESS; 2277 + u16 alloc_len; 2278 + u8 sp; 2279 + u8 pc; 2280 + u8 page_code; 2281 + 2282 + sp = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_SP_OFFSET); 2283 + if (sp != LOG_SENSE_CDB_SP_NOT_ENABLED) { 2284 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2285 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2286 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2287 + goto out; 2288 + } 2289 + pc = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_PC_OFFSET); 2290 + page_code = pc & LOG_SENSE_CDB_PAGE_CODE_MASK; 2291 + pc = (pc & LOG_SENSE_CDB_PC_MASK) >> LOG_SENSE_CDB_PC_SHIFT; 2292 + if (pc != LOG_SENSE_CDB_PC_CUMULATIVE_VALUES) { 2293 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2294 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2295 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2296 + goto out; 2297 + } 2298 + alloc_len = GET_U16_FROM_CDB(cmd, LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET); 2299 + switch (page_code) { 2300 + case LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE: 2301 + res = nvme_trans_log_supp_pages(ns, hdr, alloc_len); 2302 + break; 2303 + case LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE: 2304 + res = nvme_trans_log_info_exceptions(ns, hdr, alloc_len); 2305 + break; 2306 + case LOG_PAGE_TEMPERATURE_PAGE: 2307 + res = nvme_trans_log_temperature(ns, hdr, alloc_len); 2308 + break; 2309 + default: 2310 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2311 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2312 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2313 + break; 2314 + } 2315 + 2316 + out: 2317 + return res; 2318 + } 2319 + 2320 + static int nvme_trans_mode_select(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2321 + u8 *cmd) 2322 + { 2323 + int res = SNTI_TRANSLATION_SUCCESS; 2324 + u8 cdb10 = 0; 2325 + u16 parm_list_len; 2326 + u8 page_format; 2327 + u8 save_pages; 2328 + 2329 + page_format = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_PAGE_FORMAT_OFFSET); 2330 + page_format &= MODE_SELECT_CDB_PAGE_FORMAT_MASK; 2331 + 2332 + save_pages = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_SAVE_PAGES_OFFSET); 2333 + save_pages &= MODE_SELECT_CDB_SAVE_PAGES_MASK; 2334 + 2335 + if (GET_OPCODE(cmd) == MODE_SELECT) { 2336 + parm_list_len = GET_U8_FROM_CDB(cmd, 2337 + MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET); 2338 + } else { 2339 + parm_list_len = GET_U16_FROM_CDB(cmd, 2340 + MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET); 2341 + cdb10 = 1; 2342 + } 2343 + 2344 + if (parm_list_len != 0) { 2345 + /* 2346 + * According to SPC-4 r24, a paramter list length field of 0 2347 + * shall not be considered an error 2348 + */ 2349 + res = nvme_trans_modesel_data(ns, hdr, cmd, parm_list_len, 2350 + page_format, save_pages, cdb10); 2351 + } 2352 + 2353 + return res; 2354 + } 2355 + 2356 + static int nvme_trans_mode_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2357 + u8 *cmd) 2358 + { 2359 + int res = SNTI_TRANSLATION_SUCCESS; 2360 + u16 alloc_len; 2361 + u8 cdb10 = 0; 2362 + u8 page_code; 2363 + u8 pc; 2364 + 2365 + if (GET_OPCODE(cmd) == MODE_SENSE) { 2366 + alloc_len = GET_U8_FROM_CDB(cmd, MODE_SENSE6_ALLOC_LEN_OFFSET); 2367 + } else { 2368 + alloc_len = GET_U16_FROM_CDB(cmd, 2369 + MODE_SENSE10_ALLOC_LEN_OFFSET); 2370 + cdb10 = 1; 2371 + } 2372 + 2373 + pc = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CONTROL_OFFSET) & 2374 + MODE_SENSE_PAGE_CONTROL_MASK; 2375 + if (pc != MODE_SENSE_PC_CURRENT_VALUES) { 2376 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2377 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2378 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2379 + goto out; 2380 + } 2381 + 2382 + page_code = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CODE_OFFSET) & 2383 + MODE_SENSE_PAGE_CODE_MASK; 2384 + switch (page_code) { 2385 + case MODE_PAGE_CACHING: 2386 + res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, 2387 + cdb10, 2388 + &nvme_trans_fill_caching_page, 2389 + MODE_PAGE_CACHING_LEN); 2390 + break; 2391 + case MODE_PAGE_CONTROL: 2392 + res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, 2393 + cdb10, 2394 + &nvme_trans_fill_control_page, 2395 + MODE_PAGE_CONTROL_LEN); 2396 + break; 2397 + case MODE_PAGE_POWER_CONDITION: 2398 + res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, 2399 + cdb10, 2400 + &nvme_trans_fill_pow_cnd_page, 2401 + MODE_PAGE_POW_CND_LEN); 2402 + break; 2403 + case MODE_PAGE_INFO_EXCEP: 2404 + res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, 2405 + cdb10, 2406 + &nvme_trans_fill_inf_exc_page, 2407 + MODE_PAGE_INF_EXC_LEN); 2408 + break; 2409 + case MODE_PAGE_RETURN_ALL: 2410 + res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, 2411 + cdb10, 2412 + &nvme_trans_fill_all_pages, 2413 + MODE_PAGE_ALL_LEN); 2414 + break; 2415 + default: 2416 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2417 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2418 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2419 + break; 2420 + } 2421 + 2422 + out: 2423 + return res; 2424 + } 2425 + 2426 + static int nvme_trans_read_capacity(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2427 + u8 *cmd) 2428 + { 2429 + int res = SNTI_TRANSLATION_SUCCESS; 2430 + int nvme_sc; 2431 + u32 alloc_len = READ_CAP_10_RESP_SIZE; 2432 + u32 resp_size = READ_CAP_10_RESP_SIZE; 2433 + u32 xfer_len; 2434 + u8 cdb16; 2435 + struct nvme_dev *dev = ns->dev; 2436 + dma_addr_t dma_addr; 2437 + void *mem; 2438 + struct nvme_id_ns *id_ns; 2439 + u8 *response; 2440 + 2441 + cdb16 = IS_READ_CAP_16(cmd); 2442 + if (cdb16) { 2443 + alloc_len = GET_READ_CAP_16_ALLOC_LENGTH(cmd); 2444 + resp_size = READ_CAP_16_RESP_SIZE; 2445 + } 2446 + 2447 + mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), 2448 + &dma_addr, GFP_KERNEL); 2449 + if (mem == NULL) { 2450 + res = -ENOMEM; 2451 + goto out; 2452 + } 2453 + /* nvme ns identify */ 2454 + nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); 2455 + res = nvme_trans_status_code(hdr, nvme_sc); 2456 + if (res) 2457 + goto out_dma; 2458 + if (nvme_sc) { 2459 + res = nvme_sc; 2460 + goto out_dma; 2461 + } 2462 + id_ns = mem; 2463 + 2464 + response = kmalloc(resp_size, GFP_KERNEL); 2465 + if (response == NULL) { 2466 + res = -ENOMEM; 2467 + goto out_dma; 2468 + } 2469 + memset(response, 0, resp_size); 2470 + nvme_trans_fill_read_cap(response, id_ns, cdb16); 2471 + 2472 + xfer_len = min(alloc_len, resp_size); 2473 + res = nvme_trans_copy_to_user(hdr, response, xfer_len); 2474 + 2475 + kfree(response); 2476 + out_dma: 2477 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem, 2478 + dma_addr); 2479 + out: 2480 + return res; 2481 + } 2482 + 2483 + static int nvme_trans_report_luns(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2484 + u8 *cmd) 2485 + { 2486 + int res = SNTI_TRANSLATION_SUCCESS; 2487 + int nvme_sc; 2488 + u32 alloc_len, xfer_len, resp_size; 2489 + u8 select_report; 2490 + u8 *response; 2491 + struct nvme_dev *dev = ns->dev; 2492 + dma_addr_t dma_addr; 2493 + void *mem; 2494 + struct nvme_id_ctrl *id_ctrl; 2495 + u32 ll_length, lun_id; 2496 + u8 lun_id_offset = REPORT_LUNS_FIRST_LUN_OFFSET; 2497 + u32 tmp_len; 2498 + 2499 + alloc_len = GET_REPORT_LUNS_ALLOC_LENGTH(cmd); 2500 + select_report = GET_U8_FROM_CDB(cmd, REPORT_LUNS_SR_OFFSET); 2501 + 2502 + if ((select_report != ALL_LUNS_RETURNED) && 2503 + (select_report != ALL_WELL_KNOWN_LUNS_RETURNED) && 2504 + (select_report != RESTRICTED_LUNS_RETURNED)) { 2505 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2506 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2507 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2508 + goto out; 2509 + } else { 2510 + /* NVMe Controller Identify */ 2511 + mem = dma_alloc_coherent(&dev->pci_dev->dev, 2512 + sizeof(struct nvme_id_ctrl), 2513 + &dma_addr, GFP_KERNEL); 2514 + if (mem == NULL) { 2515 + res = -ENOMEM; 2516 + goto out; 2517 + } 2518 + nvme_sc = nvme_identify(dev, 0, 1, dma_addr); 2519 + res = nvme_trans_status_code(hdr, nvme_sc); 2520 + if (res) 2521 + goto out_dma; 2522 + if (nvme_sc) { 2523 + res = nvme_sc; 2524 + goto out_dma; 2525 + } 2526 + id_ctrl = mem; 2527 + ll_length = id_ctrl->nn * LUN_ENTRY_SIZE; 2528 + resp_size = ll_length + LUN_DATA_HEADER_SIZE; 2529 + 2530 + if (alloc_len < resp_size) { 2531 + res = nvme_trans_completion(hdr, 2532 + SAM_STAT_CHECK_CONDITION, 2533 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2534 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2535 + goto out_dma; 2536 + } 2537 + 2538 + response = kmalloc(resp_size, GFP_KERNEL); 2539 + if (response == NULL) { 2540 + res = -ENOMEM; 2541 + goto out_dma; 2542 + } 2543 + memset(response, 0, resp_size); 2544 + 2545 + /* The first LUN ID will always be 0 per the SAM spec */ 2546 + for (lun_id = 0; lun_id < id_ctrl->nn; lun_id++) { 2547 + /* 2548 + * Set the LUN Id and then increment to the next LUN 2549 + * location in the parameter data. 2550 + */ 2551 + u64 tmp_id = cpu_to_be64(lun_id); 2552 + memcpy(&response[lun_id_offset], &tmp_id, sizeof(u64)); 2553 + lun_id_offset += LUN_ENTRY_SIZE; 2554 + } 2555 + tmp_len = cpu_to_be32(ll_length); 2556 + memcpy(response, &tmp_len, sizeof(u32)); 2557 + } 2558 + 2559 + xfer_len = min(alloc_len, resp_size); 2560 + res = nvme_trans_copy_to_user(hdr, response, xfer_len); 2561 + 2562 + kfree(response); 2563 + out_dma: 2564 + dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem, 2565 + dma_addr); 2566 + out: 2567 + return res; 2568 + } 2569 + 2570 + static int nvme_trans_request_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2571 + u8 *cmd) 2572 + { 2573 + int res = SNTI_TRANSLATION_SUCCESS; 2574 + u8 alloc_len, xfer_len, resp_size; 2575 + u8 desc_format; 2576 + u8 *response; 2577 + 2578 + alloc_len = GET_REQUEST_SENSE_ALLOC_LENGTH(cmd); 2579 + desc_format = GET_U8_FROM_CDB(cmd, REQUEST_SENSE_DESC_OFFSET); 2580 + desc_format &= REQUEST_SENSE_DESC_MASK; 2581 + 2582 + resp_size = ((desc_format) ? (DESC_FMT_SENSE_DATA_SIZE) : 2583 + (FIXED_FMT_SENSE_DATA_SIZE)); 2584 + response = kmalloc(resp_size, GFP_KERNEL); 2585 + if (response == NULL) { 2586 + res = -ENOMEM; 2587 + goto out; 2588 + } 2589 + memset(response, 0, resp_size); 2590 + 2591 + if (desc_format == DESCRIPTOR_FORMAT_SENSE_DATA_TYPE) { 2592 + /* Descriptor Format Sense Data */ 2593 + response[0] = DESC_FORMAT_SENSE_DATA; 2594 + response[1] = NO_SENSE; 2595 + /* TODO How is LOW POWER CONDITION ON handled? (byte 2) */ 2596 + response[2] = SCSI_ASC_NO_SENSE; 2597 + response[3] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 2598 + /* SDAT_OVFL = 0 | Additional Sense Length = 0 */ 2599 + } else { 2600 + /* Fixed Format Sense Data */ 2601 + response[0] = FIXED_SENSE_DATA; 2602 + /* Byte 1 = Obsolete */ 2603 + response[2] = NO_SENSE; /* FM, EOM, ILI, SDAT_OVFL = 0 */ 2604 + /* Bytes 3-6 - Information - set to zero */ 2605 + response[7] = FIXED_SENSE_DATA_ADD_LENGTH; 2606 + /* Bytes 8-11 - Cmd Specific Information - set to zero */ 2607 + response[12] = SCSI_ASC_NO_SENSE; 2608 + response[13] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; 2609 + /* Byte 14 = Field Replaceable Unit Code = 0 */ 2610 + /* Bytes 15-17 - SKSV=0; Sense Key Specific = 0 */ 2611 + } 2612 + 2613 + xfer_len = min(alloc_len, resp_size); 2614 + res = nvme_trans_copy_to_user(hdr, response, xfer_len); 2615 + 2616 + kfree(response); 2617 + out: 2618 + return res; 2619 + } 2620 + 2621 + static int nvme_trans_security_protocol(struct nvme_ns *ns, 2622 + struct sg_io_hdr *hdr, 2623 + u8 *cmd) 2624 + { 2625 + return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2626 + ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND, 2627 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2628 + } 2629 + 2630 + static int nvme_trans_start_stop(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2631 + u8 *cmd) 2632 + { 2633 + int res = SNTI_TRANSLATION_SUCCESS; 2634 + int nvme_sc; 2635 + struct nvme_queue *nvmeq = get_nvmeq(ns->dev); 2636 + u8 immed, pcmod, pc, no_flush, start; 2637 + 2638 + immed = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_IMMED_OFFSET); 2639 + pcmod = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET); 2640 + pc = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_OFFSET); 2641 + no_flush = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_NO_FLUSH_OFFSET); 2642 + start = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_START_OFFSET); 2643 + 2644 + immed &= START_STOP_UNIT_CDB_IMMED_MASK; 2645 + pcmod &= START_STOP_UNIT_CDB_POWER_COND_MOD_MASK; 2646 + pc = (pc & START_STOP_UNIT_CDB_POWER_COND_MASK) >> NIBBLE_SHIFT; 2647 + no_flush &= START_STOP_UNIT_CDB_NO_FLUSH_MASK; 2648 + start &= START_STOP_UNIT_CDB_START_MASK; 2649 + 2650 + if (immed != 0) { 2651 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2652 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2653 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2654 + } else { 2655 + if (no_flush == 0) { 2656 + /* Issue NVME FLUSH command prior to START STOP UNIT */ 2657 + nvme_sc = nvme_submit_flush_data(nvmeq, ns); 2658 + put_nvmeq(nvmeq); 2659 + res = nvme_trans_status_code(hdr, nvme_sc); 2660 + if (res) 2661 + goto out; 2662 + if (nvme_sc) { 2663 + res = nvme_sc; 2664 + goto out; 2665 + } 2666 + } 2667 + /* Setup the expected power state transition */ 2668 + res = nvme_trans_power_state(ns, hdr, pc, pcmod, start); 2669 + } 2670 + 2671 + out: 2672 + return res; 2673 + } 2674 + 2675 + static int nvme_trans_synchronize_cache(struct nvme_ns *ns, 2676 + struct sg_io_hdr *hdr, u8 *cmd) 2677 + { 2678 + int res = SNTI_TRANSLATION_SUCCESS; 2679 + int nvme_sc; 2680 + struct nvme_queue *nvmeq = get_nvmeq(ns->dev); 2681 + put_nvmeq(nvmeq); 2682 + nvme_sc = nvme_submit_flush_data(nvmeq, ns); 2683 + res = nvme_trans_status_code(hdr, nvme_sc); 2684 + if (res) 2685 + goto out; 2686 + if (nvme_sc) 2687 + res = nvme_sc; 2688 + 2689 + out: 2690 + return res; 2691 + } 2692 + 2693 + static int nvme_trans_format_unit(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2694 + u8 *cmd) 2695 + { 2696 + int res = SNTI_TRANSLATION_SUCCESS; 2697 + u8 parm_hdr_len = 0; 2698 + u8 nvme_pf_code = 0; 2699 + u8 format_prot_info, long_list, format_data; 2700 + 2701 + format_prot_info = GET_U8_FROM_CDB(cmd, 2702 + FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET); 2703 + long_list = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_LONG_LIST_OFFSET); 2704 + format_data = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET); 2705 + 2706 + format_prot_info = (format_prot_info & 2707 + FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK) >> 2708 + FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT; 2709 + long_list &= FORMAT_UNIT_CDB_LONG_LIST_MASK; 2710 + format_data &= FORMAT_UNIT_CDB_FORMAT_DATA_MASK; 2711 + 2712 + if (format_data != 0) { 2713 + if (format_prot_info != 0) { 2714 + if (long_list == 0) 2715 + parm_hdr_len = FORMAT_UNIT_SHORT_PARM_LIST_LEN; 2716 + else 2717 + parm_hdr_len = FORMAT_UNIT_LONG_PARM_LIST_LEN; 2718 + } 2719 + } else if (format_data == 0 && format_prot_info != 0) { 2720 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2721 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2722 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2723 + goto out; 2724 + } 2725 + 2726 + /* Get parm header from data-in/out buffer */ 2727 + /* 2728 + * According to the translation spec, the only fields in the parameter 2729 + * list we are concerned with are in the header. So allocate only that. 2730 + */ 2731 + if (parm_hdr_len > 0) { 2732 + res = nvme_trans_fmt_get_parm_header(hdr, parm_hdr_len, 2733 + format_prot_info, &nvme_pf_code); 2734 + if (res != SNTI_TRANSLATION_SUCCESS) 2735 + goto out; 2736 + } 2737 + 2738 + /* Attempt to activate any previously downloaded firmware image */ 2739 + res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw, 0, 0, 0); 2740 + 2741 + /* Determine Block size and count and send format command */ 2742 + res = nvme_trans_fmt_set_blk_size_count(ns, hdr); 2743 + if (res != SNTI_TRANSLATION_SUCCESS) 2744 + goto out; 2745 + 2746 + res = nvme_trans_fmt_send_cmd(ns, hdr, nvme_pf_code); 2747 + 2748 + out: 2749 + return res; 2750 + } 2751 + 2752 + static int nvme_trans_test_unit_ready(struct nvme_ns *ns, 2753 + struct sg_io_hdr *hdr, 2754 + u8 *cmd) 2755 + { 2756 + int res = SNTI_TRANSLATION_SUCCESS; 2757 + struct nvme_dev *dev = ns->dev; 2758 + 2759 + if (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) 2760 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2761 + NOT_READY, SCSI_ASC_LUN_NOT_READY, 2762 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2763 + else 2764 + res = nvme_trans_completion(hdr, SAM_STAT_GOOD, NO_SENSE, 0, 0); 2765 + 2766 + return res; 2767 + } 2768 + 2769 + static int nvme_trans_write_buffer(struct nvme_ns *ns, struct sg_io_hdr *hdr, 2770 + u8 *cmd) 2771 + { 2772 + int res = SNTI_TRANSLATION_SUCCESS; 2773 + u32 buffer_offset, parm_list_length; 2774 + u8 buffer_id, mode; 2775 + 2776 + parm_list_length = 2777 + GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET); 2778 + if (parm_list_length % BYTES_TO_DWORDS != 0) { 2779 + /* NVMe expects Firmware file to be a whole number of DWORDS */ 2780 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2781 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2782 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2783 + goto out; 2784 + } 2785 + buffer_id = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_ID_OFFSET); 2786 + if (buffer_id > NVME_MAX_FIRMWARE_SLOT) { 2787 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2788 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2789 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2790 + goto out; 2791 + } 2792 + mode = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_MODE_OFFSET) & 2793 + WRITE_BUFFER_CDB_MODE_MASK; 2794 + buffer_offset = 2795 + GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET); 2796 + 2797 + switch (mode) { 2798 + case DOWNLOAD_SAVE_ACTIVATE: 2799 + res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw, 2800 + parm_list_length, buffer_offset, 2801 + buffer_id); 2802 + if (res != SNTI_TRANSLATION_SUCCESS) 2803 + goto out; 2804 + res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw, 2805 + parm_list_length, buffer_offset, 2806 + buffer_id); 2807 + break; 2808 + case DOWNLOAD_SAVE_DEFER_ACTIVATE: 2809 + res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw, 2810 + parm_list_length, buffer_offset, 2811 + buffer_id); 2812 + break; 2813 + case ACTIVATE_DEFERRED_MICROCODE: 2814 + res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw, 2815 + parm_list_length, buffer_offset, 2816 + buffer_id); 2817 + break; 2818 + default: 2819 + res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2820 + ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, 2821 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2822 + break; 2823 + } 2824 + 2825 + out: 2826 + return res; 2827 + } 2828 + 2829 + static int nvme_scsi_translate(struct nvme_ns *ns, struct sg_io_hdr *hdr) 2830 + { 2831 + u8 cmd[BLK_MAX_CDB]; 2832 + int retcode; 2833 + unsigned int opcode; 2834 + 2835 + if (hdr->cmdp == NULL) 2836 + return -EMSGSIZE; 2837 + if (copy_from_user(cmd, hdr->cmdp, hdr->cmd_len)) 2838 + return -EFAULT; 2839 + 2840 + opcode = cmd[0]; 2841 + 2842 + switch (opcode) { 2843 + case READ_6: 2844 + case READ_10: 2845 + case READ_12: 2846 + case READ_16: 2847 + retcode = nvme_trans_io(ns, hdr, 0, cmd); 2848 + break; 2849 + case WRITE_6: 2850 + case WRITE_10: 2851 + case WRITE_12: 2852 + case WRITE_16: 2853 + retcode = nvme_trans_io(ns, hdr, 1, cmd); 2854 + break; 2855 + case INQUIRY: 2856 + retcode = nvme_trans_inquiry(ns, hdr, cmd); 2857 + break; 2858 + case LOG_SENSE: 2859 + retcode = nvme_trans_log_sense(ns, hdr, cmd); 2860 + break; 2861 + case MODE_SELECT: 2862 + case MODE_SELECT_10: 2863 + retcode = nvme_trans_mode_select(ns, hdr, cmd); 2864 + break; 2865 + case MODE_SENSE: 2866 + case MODE_SENSE_10: 2867 + retcode = nvme_trans_mode_sense(ns, hdr, cmd); 2868 + break; 2869 + case READ_CAPACITY: 2870 + retcode = nvme_trans_read_capacity(ns, hdr, cmd); 2871 + break; 2872 + case SERVICE_ACTION_IN: 2873 + if (IS_READ_CAP_16(cmd)) 2874 + retcode = nvme_trans_read_capacity(ns, hdr, cmd); 2875 + else 2876 + goto out; 2877 + break; 2878 + case REPORT_LUNS: 2879 + retcode = nvme_trans_report_luns(ns, hdr, cmd); 2880 + break; 2881 + case REQUEST_SENSE: 2882 + retcode = nvme_trans_request_sense(ns, hdr, cmd); 2883 + break; 2884 + case SECURITY_PROTOCOL_IN: 2885 + case SECURITY_PROTOCOL_OUT: 2886 + retcode = nvme_trans_security_protocol(ns, hdr, cmd); 2887 + break; 2888 + case START_STOP: 2889 + retcode = nvme_trans_start_stop(ns, hdr, cmd); 2890 + break; 2891 + case SYNCHRONIZE_CACHE: 2892 + retcode = nvme_trans_synchronize_cache(ns, hdr, cmd); 2893 + break; 2894 + case FORMAT_UNIT: 2895 + retcode = nvme_trans_format_unit(ns, hdr, cmd); 2896 + break; 2897 + case TEST_UNIT_READY: 2898 + retcode = nvme_trans_test_unit_ready(ns, hdr, cmd); 2899 + break; 2900 + case WRITE_BUFFER: 2901 + retcode = nvme_trans_write_buffer(ns, hdr, cmd); 2902 + break; 2903 + default: 2904 + out: 2905 + retcode = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, 2906 + ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND, 2907 + SCSI_ASCQ_CAUSE_NOT_REPORTABLE); 2908 + break; 2909 + } 2910 + return retcode; 2911 + } 2912 + 2913 + int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr) 2914 + { 2915 + struct sg_io_hdr hdr; 2916 + int retcode; 2917 + 2918 + if (!capable(CAP_SYS_ADMIN)) 2919 + return -EACCES; 2920 + if (copy_from_user(&hdr, u_hdr, sizeof(hdr))) 2921 + return -EFAULT; 2922 + if (hdr.interface_id != 'S') 2923 + return -EINVAL; 2924 + if (hdr.cmd_len > BLK_MAX_CDB) 2925 + return -EINVAL; 2926 + 2927 + retcode = nvme_scsi_translate(ns, &hdr); 2928 + if (retcode < 0) 2929 + return retcode; 2930 + if (retcode > 0) 2931 + retcode = SNTI_TRANSLATION_SUCCESS; 2932 + if (copy_to_user(__user u_hdr, &hdr, sizeof(sg_io_hdr_t)) > 0) 2933 + return -EFAULT; 2934 + 2935 + return retcode; 2936 + } 2937 + 2938 + int nvme_sg_get_version_num(int __user *ip) 2939 + { 2940 + return put_user(sg_version_num, ip); 2941 + }
+35
include/linux/nvme.h
··· 546 546 547 547 int ns_id; 548 548 int lba_shift; 549 + u64 mode_select_num_blocks; 550 + u32 mode_select_block_len; 549 551 }; 550 552 551 553 /* ··· 565 563 dma_addr_t first_dma; 566 564 struct scatterlist sg[0]; 567 565 }; 566 + 567 + /** 568 + * nvme_free_iod - frees an nvme_iod 569 + * @dev: The device that the I/O was submitted to 570 + * @iod: The memory to free 571 + */ 572 + void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod); 573 + 574 + int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, 575 + struct nvme_iod *iod, int total_len, gfp_t gfp); 576 + struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, 577 + unsigned long addr, unsigned length); 578 + void nvme_unmap_user_pages(struct nvme_dev *dev, int write, 579 + struct nvme_iod *iod); 580 + struct nvme_queue *get_nvmeq(struct nvme_dev *dev); 581 + void put_nvmeq(struct nvme_queue *nvmeq); 582 + int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 583 + u32 *result, unsigned timeout); 584 + int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns); 585 + int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *, 586 + u32 *result); 587 + int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns, 588 + dma_addr_t dma_addr); 589 + int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, 590 + dma_addr_t dma_addr, u32 *result); 591 + int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, 592 + dma_addr_t dma_addr, u32 *result); 593 + 594 + struct sg_io_hdr; 595 + 596 + int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); 597 + int nvme_sg_get_version_num(int __user *ip); 598 + 568 599 #endif 569 600 570 601 #endif /* _LINUX_NVME_H */