ASoC: Improve EP93xx I2S clocks management.

Improve EP93xx I2S clocks management.
Some freqs values are set not exact as they requested for MCLK and
original code was not able to find divisors for SCLK and LRCLK.
This code just picks up nearest value from 3 possible variants.
This patch makes 44100 and 192000 rates working and fixes
capture function (by selecting SCLK/LRCLK=64 where possible).
All other rates should work as before.

Signed-off-by: Alexander Sverdlin <subaparts@yandex.ru>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

authored by Alexander Sverdlin and committed by Mark Brown 5cbf7e49 6d33cd77

+9 -10
+9 -10
sound/soc/ep93xx/ep93xx-i2s.c
··· 242 242 { 243 243 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 244 244 unsigned word_len, div, sdiv, lrdiv; 245 - int found = 0, err; 245 + int err; 246 246 247 247 switch (params_format(params)) { 248 248 case SNDRV_PCM_FORMAT_S16_LE: ··· 275 275 * the codec uses. 276 276 */ 277 277 div = clk_get_rate(info->mclk) / params_rate(params); 278 - for (sdiv = 2; sdiv <= 4; sdiv += 2) 279 - for (lrdiv = 64; lrdiv <= 128; lrdiv <<= 1) 280 - if (sdiv * lrdiv == div) { 281 - found = 1; 282 - goto out; 283 - } 284 - out: 285 - if (!found) 286 - return -EINVAL; 278 + sdiv = 4; 279 + if (div > (256 + 512) / 2) { 280 + lrdiv = 128; 281 + } else { 282 + lrdiv = 64; 283 + if (div < (128 + 256) / 2) 284 + sdiv = 2; 285 + } 287 286 288 287 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); 289 288 if (err)