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dt-bindings: memory: tegra: Add hot resets definitions
Add definitions for the Tegra20+ memory controller hot resets.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Dmitry Osipenko
and committed by
Thierry Reding
5c8d08f3
60cc43fc
+115
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include/dt-bindings/memory/tegra114-mc.h
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include/dt-bindings/memory/tegra114-mc.h
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#define TEGRA_SWGROUP_EMUCIF 18
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#define TEGRA_SWGROUP_TSEC 19
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#define TEGRA114_MC_RESET_AFI 0
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#define TEGRA114_MC_RESET_AVPC 1
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#define TEGRA114_MC_RESET_DC 2
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#define TEGRA114_MC_RESET_DCB 3
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#define TEGRA114_MC_RESET_EPP 4
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#define TEGRA114_MC_RESET_2D 5
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#define TEGRA114_MC_RESET_HC 6
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#define TEGRA114_MC_RESET_HDA 7
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#define TEGRA114_MC_RESET_ISP 8
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#define TEGRA114_MC_RESET_MPCORE 9
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#define TEGRA114_MC_RESET_MPCORELP 10
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#define TEGRA114_MC_RESET_MPE 11
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#define TEGRA114_MC_RESET_3D 12
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#define TEGRA114_MC_RESET_3D2 13
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#define TEGRA114_MC_RESET_PPCS 14
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#define TEGRA114_MC_RESET_SATA 15
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#define TEGRA114_MC_RESET_VDE 16
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#define TEGRA114_MC_RESET_VI 17
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#endif
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include/dt-bindings/memory/tegra124-mc.h
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include/dt-bindings/memory/tegra124-mc.h
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#define TEGRA_SWGROUP_VIC 24
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#define TEGRA_SWGROUP_VI 25
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#define TEGRA124_MC_RESET_AFI 0
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#define TEGRA124_MC_RESET_AVPC 1
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#define TEGRA124_MC_RESET_DC 2
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#define TEGRA124_MC_RESET_DCB 3
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#define TEGRA124_MC_RESET_HC 4
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#define TEGRA124_MC_RESET_HDA 5
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#define TEGRA124_MC_RESET_ISP2 6
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#define TEGRA124_MC_RESET_MPCORE 7
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#define TEGRA124_MC_RESET_MPCORELP 8
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#define TEGRA124_MC_RESET_MSENC 9
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#define TEGRA124_MC_RESET_PPCS 10
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#define TEGRA124_MC_RESET_SATA 11
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#define TEGRA124_MC_RESET_VDE 12
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#define TEGRA124_MC_RESET_VI 13
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#define TEGRA124_MC_RESET_VIC 14
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#define TEGRA124_MC_RESET_XUSB_HOST 15
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#define TEGRA124_MC_RESET_XUSB_DEV 16
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#define TEGRA124_MC_RESET_TSEC 17
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#define TEGRA124_MC_RESET_SDMMC1 18
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#define TEGRA124_MC_RESET_SDMMC2 19
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#define TEGRA124_MC_RESET_SDMMC3 20
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#define TEGRA124_MC_RESET_SDMMC4 21
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#define TEGRA124_MC_RESET_ISP2B 22
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#define TEGRA124_MC_RESET_GPU 23
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#endif
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include/dt-bindings/memory/tegra20-mc.h
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include/dt-bindings/memory/tegra20-mc.h
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
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#define TEGRA20_MC_RESET_AVPC 0
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#define TEGRA20_MC_RESET_DC 1
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#define TEGRA20_MC_RESET_DCB 2
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#define TEGRA20_MC_RESET_EPP 3
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#define TEGRA20_MC_RESET_2D 4
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#define TEGRA20_MC_RESET_HC 5
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#define TEGRA20_MC_RESET_ISP 6
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#define TEGRA20_MC_RESET_MPCORE 7
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#define TEGRA20_MC_RESET_MPEA 8
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#define TEGRA20_MC_RESET_MPEB 9
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#define TEGRA20_MC_RESET_MPEC 10
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#define TEGRA20_MC_RESET_3D 11
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#define TEGRA20_MC_RESET_PPCS 12
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#define TEGRA20_MC_RESET_VDE 13
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#define TEGRA20_MC_RESET_VI 14
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#endif
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include/dt-bindings/memory/tegra210-mc.h
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include/dt-bindings/memory/tegra210-mc.h
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#define TEGRA_SWGROUP_ETR 29
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#define TEGRA_SWGROUP_TSECB 30
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#define TEGRA210_MC_RESET_AFI 0
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#define TEGRA210_MC_RESET_AVPC 1
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#define TEGRA210_MC_RESET_DC 2
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#define TEGRA210_MC_RESET_DCB 3
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#define TEGRA210_MC_RESET_HC 4
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#define TEGRA210_MC_RESET_HDA 5
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#define TEGRA210_MC_RESET_ISP2 6
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#define TEGRA210_MC_RESET_MPCORE 7
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#define TEGRA210_MC_RESET_NVENC 8
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#define TEGRA210_MC_RESET_PPCS 9
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#define TEGRA210_MC_RESET_SATA 10
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#define TEGRA210_MC_RESET_VI 11
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#define TEGRA210_MC_RESET_VIC 12
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#define TEGRA210_MC_RESET_XUSB_HOST 13
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#define TEGRA210_MC_RESET_XUSB_DEV 14
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#define TEGRA210_MC_RESET_A9AVP 15
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#define TEGRA210_MC_RESET_TSEC 16
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#define TEGRA210_MC_RESET_SDMMC1 17
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#define TEGRA210_MC_RESET_SDMMC2 18
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#define TEGRA210_MC_RESET_SDMMC3 19
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#define TEGRA210_MC_RESET_SDMMC4 20
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#define TEGRA210_MC_RESET_ISP2B 21
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#define TEGRA210_MC_RESET_GPU 22
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#define TEGRA210_MC_RESET_NVDEC 23
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#define TEGRA210_MC_RESET_APE 24
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#define TEGRA210_MC_RESET_SE 25
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#define TEGRA210_MC_RESET_NVJPG 26
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#define TEGRA210_MC_RESET_AXIAP 27
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#define TEGRA210_MC_RESET_ETR 28
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#define TEGRA210_MC_RESET_TSECB 29
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#endif
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include/dt-bindings/memory/tegra30-mc.h
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include/dt-bindings/memory/tegra30-mc.h
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#define TEGRA_SWGROUP_MPCORE 17
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#define TEGRA_SWGROUP_ISP 18
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#define TEGRA30_MC_RESET_AFI 0
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#define TEGRA30_MC_RESET_AVPC 1
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#define TEGRA30_MC_RESET_DC 2
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#define TEGRA30_MC_RESET_DCB 3
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#define TEGRA30_MC_RESET_EPP 4
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#define TEGRA30_MC_RESET_2D 5
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#define TEGRA30_MC_RESET_HC 6
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#define TEGRA30_MC_RESET_HDA 7
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#define TEGRA30_MC_RESET_ISP 8
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#define TEGRA30_MC_RESET_MPCORE 9
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#define TEGRA30_MC_RESET_MPCORELP 10
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#define TEGRA30_MC_RESET_MPE 11
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#define TEGRA30_MC_RESET_3D 12
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#define TEGRA30_MC_RESET_3D2 13
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#define TEGRA30_MC_RESET_PPCS 14
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#define TEGRA30_MC_RESET_SATA 15
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#define TEGRA30_MC_RESET_VDE 16
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#define TEGRA30_MC_RESET_VI 17
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#endif