···11+Lantiq XWAY pinmux controller22+33+Required properties:44+- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"55+- reg: Should contain the physical address and length of the gpio/pinmux66+ register range77+88+Please refer to pinctrl-bindings.txt in this directory for details of the99+common pinctrl bindings used by client devices, including the meaning of the1010+phrase "pin configuration node".1111+1212+Lantiq's pin configuration nodes act as a container for an abitrary number of1313+subnodes. Each of these subnodes represents some desired configuration for a1414+pin, a group, or a list of pins or groups. This configuration can include the1515+mux function to select on those group(s), and two pin configuration parameters:1616+pull-up and open-drain1717+1818+The name of each subnode is not important as long as it is unique; all subnodes1919+should be enumerated and processed purely based on their content.2020+2121+Each subnode only affects those parameters that are explicitly listed. In2222+other words, a subnode that lists a mux function but no pin configuration2323+parameters implies no information about any pin configuration parameters.2424+Similarly, a pin subnode that describes a pullup parameter implies no2525+information about e.g. the mux function.2626+2727+We support 2 types of nodes.2828+2929+Definition of mux function groups:3030+3131+Required subnode-properties:3232+- lantiq,groups : An array of strings. Each string contains the name of a group.3333+ Valid values for these names are listed below.3434+- lantiq,function: A string containing the name of the function to mux to the3535+ group. Valid values for function names are listed below.3636+3737+Valid values for group and function names:3838+3939+ mux groups:4040+ exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,4141+ ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,4242+ spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,4343+ gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,4444+ req34545+4646+ additional mux groups (XR9 only):4747+ mdio, nand rdy, nand rd, exin3, exin4, gnt4, req44848+4949+ functions:5050+ spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio5151+5252+5353+5454+Definition of pin configurations:5555+5656+Required subnode-properties:5757+- lantiq,pins : An array of strings. Each string contains the name of a pin.5858+ Valid values for these names are listed below.5959+6060+Optional subnode-properties:6161+- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.6262+ 0: none, 1: down, 2: up.6363+- lantiq,open-drain: Boolean, enables open-drain on the defined pin.6464+6565+Valid values for XWAY pin names:6666+ Pinconf pins can be referenced via the names io0-io31.6767+6868+Valid values for XR9 pin names:6969+ Pinconf pins can be referenced via the names io0-io55.7070+7171+Example:7272+ gpio: pinmux@E100B10 {7373+ compatible = "lantiq,pinctrl-xway";7474+ pinctrl-names = "default";7575+ pinctrl-0 = <&state_default>;7676+7777+ #gpio-cells = <2>;7878+ gpio-controller;7979+ reg = <0xE100B10 0xA0>;8080+8181+ state_default: pinmux {8282+ stp {8383+ lantiq,groups = "stp";8484+ lantiq,function = "stp";8585+ };8686+ pci {8787+ lantiq,groups = "gnt1";8888+ lantiq,function = "pci";8989+ };9090+ conf_out {9191+ lantiq,pins = "io4", "io5", "io6"; /* stp */9292+ lantiq,open-drain;9393+ lantiq,pull = <0>;9494+ };9595+ };9696+ };9797+