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dt-bindings: phy: Tegra194 P2U convert to YAML

Convert Tegra194 P2U binding to the YAML format.

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211031113236.29712-1-david@ixit.cz
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

David Heidelberg and committed by
Vinod Koul
5c2ecfce e45dbd3a

+44 -28
-28
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
··· 1 - NVIDIA Tegra194 P2U binding 2 - 3 - Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High 4 - Speed) each interfacing with 12 and 8 P2U instances respectively. 5 - A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE 6 - interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe 7 - lane. 8 - 9 - Required properties: 10 - - compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". 11 - - reg: Should be the physical address space and length of respective each P2U 12 - instance. 13 - - reg-names: Must include the entry "ctl". 14 - 15 - Required properties for PHY port node: 16 - - #phy-cells: Defined by generic PHY bindings. Must be 0. 17 - 18 - Refer to phy/phy-bindings.txt for the generic PHY binding properties. 19 - 20 - Example: 21 - 22 - p2u_hsio_0: phy@3e10000 { 23 - compatible = "nvidia,tegra194-p2u"; 24 - reg = <0x03e10000 0x10000>; 25 - reg-names = "ctl"; 26 - 27 - #phy-cells = <0>; 28 - };
+44
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: NVIDIA Tegra194 P2U binding 8 + 9 + maintainers: 10 + - Thierry Reding <treding@nvidia.com> 11 + 12 + description: > 13 + Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High 14 + Speed) each interfacing with 12 and 8 P2U instances respectively. 15 + A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE 16 + interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe 17 + lane. 18 + 19 + properties: 20 + compatible: 21 + const: nvidia,tegra194-p2u 22 + 23 + reg: 24 + maxItems: 1 25 + description: Should be the physical address space and length of respective each P2U instance. 26 + 27 + reg-names: 28 + items: 29 + - const: ctl 30 + 31 + '#phy-cells': 32 + const: 0 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + p2u_hsio_0: phy@3e10000 { 39 + compatible = "nvidia,tegra194-p2u"; 40 + reg = <0x03e10000 0x10000>; 41 + reg-names = "ctl"; 42 + 43 + #phy-cells = <0>; 44 + };