mm: introduce cpu_icache_is_aliasing() across all architectures

In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing
VIPT)"), arc adds the need to flush dcache to make icache see the code
page change. This also requires special handling for
clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make MM
code query special clear_user_(high)page() easier. This will be used by
the following commit.

Link: https://lkml.kernel.org/r/[e-mail]
Fixes: 5708d96da20b ("mm: avoid zeroing user movable page twice with init_on_alloc=1")
Signed-off-by: Zi Yan <[e-mail]>
Suggested-by: Mathieu Desnoyers <[e-mail]>
Reviewed-by: Mathieu Desnoyers <[e-mail]>
Acked-by: Vlastimil Babka <[e-mail]>
Cc: Alexander Potapenko <[e-mail]>
Cc: David Hildenbrand <[e-mail]>
Cc: Geert Uytterhoeven <[e-mail]>
Cc: John Hubbard <[e-mail]>
Cc: Kees Cook <[e-mail]>
Cc: Kefeng Wang <[e-mail]>
Cc: Matthew Wilcox <[e-mail]>
Cc: Miaohe Lin <[e-mail]>
Cc: Ryan Roberts <[e-mail]>
Cc: Vineet Gupta <[e-mail]>
Signed-off-by: Andrew Morton <[e-mail]>

arch/arc/Kconfig

···
 config ARC
 	def_bool y
 	select ARC_TIMERS
+	select ARCH_HAS_CPU_CACHE_ALIASING
 	select ARCH_HAS_CACHE_LINE_SIZE
 	select ARCH_HAS_DEBUG_VM_PGTABLE
 	select ARCH_HAS_DMA_PREP_COHERENT

arch/arc/include/asm/cachetype.h

···
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_ARC_CACHETYPE_H
+#define __ASM_ARC_CACHETYPE_H
+
+#define cpu_dcache_is_aliasing()	false
+#define cpu_icache_is_aliasing()	true
+
+#endif

include/linux/cacheinfo.h

···
 
 #ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING
 #define cpu_dcache_is_aliasing()	false
+#define cpu_icache_is_aliasing()	cpu_dcache_is_aliasing()
 #else
 #include <asm/cachetype.h>
+
+#ifndef cpu_icache_is_aliasing
+#define cpu_icache_is_aliasing()	cpu_dcache_is_aliasing()
+#endif
+
 #endif
 
 #endif /* _LINUX_CACHEINFO_H */