Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'sh-for-v6.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux

Pull sh updates from John Paul Adrian Glaubitz:
"While the previously announced patch series for converting arch/sh to
device trees is not yet ready for inclusion to mainline and therefore
didn't make it for this pull request, there are still a small number
changes for v6.7 which include one platform (board plus CPU and driver
code) removal plus two fixes.

The removal sent in by Arnd Bergmann concerns the microdev board which
was an early SuperH prototype board that was never used in production.
With the board removed, we were able to drop the now unused code for
the SH4-202 CPU and well as the driver code for the superhyway bus and
a custom implementation for ioport_map() and ioport_unmap() which will
allow us to simplify ioport handling in the future.

Another patch set by Geert Uytterhoeven revives SuperH BIOS
earlyprintk support which got accidentally disabled in
e76fe57447e88916 ("sh: Remove old early serial console code V2"), the
second patch in the series updates the documentation.

Finally, a patch by Masami Hiramatsu fixes a regression reported by
the kernel test robot which uncovered that arch/sh is not implementing
arch_cmpxchg_local() and therefore needs use __generic_cmpxchg_local()
instead"

* tag 'sh-for-v6.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux:
locking/atomic: sh: Use generic_cmpxchg_local for arch_cmpxchg_local()
Documentation: kernel-parameters: Add earlyprintk=bios on SH
sh: bios: Revive earlyprintk support
sh: machvec: Remove custom ioport_{un,}map()
sh: Remove superhyway bus support
sh: Remove unused SH4-202 support
sh: Remove stale microdev board

+27 -1704
+3
Documentation/admin-guide/kernel-parameters.txt
··· 1335 1335 earlyprintk=dbgp[debugController#] 1336 1336 earlyprintk=pciserial[,force],bus:device.function[,baudrate] 1337 1337 earlyprintk=xdbc[xhciController#] 1338 + earlyprintk=bios 1338 1339 1339 1340 earlyprintk is useful when the kernel crashes before 1340 1341 the normal console is initialized. It is not enabled by ··· 1365 1364 The xen option can only be used in Xen domains. 1366 1365 1367 1366 The sclp output can only be used on s390. 1367 + 1368 + The bios output can only be used on SuperH. 1368 1369 1369 1370 The optional "force" to "pciserial" enables use of a 1370 1371 PCI device even when its classcode is not of the
-6
Documentation/arch/sh/index.rst
··· 43 43 Busses 44 44 ====== 45 45 46 - SuperHyway 47 - ---------- 48 - 49 - .. kernel-doc:: drivers/sh/superhyway/superhyway.c 50 - :export: 51 - 52 46 Maple 53 47 ----- 54 48
+1 -11
arch/sh/Kconfig
··· 124 124 125 125 config NO_IOPORT_MAP 126 126 def_bool !PCI 127 - depends on !SH_SH4202_MICRODEV && !SH_SHMIN && !SH_HP6XX && \ 128 - !SH_SOLUTION_ENGINE 127 + depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE 129 128 130 129 config IO_TRAPPED 131 130 bool ··· 383 384 bool "Support SH7760 processor" 384 385 select CPU_SH4 385 386 386 - config CPU_SUBTYPE_SH4_202 387 - bool "Support SH4-202 processor" 388 - select CPU_SH4 389 - 390 387 # SH-4A Processor Support 391 388 392 389 config CPU_SUBTYPE_SH7723 ··· 513 518 CPU_SUBTYPE_SH7263 || \ 514 519 CPU_SUBTYPE_MXG 515 520 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R 516 - default "66000000" if CPU_SUBTYPE_SH4_202 517 521 default "50000000" 518 522 help 519 523 This option is used to specify the peripheral clock frequency. ··· 736 742 endmenu 737 743 738 744 menu "Bus options" 739 - 740 - config SUPERHYWAY 741 - tristate "SuperHyway Bus support" 742 - depends on CPU_SUBTYPE_SH4_202 743 745 744 746 config MAPLE 745 747 bool "Maple Bus support"
+11
arch/sh/Kconfig.debug
··· 22 22 every function call and will therefore incur a major 23 23 performance hit. Most users should say N. 24 24 25 + config EARLY_PRINTK 26 + bool "Early printk" 27 + depends on SH_STANDARD_BIOS 28 + help 29 + Say Y here to redirect kernel printk messages to the serial port 30 + used by the SH-IPL bootloader, starting very early in the boot 31 + process and ending when the kernel's serial console is initialised. 32 + This option is only useful while porting the kernel to a new machine, 33 + when the kernel may crash or hang before the serial console is 34 + initialised. If unsure, say N. 35 + 25 36 config 4KSTACKS 26 37 bool "Use 4Kb for kernel stacks instead of 8Kb" 27 38 depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
-7
arch/sh/boards/Kconfig
··· 289 289 Select if configuring for a Renesas EDOSK7760 290 290 evaluation board. 291 291 292 - config SH_SH4202_MICRODEV 293 - bool "SH4-202 MicroDev" 294 - depends on CPU_SUBTYPE_SH4_202 295 - help 296 - Select SH4-202 MicroDev if configuring for a SuperH MicroDev board 297 - with an SH4-202 CPU. 298 - 299 292 config SH_LANDISK 300 293 bool "LANDISK" 301 294 depends on CPU_SUBTYPE_SH7751R
-1
arch/sh/boards/Makefile
··· 33 33 obj-$(CONFIG_SH_SDK7786) += mach-sdk7786/ 34 34 obj-$(CONFIG_SH_X3PROTO) += mach-x3proto/ 35 35 obj-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp/ 36 - obj-$(CONFIG_SH_SH4202_MICRODEV)+= mach-microdev/ 37 36 obj-$(CONFIG_SH_LANDISK) += mach-landisk/ 38 37 obj-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2/ 39 38 obj-$(CONFIG_SH_RSK) += mach-rsk/
-6
arch/sh/boards/mach-microdev/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # Makefile for the SuperH MicroDev specific parts of the kernel 4 - # 5 - 6 - obj-y := setup.o irq.o io.o fdc37c93xapm.o
-157
arch/sh/boards/mach-microdev/fdc37c93xapm.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Setup for the SMSC FDC37C93xAPM 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * Copyright (C) 2003, 2004 SuperH, Inc. 7 - * Copyright (C) 2004, 2005 Paul Mundt 8 - * 9 - * SuperH SH4-202 MicroDev board support. 10 - */ 11 - #include <linux/init.h> 12 - #include <linux/ioport.h> 13 - #include <linux/io.h> 14 - #include <linux/err.h> 15 - #include <mach/microdev.h> 16 - 17 - #define SMSC_CONFIG_PORT_ADDR (0x3F0) 18 - #define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR 19 - #define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1) 20 - 21 - #define SMSC_ENTER_CONFIG_KEY 0x55 22 - #define SMSC_EXIT_CONFIG_KEY 0xaa 23 - 24 - #define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */ 25 - #define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */ 26 - #define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */ 27 - #define SMSC_ACTIVATE_INDEX 0x30 /* Activate */ 28 - #define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */ 29 - #define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */ 30 - #define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */ 31 - #define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */ 32 - #define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */ 33 - #define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */ 34 - 35 - #define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */ 36 - #define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */ 37 - #define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */ 38 - #define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */ 39 - #define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */ 40 - #define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */ 41 - #define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */ 42 - 43 - #define SMSC_READ_INDEXED(index) ({ \ 44 - outb((index), SMSC_INDEX_PORT_ADDR); \ 45 - inb(SMSC_DATA_PORT_ADDR); }) 46 - #define SMSC_WRITE_INDEXED(val, index) ({ \ 47 - outb((index), SMSC_INDEX_PORT_ADDR); \ 48 - outb((val), SMSC_DATA_PORT_ADDR); }) 49 - 50 - #define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */ 51 - #define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */ 52 - #define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */ 53 - #define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */ 54 - 55 - #define SERIAL1_PRIMARY_BASE 0x03f8 56 - #define SERIAL2_PRIMARY_BASE 0x02f8 57 - 58 - #define MSB(x) ( (x) >> 8 ) 59 - #define LSB(x) ( (x) & 0xff ) 60 - 61 - /* General-Purpose base address on CPU-board FPGA */ 62 - #define MICRODEV_FPGA_GP_BASE 0xa6100000ul 63 - 64 - static int __init smsc_superio_setup(void) 65 - { 66 - 67 - unsigned char devid, devrev; 68 - 69 - /* Initially the chip is in run state */ 70 - /* Put it into configuration state */ 71 - outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 72 - 73 - /* Read device ID info */ 74 - devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); 75 - devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); 76 - 77 - if ((devid == 0x30) && (devrev == 0x01)) 78 - printk("SMSC FDC37C93xAPM SuperIO device detected\n"); 79 - else 80 - return -ENODEV; 81 - 82 - /* Select the keyboard device */ 83 - SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); 84 - /* enable it */ 85 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 86 - /* enable the interrupts */ 87 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX); 88 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX); 89 - 90 - /* Select the Serial #1 device */ 91 - SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX); 92 - /* enable it */ 93 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 94 - /* program with port addresses */ 95 - SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 96 - SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 97 - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); 98 - /* enable the interrupts */ 99 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX); 100 - 101 - /* Select the Serial #2 device */ 102 - SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX); 103 - /* enable it */ 104 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 105 - /* program with port addresses */ 106 - SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 107 - SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 108 - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); 109 - /* enable the interrupts */ 110 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX); 111 - 112 - /* Select the IDE#1 device */ 113 - SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); 114 - /* enable it */ 115 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 116 - /* program with port addresses */ 117 - SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 118 - SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 119 - SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); 120 - SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); 121 - SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX); 122 - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX); 123 - /* select the interrupt */ 124 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX); 125 - 126 - /* Select the IDE#2 device */ 127 - SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX); 128 - /* enable it */ 129 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 130 - /* program with port addresses */ 131 - SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 132 - SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 133 - SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); 134 - SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); 135 - /* select the interrupt */ 136 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX); 137 - 138 - /* Select the configuration registers */ 139 - SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); 140 - /* enable the appropriate GPIO pins for IDE functionality: 141 - * bit[0] In/Out 1==input; 0==output 142 - * bit[1] Polarity 1==invert; 0==no invert 143 - * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable 144 - * bit[3:4] Function Select 00==original; 01==Alternate Function #1 145 - */ 146 - SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ 147 - SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ 148 - SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ 149 - SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ 150 - SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ 151 - 152 - /* Exit the configuration state */ 153 - outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 154 - 155 - return 0; 156 - } 157 - device_initcall(smsc_superio_setup);
-123
arch/sh/boards/mach-microdev/io.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * linux/arch/sh/boards/superh/microdev/io.c 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * Copyright (C) 2003, 2004 SuperH, Inc. 7 - * Copyright (C) 2004 Paul Mundt 8 - * 9 - * SuperH SH4-202 MicroDev board support. 10 - */ 11 - 12 - #include <linux/init.h> 13 - #include <linux/pci.h> 14 - #include <linux/wait.h> 15 - #include <asm/io.h> 16 - #include <mach/microdev.h> 17 - 18 - /* 19 - * we need to have a 'safe' address to re-direct all I/O requests 20 - * that we do not explicitly wish to handle. This safe address 21 - * must have the following properies: 22 - * 23 - * * writes are ignored (no exception) 24 - * * reads are benign (no side-effects) 25 - * * accesses of width 1, 2 and 4-bytes are all valid. 26 - * 27 - * The Processor Version Register (PVR) has these properties. 28 - */ 29 - #define PVR 0xff000030 /* Processor Version Register */ 30 - 31 - 32 - #define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */ 33 - #define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */ 34 - #define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */ 35 - #define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */ 36 - #define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */ 37 - #define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */ 38 - #define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */ 39 - #define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */ 40 - #define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */ 41 - 42 - #define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */ 43 - #define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */ 44 - #define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */ 45 - #define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */ 46 - #define IO_SERIAL_EXTENT 0x10ul 47 - 48 - #define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */ 49 - #define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */ 50 - #define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */ 51 - 52 - /* 53 - * map I/O ports to memory-mapped addresses 54 - */ 55 - void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len) 56 - { 57 - unsigned long result; 58 - 59 - if ((offset >= IO_LAN91C111_BASE) && 60 - (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { 61 - /* 62 - * SMSC LAN91C111 Ethernet chip 63 - */ 64 - result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; 65 - } else if ((offset >= IO_SUPERIO_BASE) && 66 - (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { 67 - /* 68 - * SMSC FDC37C93xAPM SuperIO chip 69 - * 70 - * Configuration Registers 71 - */ 72 - result = IO_SUPERIO_PHYS + (offset << 1); 73 - } else if (((offset >= IO_IDE1_BASE) && 74 - (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || 75 - (offset == IO_IDE1_MISC)) { 76 - /* 77 - * SMSC FDC37C93xAPM SuperIO chip 78 - * 79 - * IDE #1 80 - */ 81 - result = IO_SUPERIO_PHYS + (offset << 1); 82 - } else if (((offset >= IO_IDE2_BASE) && 83 - (offset < IO_IDE2_BASE + IO_IDE_EXTENT)) || 84 - (offset == IO_IDE2_MISC)) { 85 - /* 86 - * SMSC FDC37C93xAPM SuperIO chip 87 - * 88 - * IDE #2 89 - */ 90 - result = IO_SUPERIO_PHYS + (offset << 1); 91 - } else if ((offset >= IO_SERIAL1_BASE) && 92 - (offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) { 93 - /* 94 - * SMSC FDC37C93xAPM SuperIO chip 95 - * 96 - * Serial #1 97 - */ 98 - result = IO_SUPERIO_PHYS + (offset << 1); 99 - } else if ((offset >= IO_SERIAL2_BASE) && 100 - (offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) { 101 - /* 102 - * SMSC FDC37C93xAPM SuperIO chip 103 - * 104 - * Serial #2 105 - */ 106 - result = IO_SUPERIO_PHYS + (offset << 1); 107 - } else if ((offset >= IO_ISP1161_BASE) && 108 - (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) { 109 - /* 110 - * Philips USB ISP1161x chip 111 - */ 112 - result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE; 113 - } else { 114 - /* 115 - * safe default. 116 - */ 117 - printk("Warning: unexpected port in %s( offset = 0x%lx )\n", 118 - __func__, offset); 119 - result = PVR; 120 - } 121 - 122 - return (void __iomem *)result; 123 - }
-150
arch/sh/boards/mach-microdev/irq.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/boards/superh/microdev/irq.c 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * 7 - * SuperH SH4-202 MicroDev board support. 8 - */ 9 - 10 - #include <linux/init.h> 11 - #include <linux/irq.h> 12 - #include <linux/interrupt.h> 13 - #include <asm/io.h> 14 - #include <mach/microdev.h> 15 - 16 - #define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */ 17 - 18 - static const struct { 19 - unsigned char fpgaIrq; 20 - unsigned char mapped; 21 - const char *name; 22 - } fpgaIrqTable[NUM_EXTERNAL_IRQS] = { 23 - { 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */ 24 - { MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */ 25 - { MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */ 26 - { MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */ 27 - { MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */ 28 - { 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */ 29 - { 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */ 30 - { MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */ 31 - { MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */ 32 - { MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */ 33 - { MICRODEV_IRQ_PCI_INTC, 1, "PCI INTC" }, /* IRQ #10 IRL=5 0x340 */ 34 - { MICRODEV_IRQ_PCI_INTD, 1, "PCI INTD" }, /* IRQ #11 IRL=4 0x360 */ 35 - { MICRODEV_FPGA_IRQ_MOUSE, 1, "mouse" }, /* IRQ #12 IRL=3 0x380 */ 36 - { MICRODEV_FPGA_IRQ_IDE2, 1, "IDE #2" }, /* IRQ #13 IRL=2 0x3a0 */ 37 - { MICRODEV_FPGA_IRQ_IDE1, 1, "IDE #1" }, /* IRQ #14 IRL=1 0x3c0 */ 38 - { 0, 0, "unused" }, /* IRQ #15 IRL=0 0x3e0 */ 39 - }; 40 - 41 - #if (MICRODEV_LINUX_IRQ_KEYBOARD != 1) 42 - # error Inconsistancy in defining the IRQ# for Keyboard! 43 - #endif 44 - 45 - #if (MICRODEV_LINUX_IRQ_ETHERNET != 3) 46 - # error Inconsistancy in defining the IRQ# for Ethernet! 47 - #endif 48 - 49 - #if (MICRODEV_LINUX_IRQ_USB_HC != 7) 50 - # error Inconsistancy in defining the IRQ# for USB! 51 - #endif 52 - 53 - #if (MICRODEV_LINUX_IRQ_MOUSE != 12) 54 - # error Inconsistancy in defining the IRQ# for PS/2 Mouse! 55 - #endif 56 - 57 - #if (MICRODEV_LINUX_IRQ_IDE2 != 13) 58 - # error Inconsistancy in defining the IRQ# for secondary IDE! 59 - #endif 60 - 61 - #if (MICRODEV_LINUX_IRQ_IDE1 != 14) 62 - # error Inconsistancy in defining the IRQ# for primary IDE! 63 - #endif 64 - 65 - static void disable_microdev_irq(struct irq_data *data) 66 - { 67 - unsigned int irq = data->irq; 68 - unsigned int fpgaIrq; 69 - 70 - if (irq >= NUM_EXTERNAL_IRQS) 71 - return; 72 - if (!fpgaIrqTable[irq].mapped) 73 - return; 74 - 75 - fpgaIrq = fpgaIrqTable[irq].fpgaIrq; 76 - 77 - /* disable interrupts on the FPGA INTC register */ 78 - __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); 79 - } 80 - 81 - static void enable_microdev_irq(struct irq_data *data) 82 - { 83 - unsigned int irq = data->irq; 84 - unsigned long priorityReg, priorities, pri; 85 - unsigned int fpgaIrq; 86 - 87 - if (unlikely(irq >= NUM_EXTERNAL_IRQS)) 88 - return; 89 - if (unlikely(!fpgaIrqTable[irq].mapped)) 90 - return; 91 - 92 - pri = 15 - irq; 93 - 94 - fpgaIrq = fpgaIrqTable[irq].fpgaIrq; 95 - priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq); 96 - 97 - /* set priority for the interrupt */ 98 - priorities = __raw_readl(priorityReg); 99 - priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq); 100 - priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri); 101 - __raw_writel(priorities, priorityReg); 102 - 103 - /* enable interrupts on the FPGA INTC register */ 104 - __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); 105 - } 106 - 107 - static struct irq_chip microdev_irq_type = { 108 - .name = "MicroDev-IRQ", 109 - .irq_unmask = enable_microdev_irq, 110 - .irq_mask = disable_microdev_irq, 111 - }; 112 - 113 - /* This function sets the desired irq handler to be a MicroDev type */ 114 - static void __init make_microdev_irq(unsigned int irq) 115 - { 116 - disable_irq_nosync(irq); 117 - irq_set_chip_and_handler(irq, &microdev_irq_type, handle_level_irq); 118 - disable_microdev_irq(irq_get_irq_data(irq)); 119 - } 120 - 121 - extern void __init init_microdev_irq(void) 122 - { 123 - int i; 124 - 125 - /* disable interrupts on the FPGA INTC register */ 126 - __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG); 127 - 128 - for (i = 0; i < NUM_EXTERNAL_IRQS; i++) 129 - make_microdev_irq(i); 130 - } 131 - 132 - extern void microdev_print_fpga_intc_status(void) 133 - { 134 - volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG; 135 - volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG; 136 - volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0); 137 - volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8); 138 - volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16); 139 - volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24); 140 - volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG; 141 - volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG; 142 - 143 - printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n"); 144 - printk("FPGA_INTENB = 0x%08x\n", *intenb); 145 - printk("FPGA_INTDSB = 0x%08x\n", *intdsb); 146 - printk("FPGA_INTSRC = 0x%08x\n", *intsrc); 147 - printk("FPGA_INTREQ = 0x%08x\n", *intreq); 148 - printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria); 149 - printk("-------------------------------------------------------------------------------\n"); 150 - }
-197
arch/sh/boards/mach-microdev/setup.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/boards/superh/microdev/setup.c 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * Copyright (C) 2003, 2004 SuperH, Inc. 7 - * Copyright (C) 2004, 2005 Paul Mundt 8 - * 9 - * SuperH SH4-202 MicroDev board support. 10 - */ 11 - #include <linux/init.h> 12 - #include <linux/platform_device.h> 13 - #include <linux/ioport.h> 14 - #include <video/s1d13xxxfb.h> 15 - #include <mach/microdev.h> 16 - #include <asm/io.h> 17 - #include <asm/machvec.h> 18 - #include <linux/sizes.h> 19 - 20 - static struct resource smc91x_resources[] = { 21 - [0] = { 22 - .start = 0x300, 23 - .end = 0x300 + SZ_4K - 1, 24 - .flags = IORESOURCE_MEM, 25 - }, 26 - [1] = { 27 - .start = MICRODEV_LINUX_IRQ_ETHERNET, 28 - .end = MICRODEV_LINUX_IRQ_ETHERNET, 29 - .flags = IORESOURCE_IRQ, 30 - }, 31 - }; 32 - 33 - static struct platform_device smc91x_device = { 34 - .name = "smc91x", 35 - .id = -1, 36 - .num_resources = ARRAY_SIZE(smc91x_resources), 37 - .resource = smc91x_resources, 38 - }; 39 - 40 - static struct s1d13xxxfb_regval s1d13806_initregs[] = { 41 - { S1DREG_MISC, 0x00 }, 42 - { S1DREG_COM_DISP_MODE, 0x00 }, 43 - { S1DREG_GPIO_CNF0, 0x00 }, 44 - { S1DREG_GPIO_CNF1, 0x00 }, 45 - { S1DREG_GPIO_CTL0, 0x00 }, 46 - { S1DREG_GPIO_CTL1, 0x00 }, 47 - { S1DREG_CLK_CNF, 0x02 }, 48 - { S1DREG_LCD_CLK_CNF, 0x01 }, 49 - { S1DREG_CRT_CLK_CNF, 0x03 }, 50 - { S1DREG_MPLUG_CLK_CNF, 0x03 }, 51 - { S1DREG_CPU2MEM_WST_SEL, 0x02 }, 52 - { S1DREG_SDRAM_REF_RATE, 0x03 }, 53 - { S1DREG_SDRAM_TC0, 0x00 }, 54 - { S1DREG_SDRAM_TC1, 0x01 }, 55 - { S1DREG_MEM_CNF, 0x80 }, 56 - { S1DREG_PANEL_TYPE, 0x25 }, 57 - { S1DREG_MOD_RATE, 0x00 }, 58 - { S1DREG_LCD_DISP_HWIDTH, 0x63 }, 59 - { S1DREG_LCD_NDISP_HPER, 0x1e }, 60 - { S1DREG_TFT_FPLINE_START, 0x06 }, 61 - { S1DREG_TFT_FPLINE_PWIDTH, 0x03 }, 62 - { S1DREG_LCD_DISP_VHEIGHT0, 0x57 }, 63 - { S1DREG_LCD_DISP_VHEIGHT1, 0x02 }, 64 - { S1DREG_LCD_NDISP_VPER, 0x00 }, 65 - { S1DREG_TFT_FPFRAME_START, 0x0a }, 66 - { S1DREG_TFT_FPFRAME_PWIDTH, 0x81 }, 67 - { S1DREG_LCD_DISP_MODE, 0x03 }, 68 - { S1DREG_LCD_MISC, 0x00 }, 69 - { S1DREG_LCD_DISP_START0, 0x00 }, 70 - { S1DREG_LCD_DISP_START1, 0x00 }, 71 - { S1DREG_LCD_DISP_START2, 0x00 }, 72 - { S1DREG_LCD_MEM_OFF0, 0x90 }, 73 - { S1DREG_LCD_MEM_OFF1, 0x01 }, 74 - { S1DREG_LCD_PIX_PAN, 0x00 }, 75 - { S1DREG_LCD_DISP_FIFO_HTC, 0x00 }, 76 - { S1DREG_LCD_DISP_FIFO_LTC, 0x00 }, 77 - { S1DREG_CRT_DISP_HWIDTH, 0x63 }, 78 - { S1DREG_CRT_NDISP_HPER, 0x1f }, 79 - { S1DREG_CRT_HRTC_START, 0x04 }, 80 - { S1DREG_CRT_HRTC_PWIDTH, 0x8f }, 81 - { S1DREG_CRT_DISP_VHEIGHT0, 0x57 }, 82 - { S1DREG_CRT_DISP_VHEIGHT1, 0x02 }, 83 - { S1DREG_CRT_NDISP_VPER, 0x1b }, 84 - { S1DREG_CRT_VRTC_START, 0x00 }, 85 - { S1DREG_CRT_VRTC_PWIDTH, 0x83 }, 86 - { S1DREG_TV_OUT_CTL, 0x10 }, 87 - { S1DREG_CRT_DISP_MODE, 0x05 }, 88 - { S1DREG_CRT_DISP_START0, 0x00 }, 89 - { S1DREG_CRT_DISP_START1, 0x00 }, 90 - { S1DREG_CRT_DISP_START2, 0x00 }, 91 - { S1DREG_CRT_MEM_OFF0, 0x20 }, 92 - { S1DREG_CRT_MEM_OFF1, 0x03 }, 93 - { S1DREG_CRT_PIX_PAN, 0x00 }, 94 - { S1DREG_CRT_DISP_FIFO_HTC, 0x00 }, 95 - { S1DREG_CRT_DISP_FIFO_LTC, 0x00 }, 96 - { S1DREG_LCD_CUR_CTL, 0x00 }, 97 - { S1DREG_LCD_CUR_START, 0x01 }, 98 - { S1DREG_LCD_CUR_XPOS0, 0x00 }, 99 - { S1DREG_LCD_CUR_XPOS1, 0x00 }, 100 - { S1DREG_LCD_CUR_YPOS0, 0x00 }, 101 - { S1DREG_LCD_CUR_YPOS1, 0x00 }, 102 - { S1DREG_LCD_CUR_BCTL0, 0x00 }, 103 - { S1DREG_LCD_CUR_GCTL0, 0x00 }, 104 - { S1DREG_LCD_CUR_RCTL0, 0x00 }, 105 - { S1DREG_LCD_CUR_BCTL1, 0x1f }, 106 - { S1DREG_LCD_CUR_GCTL1, 0x3f }, 107 - { S1DREG_LCD_CUR_RCTL1, 0x1f }, 108 - { S1DREG_LCD_CUR_FIFO_HTC, 0x00 }, 109 - { S1DREG_CRT_CUR_CTL, 0x00 }, 110 - { S1DREG_CRT_CUR_START, 0x01 }, 111 - { S1DREG_CRT_CUR_XPOS0, 0x00 }, 112 - { S1DREG_CRT_CUR_XPOS1, 0x00 }, 113 - { S1DREG_CRT_CUR_YPOS0, 0x00 }, 114 - { S1DREG_CRT_CUR_YPOS1, 0x00 }, 115 - { S1DREG_CRT_CUR_BCTL0, 0x00 }, 116 - { S1DREG_CRT_CUR_GCTL0, 0x00 }, 117 - { S1DREG_CRT_CUR_RCTL0, 0x00 }, 118 - { S1DREG_CRT_CUR_BCTL1, 0x1f }, 119 - { S1DREG_CRT_CUR_GCTL1, 0x3f }, 120 - { S1DREG_CRT_CUR_RCTL1, 0x1f }, 121 - { S1DREG_CRT_CUR_FIFO_HTC, 0x00 }, 122 - { S1DREG_BBLT_CTL0, 0x00 }, 123 - { S1DREG_BBLT_CTL1, 0x00 }, 124 - { S1DREG_BBLT_CC_EXP, 0x00 }, 125 - { S1DREG_BBLT_OP, 0x00 }, 126 - { S1DREG_BBLT_SRC_START0, 0x00 }, 127 - { S1DREG_BBLT_SRC_START1, 0x00 }, 128 - { S1DREG_BBLT_SRC_START2, 0x00 }, 129 - { S1DREG_BBLT_DST_START0, 0x00 }, 130 - { S1DREG_BBLT_DST_START1, 0x00 }, 131 - { S1DREG_BBLT_DST_START2, 0x00 }, 132 - { S1DREG_BBLT_MEM_OFF0, 0x00 }, 133 - { S1DREG_BBLT_MEM_OFF1, 0x00 }, 134 - { S1DREG_BBLT_WIDTH0, 0x00 }, 135 - { S1DREG_BBLT_WIDTH1, 0x00 }, 136 - { S1DREG_BBLT_HEIGHT0, 0x00 }, 137 - { S1DREG_BBLT_HEIGHT1, 0x00 }, 138 - { S1DREG_BBLT_BGC0, 0x00 }, 139 - { S1DREG_BBLT_BGC1, 0x00 }, 140 - { S1DREG_BBLT_FGC0, 0x00 }, 141 - { S1DREG_BBLT_FGC1, 0x00 }, 142 - { S1DREG_LKUP_MODE, 0x00 }, 143 - { S1DREG_LKUP_ADDR, 0x00 }, 144 - { S1DREG_PS_CNF, 0x10 }, 145 - { S1DREG_PS_STATUS, 0x00 }, 146 - { S1DREG_CPU2MEM_WDOGT, 0x00 }, 147 - { S1DREG_COM_DISP_MODE, 0x02 }, 148 - }; 149 - 150 - static struct s1d13xxxfb_pdata s1d13806_platform_data = { 151 - .initregs = s1d13806_initregs, 152 - .initregssize = ARRAY_SIZE(s1d13806_initregs), 153 - }; 154 - 155 - static struct resource s1d13806_resources[] = { 156 - [0] = { 157 - .start = 0x07200000, 158 - .end = 0x07200000 + SZ_2M - 1, 159 - .flags = IORESOURCE_MEM, 160 - }, 161 - [1] = { 162 - .start = 0x07000000, 163 - .end = 0x07000000 + SZ_2M - 1, 164 - .flags = IORESOURCE_MEM, 165 - }, 166 - }; 167 - 168 - static struct platform_device s1d13806_device = { 169 - .name = "s1d13806fb", 170 - .id = -1, 171 - .num_resources = ARRAY_SIZE(s1d13806_resources), 172 - .resource = s1d13806_resources, 173 - 174 - .dev = { 175 - .platform_data = &s1d13806_platform_data, 176 - }, 177 - }; 178 - 179 - static struct platform_device *microdev_devices[] __initdata = { 180 - &smc91x_device, 181 - &s1d13806_device, 182 - }; 183 - 184 - static int __init microdev_devices_setup(void) 185 - { 186 - return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); 187 - } 188 - device_initcall(microdev_devices_setup); 189 - 190 - /* 191 - * The Machine Vector 192 - */ 193 - static struct sh_machine_vector mv_sh4202_microdev __initmv = { 194 - .mv_name = "SH4-202 MicroDev", 195 - .mv_ioport_map = microdev_ioport_map, 196 - .mv_init_irq = init_microdev_irq, 197 - };
-42
arch/sh/configs/microdev_defconfig
··· 1 - CONFIG_BSD_PROCESS_ACCT=y 2 - CONFIG_LOG_BUF_SHIFT=14 3 - CONFIG_BLK_DEV_INITRD=y 4 - # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 5 - # CONFIG_BLK_DEV_BSG is not set 6 - CONFIG_CPU_SUBTYPE_SH4_202=y 7 - CONFIG_FLATMEM_MANUAL=y 8 - CONFIG_SH_SH4202_MICRODEV=y 9 - CONFIG_SH_DMA=y 10 - CONFIG_SH_DMA_API=y 11 - CONFIG_HEARTBEAT=y 12 - CONFIG_PREEMPT=y 13 - CONFIG_CMDLINE_OVERWRITE=y 14 - CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/hda1" 15 - CONFIG_SUPERHYWAY=y 16 - CONFIG_NET=y 17 - CONFIG_INET=y 18 - CONFIG_IP_PNP=y 19 - # CONFIG_IPV6 is not set 20 - # CONFIG_FW_LOADER is not set 21 - CONFIG_BLK_DEV_RAM=y 22 - CONFIG_NETDEVICES=y 23 - CONFIG_NET_ETHERNET=y 24 - CONFIG_SMC91X=y 25 - # CONFIG_INPUT is not set 26 - # CONFIG_SERIO is not set 27 - # CONFIG_VT is not set 28 - CONFIG_SERIAL_SH_SCI=y 29 - CONFIG_SERIAL_SH_SCI_CONSOLE=y 30 - CONFIG_EXT2_FS=y 31 - CONFIG_EXT3_FS=y 32 - # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 33 - CONFIG_VFAT_FS=y 34 - CONFIG_PROC_KCORE=y 35 - CONFIG_TMPFS=y 36 - CONFIG_HUGETLBFS=y 37 - CONFIG_NFS_FS=y 38 - CONFIG_NFS_V3=y 39 - CONFIG_NFS_V4=y 40 - CONFIG_ROOT_NFS=y 41 - CONFIG_CRYPTO_ECB=y 42 - # CONFIG_CRYPTO_ANSI_CPRNG is not set
-1
arch/sh/drivers/Makefile
··· 6 6 obj-y += dma/ platform_early.o 7 7 8 8 obj-$(CONFIG_PCI) += pci/ 9 - obj-$(CONFIG_SUPERHYWAY) += superhyway/ 10 9 obj-$(CONFIG_PUSH_SWITCH) += push-switch.o 11 10 obj-$(CONFIG_HEARTBEAT) += heartbeat.o
-7
arch/sh/drivers/superhyway/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # Makefile for the SuperHyway specific kernel interface routines under Linux. 4 - # 5 - 6 - obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += ops-sh4-202.o 7 -
-168
arch/sh/drivers/superhyway/ops-sh4-202.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/drivers/superhyway/ops-sh4-202.c 4 - * 5 - * SuperHyway bus support for SH4-202 6 - * 7 - * Copyright (C) 2005 Paul Mundt 8 - */ 9 - #include <linux/kernel.h> 10 - #include <linux/init.h> 11 - #include <linux/superhyway.h> 12 - #include <linux/string.h> 13 - #include <asm/addrspace.h> 14 - #include <asm/io.h> 15 - 16 - #define PHYS_EMI_CBLOCK P4SEGADDR(0x1ec00000) 17 - #define PHYS_EMI_DBLOCK P4SEGADDR(0x08000000) 18 - #define PHYS_FEMI_CBLOCK P4SEGADDR(0x1f800000) 19 - #define PHYS_FEMI_DBLOCK P4SEGADDR(0x00000000) 20 - 21 - #define PHYS_EPBR_BLOCK P4SEGADDR(0x1de00000) 22 - #define PHYS_DMAC_BLOCK P4SEGADDR(0x1fa00000) 23 - #define PHYS_PBR_BLOCK P4SEGADDR(0x1fc00000) 24 - 25 - static struct resource emi_resources[] = { 26 - [0] = { 27 - .start = PHYS_EMI_CBLOCK, 28 - .end = PHYS_EMI_CBLOCK + 0x00300000 - 1, 29 - .flags = IORESOURCE_MEM, 30 - }, 31 - [1] = { 32 - .start = PHYS_EMI_DBLOCK, 33 - .end = PHYS_EMI_DBLOCK + 0x08000000 - 1, 34 - .flags = IORESOURCE_MEM, 35 - }, 36 - }; 37 - 38 - static struct superhyway_device emi_device = { 39 - .name = "emi", 40 - .num_resources = ARRAY_SIZE(emi_resources), 41 - .resource = emi_resources, 42 - }; 43 - 44 - static struct resource femi_resources[] = { 45 - [0] = { 46 - .start = PHYS_FEMI_CBLOCK, 47 - .end = PHYS_FEMI_CBLOCK + 0x00100000 - 1, 48 - .flags = IORESOURCE_MEM, 49 - }, 50 - [1] = { 51 - .start = PHYS_FEMI_DBLOCK, 52 - .end = PHYS_FEMI_DBLOCK + 0x08000000 - 1, 53 - .flags = IORESOURCE_MEM, 54 - }, 55 - }; 56 - 57 - static struct superhyway_device femi_device = { 58 - .name = "femi", 59 - .num_resources = ARRAY_SIZE(femi_resources), 60 - .resource = femi_resources, 61 - }; 62 - 63 - static struct resource epbr_resources[] = { 64 - [0] = { 65 - .start = P4SEGADDR(0x1e7ffff8), 66 - .end = P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1), 67 - .flags = IORESOURCE_MEM, 68 - }, 69 - [1] = { 70 - .start = PHYS_EPBR_BLOCK, 71 - .end = PHYS_EPBR_BLOCK + 0x00a00000 - 1, 72 - .flags = IORESOURCE_MEM, 73 - }, 74 - }; 75 - 76 - static struct superhyway_device epbr_device = { 77 - .name = "epbr", 78 - .num_resources = ARRAY_SIZE(epbr_resources), 79 - .resource = epbr_resources, 80 - }; 81 - 82 - static struct resource dmac_resource = { 83 - .start = PHYS_DMAC_BLOCK, 84 - .end = PHYS_DMAC_BLOCK + 0x00100000 - 1, 85 - .flags = IORESOURCE_MEM, 86 - }; 87 - 88 - static struct superhyway_device dmac_device = { 89 - .name = "dmac", 90 - .num_resources = 1, 91 - .resource = &dmac_resource, 92 - }; 93 - 94 - static struct resource pbr_resources[] = { 95 - [0] = { 96 - .start = P4SEGADDR(0x1ffffff8), 97 - .end = P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1), 98 - .flags = IORESOURCE_MEM, 99 - }, 100 - [1] = { 101 - .start = PHYS_PBR_BLOCK, 102 - .end = PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1, 103 - .flags = IORESOURCE_MEM, 104 - }, 105 - }; 106 - 107 - static struct superhyway_device pbr_device = { 108 - .name = "pbr", 109 - .num_resources = ARRAY_SIZE(pbr_resources), 110 - .resource = pbr_resources, 111 - }; 112 - 113 - static struct superhyway_device *sh4202_devices[] __initdata = { 114 - &emi_device, &femi_device, &epbr_device, &dmac_device, &pbr_device, 115 - }; 116 - 117 - static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr) 118 - { 119 - u32 vcrh, vcrl; 120 - u64 tmp; 121 - 122 - /* 123 - * XXX: Even though the SH4-202 Evaluation Device documentation 124 - * indicates that VCRL is mapped first with VCRH at a + 0x04 125 - * offset, the opposite seems to be true. 126 - * 127 - * Some modules (PBR and ePBR for instance) also appear to have 128 - * VCRL/VCRH flipped in the documentation, but on the SH4-202 129 - * itself it appears that these are all consistently mapped with 130 - * VCRH preceding VCRL. 131 - * 132 - * Do not trust the documentation, for it is evil. 133 - */ 134 - vcrh = __raw_readl(base); 135 - vcrl = __raw_readl(base + sizeof(u32)); 136 - 137 - tmp = ((u64)vcrh << 32) | vcrl; 138 - memcpy(vcr, &tmp, sizeof(u64)); 139 - 140 - return 0; 141 - } 142 - 143 - static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr) 144 - { 145 - u64 tmp = *(u64 *)&vcr; 146 - 147 - __raw_writel((tmp >> 32) & 0xffffffff, base); 148 - __raw_writel(tmp & 0xffffffff, base + sizeof(u32)); 149 - 150 - return 0; 151 - } 152 - 153 - static struct superhyway_ops sh4202_superhyway_ops = { 154 - .read_vcr = sh4202_read_vcr, 155 - .write_vcr = sh4202_write_vcr, 156 - }; 157 - 158 - struct superhyway_bus superhyway_channels[] = { 159 - { &sh4202_superhyway_ops, }, 160 - { 0, }, 161 - }; 162 - 163 - int __init superhyway_scan_bus(struct superhyway_bus *bus) 164 - { 165 - return superhyway_add_devices(bus, sh4202_devices, 166 - ARRAY_SIZE(sh4202_devices)); 167 - } 168 -
+9
arch/sh/include/asm/cmpxchg.h
··· 71 71 (unsigned long)_n_, sizeof(*(ptr))); \ 72 72 }) 73 73 74 + #include <asm-generic/cmpxchg-local.h> 75 + 76 + #define arch_cmpxchg_local(ptr, o, n) ({ \ 77 + (__typeof__(*ptr))__generic_cmpxchg_local((ptr), \ 78 + (unsigned long)(o), \ 79 + (unsigned long)(n), \ 80 + sizeof(*(ptr))); \ 81 + }) 82 + 74 83 #endif /* __ASM_SH_CMPXCHG_H */
+2 -2
arch/sh/include/asm/io.h
··· 181 181 { \ 182 182 volatile type *__addr; \ 183 183 \ 184 - __addr = __ioport_map(port, sizeof(type)); \ 184 + __addr = (void __iomem *)sh_io_port_base + port; \ 185 185 *__addr = val; \ 186 186 slow; \ 187 187 } \ ··· 191 191 volatile type *__addr; \ 192 192 type __val; \ 193 193 \ 194 - __addr = __ioport_map(port, sizeof(type)); \ 194 + __addr = (void __iomem *)sh_io_port_base + port; \ 195 195 __val = *__addr; \ 196 196 slow; \ 197 197 \
-5
arch/sh/include/asm/machvec.h
··· 19 19 int (*mv_irq_demux)(int irq); 20 20 void (*mv_init_irq)(void); 21 21 22 - #ifdef CONFIG_HAS_IOPORT_MAP 23 - void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); 24 - void (*mv_ioport_unmap)(void __iomem *); 25 - #endif 26 - 27 22 int (*mv_clk_init)(void); 28 23 int (*mv_mode_pins)(void); 29 24
-69
arch/sh/include/mach-common/mach/microdev.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 2 - * 3 - * linux/include/asm-sh/microdev.h 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * 7 - * Definitions for the SuperH SH4-202 MicroDev board. 8 - */ 9 - #ifndef __ASM_SH_MICRODEV_H 10 - #define __ASM_SH_MICRODEV_H 11 - 12 - extern void init_microdev_irq(void); 13 - extern void microdev_print_fpga_intc_status(void); 14 - 15 - /* 16 - * The following are useful macros for manipulating the interrupt 17 - * controller (INTC) on the CPU-board FPGA. should be noted that there 18 - * is an INTC on the FPGA, and a separate INTC on the SH4-202 core - 19 - * these are two different things, both of which need to be prorammed to 20 - * correctly route - unfortunately, they have the same name and 21 - * abbreviations! 22 - */ 23 - #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ 24 - #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ 25 - #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ 26 - #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */ 27 - #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ 28 - #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ 29 - #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ 30 - #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ 31 - #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ 32 - 33 - 34 - /* 35 - * The following are the IRQ numbers for the Linux Kernel for external 36 - * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'. 37 - */ 38 - #define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ 39 - #define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ 40 - #define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ 41 - #define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ 42 - #define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ 43 - #define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ 44 - #define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ 45 - #define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ 46 - 47 - /* 48 - * The following are the IRQ numbers for the INTC on the FPGA for 49 - * external interrupts. i.e. the bits in the INTC registers in the 50 - * FPGA. 51 - */ 52 - #define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ 53 - #define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ 54 - #define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ 55 - #define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ 56 - #define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ 57 - #define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ 58 - #define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ 59 - #define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ 60 - 61 - #define MICRODEV_IRQ_PCI_INTA 8 62 - #define MICRODEV_IRQ_PCI_INTB 9 63 - #define MICRODEV_IRQ_PCI_INTC 10 64 - #define MICRODEV_IRQ_PCI_INTD 11 65 - 66 - #define __IO_PREFIX microdev 67 - #include <asm/io_generic.h> 68 - 69 - #endif /* __ASM_SH_MICRODEV_H */
-4
arch/sh/kernel/cpu/sh4/Makefile
··· 23 23 obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o 24 24 obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += setup-sh7750.o 25 25 obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o 26 - obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o 27 26 28 27 # Primary on-chip clocks (common) 29 28 ifndef CONFIG_CPU_SH4A 30 29 clock-$(CONFIG_CPU_SH4) := clock-sh4.o 31 30 endif 32 - 33 - # Additional clocks by subtype 34 - clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o 35 31 36 32 obj-y += $(clock-y) 37 33 obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
-174
arch/sh/kernel/cpu/sh4/clock-sh4-202.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/kernel/cpu/sh4/clock-sh4-202.c 4 - * 5 - * Additional SH4-202 support for the clock framework 6 - * 7 - * Copyright (C) 2005 Paul Mundt 8 - */ 9 - #include <linux/init.h> 10 - #include <linux/kernel.h> 11 - #include <linux/err.h> 12 - #include <linux/io.h> 13 - #include <linux/clkdev.h> 14 - #include <asm/clock.h> 15 - #include <asm/freq.h> 16 - 17 - #define CPG2_FRQCR3 0xfe0a0018 18 - 19 - static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; 20 - static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; 21 - 22 - static unsigned long emi_clk_recalc(struct clk *clk) 23 - { 24 - int idx = __raw_readl(CPG2_FRQCR3) & 0x0007; 25 - return clk->parent->rate / frqcr3_divisors[idx]; 26 - } 27 - 28 - static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) 29 - { 30 - int divisor = clk->parent->rate / rate; 31 - int i; 32 - 33 - for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) 34 - if (frqcr3_divisors[i] == divisor) 35 - return frqcr3_values[i]; 36 - 37 - /* Safe fallback */ 38 - return 5; 39 - } 40 - 41 - static struct sh_clk_ops sh4202_emi_clk_ops = { 42 - .recalc = emi_clk_recalc, 43 - }; 44 - 45 - static struct clk sh4202_emi_clk = { 46 - .flags = CLK_ENABLE_ON_INIT, 47 - .ops = &sh4202_emi_clk_ops, 48 - }; 49 - 50 - static unsigned long femi_clk_recalc(struct clk *clk) 51 - { 52 - int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007; 53 - return clk->parent->rate / frqcr3_divisors[idx]; 54 - } 55 - 56 - static struct sh_clk_ops sh4202_femi_clk_ops = { 57 - .recalc = femi_clk_recalc, 58 - }; 59 - 60 - static struct clk sh4202_femi_clk = { 61 - .flags = CLK_ENABLE_ON_INIT, 62 - .ops = &sh4202_femi_clk_ops, 63 - }; 64 - 65 - static void shoc_clk_init(struct clk *clk) 66 - { 67 - int i; 68 - 69 - /* 70 - * For some reason, the shoc_clk seems to be set to some really 71 - * insane value at boot (values outside of the allowable frequency 72 - * range for instance). We deal with this by scaling it back down 73 - * to something sensible just in case. 74 - * 75 - * Start scaling from the high end down until we find something 76 - * that passes rate verification.. 77 - */ 78 - for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) { 79 - int divisor = frqcr3_divisors[i]; 80 - 81 - if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) 82 - break; 83 - } 84 - 85 - WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ 86 - } 87 - 88 - static unsigned long shoc_clk_recalc(struct clk *clk) 89 - { 90 - int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007; 91 - return clk->parent->rate / frqcr3_divisors[idx]; 92 - } 93 - 94 - static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) 95 - { 96 - struct clk *bclk = clk_get(NULL, "bus_clk"); 97 - unsigned long bclk_rate = clk_get_rate(bclk); 98 - 99 - clk_put(bclk); 100 - 101 - if (rate > bclk_rate) 102 - return 1; 103 - if (rate > 66000000) 104 - return 1; 105 - 106 - return 0; 107 - } 108 - 109 - static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) 110 - { 111 - unsigned long frqcr3; 112 - unsigned int tmp; 113 - 114 - /* Make sure we have something sensible to switch to */ 115 - if (shoc_clk_verify_rate(clk, rate) != 0) 116 - return -EINVAL; 117 - 118 - tmp = frqcr3_lookup(clk, rate); 119 - 120 - frqcr3 = __raw_readl(CPG2_FRQCR3); 121 - frqcr3 &= ~(0x0007 << 6); 122 - frqcr3 |= tmp << 6; 123 - __raw_writel(frqcr3, CPG2_FRQCR3); 124 - 125 - clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; 126 - 127 - return 0; 128 - } 129 - 130 - static struct sh_clk_ops sh4202_shoc_clk_ops = { 131 - .init = shoc_clk_init, 132 - .recalc = shoc_clk_recalc, 133 - .set_rate = shoc_clk_set_rate, 134 - }; 135 - 136 - static struct clk sh4202_shoc_clk = { 137 - .flags = CLK_ENABLE_ON_INIT, 138 - .ops = &sh4202_shoc_clk_ops, 139 - }; 140 - 141 - static struct clk *sh4202_onchip_clocks[] = { 142 - &sh4202_emi_clk, 143 - &sh4202_femi_clk, 144 - &sh4202_shoc_clk, 145 - }; 146 - 147 - static struct clk_lookup lookups[] = { 148 - /* main clocks */ 149 - CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk), 150 - CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk), 151 - CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk), 152 - }; 153 - 154 - int __init arch_clk_init(void) 155 - { 156 - struct clk *clk; 157 - int i, ret = 0; 158 - 159 - cpg_clk_init(); 160 - 161 - clk = clk_get(NULL, "master_clk"); 162 - for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) { 163 - struct clk *clkp = sh4202_onchip_clocks[i]; 164 - 165 - clkp->parent = clk; 166 - ret |= clk_register(clkp); 167 - } 168 - 169 - clk_put(clk); 170 - 171 - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 172 - 173 - return ret; 174 - }
-139
arch/sh/kernel/cpu/sh4/setup-sh4-202.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * SH4-202 Setup 4 - * 5 - * Copyright (C) 2006 Paul Mundt 6 - * Copyright (C) 2009 Magnus Damm 7 - */ 8 - #include <linux/platform_device.h> 9 - #include <linux/init.h> 10 - #include <linux/serial.h> 11 - #include <linux/serial_sci.h> 12 - #include <linux/sh_timer.h> 13 - #include <linux/sh_intc.h> 14 - #include <linux/io.h> 15 - #include <asm/platform_early.h> 16 - 17 - static struct plat_sci_port scif0_platform_data = { 18 - .scscr = SCSCR_REIE, 19 - .type = PORT_SCIF, 20 - }; 21 - 22 - static struct resource scif0_resources[] = { 23 - DEFINE_RES_MEM(0xffe80000, 0x100), 24 - DEFINE_RES_IRQ(evt2irq(0x700)), 25 - DEFINE_RES_IRQ(evt2irq(0x720)), 26 - DEFINE_RES_IRQ(evt2irq(0x760)), 27 - DEFINE_RES_IRQ(evt2irq(0x740)), 28 - }; 29 - 30 - static struct platform_device scif0_device = { 31 - .name = "sh-sci", 32 - .id = 0, 33 - .resource = scif0_resources, 34 - .num_resources = ARRAY_SIZE(scif0_resources), 35 - .dev = { 36 - .platform_data = &scif0_platform_data, 37 - }, 38 - }; 39 - 40 - static struct sh_timer_config tmu0_platform_data = { 41 - .channels_mask = 7, 42 - }; 43 - 44 - static struct resource tmu0_resources[] = { 45 - DEFINE_RES_MEM(0xffd80000, 0x30), 46 - DEFINE_RES_IRQ(evt2irq(0x400)), 47 - DEFINE_RES_IRQ(evt2irq(0x420)), 48 - DEFINE_RES_IRQ(evt2irq(0x440)), 49 - }; 50 - 51 - static struct platform_device tmu0_device = { 52 - .name = "sh-tmu", 53 - .id = 0, 54 - .dev = { 55 - .platform_data = &tmu0_platform_data, 56 - }, 57 - .resource = tmu0_resources, 58 - .num_resources = ARRAY_SIZE(tmu0_resources), 59 - }; 60 - 61 - static struct platform_device *sh4202_devices[] __initdata = { 62 - &scif0_device, 63 - &tmu0_device, 64 - }; 65 - 66 - static int __init sh4202_devices_setup(void) 67 - { 68 - return platform_add_devices(sh4202_devices, 69 - ARRAY_SIZE(sh4202_devices)); 70 - } 71 - arch_initcall(sh4202_devices_setup); 72 - 73 - static struct platform_device *sh4202_early_devices[] __initdata = { 74 - &scif0_device, 75 - &tmu0_device, 76 - }; 77 - 78 - void __init plat_early_device_setup(void) 79 - { 80 - sh_early_platform_add_devices(sh4202_early_devices, 81 - ARRAY_SIZE(sh4202_early_devices)); 82 - } 83 - 84 - enum { 85 - UNUSED = 0, 86 - 87 - /* interrupt sources */ 88 - IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 89 - HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, 90 - }; 91 - 92 - static struct intc_vect vectors[] __initdata = { 93 - INTC_VECT(HUDI, 0x600), 94 - INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 95 - INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 96 - INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 97 - INTC_VECT(RTC, 0x4c0), 98 - INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 99 - INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 100 - INTC_VECT(WDT, 0x560), 101 - }; 102 - 103 - static struct intc_prio_reg prio_registers[] __initdata = { 104 - { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 105 - { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } }, 106 - { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } }, 107 - { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 108 - }; 109 - 110 - static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL, 111 - NULL, prio_registers, NULL); 112 - 113 - static struct intc_vect vectors_irlm[] __initdata = { 114 - INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 115 - INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 116 - }; 117 - 118 - static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL, 119 - NULL, prio_registers, NULL); 120 - 121 - void __init plat_irq_setup(void) 122 - { 123 - register_intc_controller(&intc_desc); 124 - } 125 - 126 - #define INTC_ICR 0xffd00000UL 127 - #define INTC_ICR_IRLM (1<<7) 128 - 129 - void __init plat_irq_setup_pins(int mode) 130 - { 131 - switch (mode) { 132 - case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 133 - __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 134 - register_intc_controller(&intc_desc_irlm); 135 - break; 136 - default: 137 - BUG(); 138 - } 139 - }
+1 -12
arch/sh/kernel/ioport.c
··· 12 12 unsigned long sh_io_port_base __read_mostly = -1; 13 13 EXPORT_SYMBOL(sh_io_port_base); 14 14 15 - void __iomem *__ioport_map(unsigned long addr, unsigned int size) 16 - { 17 - if (sh_mv.mv_ioport_map) 18 - return sh_mv.mv_ioport_map(addr, size); 19 - 20 - return (void __iomem *)(addr + sh_io_port_base); 21 - } 22 - EXPORT_SYMBOL(__ioport_map); 23 - 24 15 void __iomem *ioport_map(unsigned long port, unsigned int nr) 25 16 { 26 17 void __iomem *ret; ··· 20 29 if (ret) 21 30 return ret; 22 31 23 - return __ioport_map(port, nr); 32 + return (void __iomem *)(port + sh_io_port_base); 24 33 } 25 34 EXPORT_SYMBOL(ioport_map); 26 35 27 36 void ioport_unmap(void __iomem *addr) 28 37 { 29 - if (sh_mv.mv_ioport_unmap) 30 - sh_mv.mv_ioport_unmap(addr); 31 38 } 32 39 EXPORT_SYMBOL(ioport_unmap);
-19
drivers/net/ethernet/smsc/smc91x.h
··· 114 114 (lp)->cfg.pxa_u16_align4) 115 115 116 116 117 - #elif defined(CONFIG_SH_SH4202_MICRODEV) 118 - 119 - #define SMC_CAN_USE_8BIT 0 120 - #define SMC_CAN_USE_16BIT 1 121 - #define SMC_CAN_USE_32BIT 0 122 - 123 - #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) 124 - #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) 125 - #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) 126 - #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) 127 - #define SMC_outw(lp, v, a, r) outw(v, (a) + (r) - 0xa0000000) 128 - #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) 129 - #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) 130 - #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) 131 - #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) 132 - #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) 133 - 134 - #define SMC_IRQ_FLAGS (0) 135 - 136 117 #elif defined(CONFIG_ATARI) 137 118 138 119 #define SMC_CAN_USE_8BIT 1
-1
drivers/sh/Makefile
··· 7 7 obj-$(CONFIG_HAVE_CLK) += clk/ 8 8 endif 9 9 obj-$(CONFIG_MAPLE) += maple/ 10 - obj-$(CONFIG_SUPERHYWAY) += superhyway/ 11 10 12 11 obj-y += pm_runtime.o
-8
drivers/sh/superhyway/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - # 3 - # Makefile for the SuperHyway bus drivers. 4 - # 5 - 6 - obj-$(CONFIG_SUPERHYWAY) += superhyway.o 7 - obj-$(CONFIG_SYSFS) += superhyway-sysfs.o 8 -
-54
drivers/sh/superhyway/superhyway-sysfs.c
··· 1 - /* 2 - * drivers/sh/superhyway/superhyway-sysfs.c 3 - * 4 - * SuperHyway Bus sysfs interface 5 - * 6 - * Copyright (C) 2004, 2005 Paul Mundt <lethal@linux-sh.org> 7 - * 8 - * This file is subject to the terms and conditions of the GNU General Public 9 - * License. See the file "COPYING" in the main directory of this archive 10 - * for more details. 11 - */ 12 - #include <linux/kernel.h> 13 - #include <linux/device.h> 14 - #include <linux/types.h> 15 - #include <linux/superhyway.h> 16 - 17 - #define superhyway_ro_attr(name, fmt, field) \ 18 - static ssize_t name##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 19 - { \ 20 - struct superhyway_device *s = to_superhyway_device(dev); \ 21 - return sprintf(buf, fmt, s->field); \ 22 - } \ 23 - static DEVICE_ATTR_RO(name); 24 - 25 - /* VCR flags */ 26 - superhyway_ro_attr(perr_flags, "0x%02x\n", vcr.perr_flags); 27 - superhyway_ro_attr(merr_flags, "0x%02x\n", vcr.merr_flags); 28 - superhyway_ro_attr(mod_vers, "0x%04x\n", vcr.mod_vers); 29 - superhyway_ro_attr(mod_id, "0x%04x\n", vcr.mod_id); 30 - superhyway_ro_attr(bot_mb, "0x%02x\n", vcr.bot_mb); 31 - superhyway_ro_attr(top_mb, "0x%02x\n", vcr.top_mb); 32 - 33 - /* Misc */ 34 - superhyway_ro_attr(resource, "0x%08lx\n", resource[0].start); 35 - 36 - static struct attribute *superhyway_dev_attrs[] = { 37 - &dev_attr_perr_flags.attr, 38 - &dev_attr_merr_flags.attr, 39 - &dev_attr_mod_vers.attr, 40 - &dev_attr_mod_id.attr, 41 - &dev_attr_bot_mb.attr, 42 - &dev_attr_top_mb.attr, 43 - &dev_attr_resource.attr, 44 - NULL, 45 - }; 46 - 47 - static const struct attribute_group superhyway_dev_group = { 48 - .attrs = superhyway_dev_attrs, 49 - }; 50 - 51 - const struct attribute_group *superhyway_dev_groups[] = { 52 - &superhyway_dev_group, 53 - NULL, 54 - };
-234
drivers/sh/superhyway/superhyway.c
··· 1 - /* 2 - * drivers/sh/superhyway/superhyway.c 3 - * 4 - * SuperHyway Bus Driver 5 - * 6 - * Copyright (C) 2004, 2005 Paul Mundt <lethal@linux-sh.org> 7 - * 8 - * This file is subject to the terms and conditions of the GNU General Public 9 - * License. See the file "COPYING" in the main directory of this archive 10 - * for more details. 11 - */ 12 - #include <linux/kernel.h> 13 - #include <linux/device.h> 14 - #include <linux/init.h> 15 - #include <linux/module.h> 16 - #include <linux/types.h> 17 - #include <linux/list.h> 18 - #include <linux/superhyway.h> 19 - #include <linux/string.h> 20 - #include <linux/slab.h> 21 - 22 - static int superhyway_devices; 23 - 24 - static struct device superhyway_bus_device = { 25 - .init_name = "superhyway", 26 - }; 27 - 28 - static void superhyway_device_release(struct device *dev) 29 - { 30 - struct superhyway_device *sdev = to_superhyway_device(dev); 31 - 32 - kfree(sdev->resource); 33 - kfree(sdev); 34 - } 35 - 36 - /** 37 - * superhyway_add_device - Add a SuperHyway module 38 - * @base: Physical address where module is mapped. 39 - * @sdev: SuperHyway device to add, or NULL to allocate a new one. 40 - * @bus: Bus where SuperHyway module resides. 41 - * 42 - * This is responsible for adding a new SuperHyway module. This sets up a new 43 - * struct superhyway_device for the module being added if @sdev == NULL. 44 - * 45 - * Devices are initially added in the order that they are scanned (from the 46 - * top-down of the memory map), and are assigned an ID based on the order that 47 - * they are added. Any manual addition of a module will thus get the ID after 48 - * the devices already discovered regardless of where it resides in memory. 49 - * 50 - * Further work can and should be done in superhyway_scan_bus(), to be sure 51 - * that any new modules are properly discovered and subsequently registered. 52 - */ 53 - int superhyway_add_device(unsigned long base, struct superhyway_device *sdev, 54 - struct superhyway_bus *bus) 55 - { 56 - struct superhyway_device *dev = sdev; 57 - 58 - if (!dev) { 59 - dev = kzalloc(sizeof(struct superhyway_device), GFP_KERNEL); 60 - if (!dev) 61 - return -ENOMEM; 62 - 63 - } 64 - 65 - dev->bus = bus; 66 - superhyway_read_vcr(dev, base, &dev->vcr); 67 - 68 - if (!dev->resource) { 69 - dev->resource = kzalloc(sizeof(struct resource), GFP_KERNEL); 70 - if (!dev->resource) { 71 - kfree(dev); 72 - return -ENOMEM; 73 - } 74 - 75 - dev->resource->name = dev->name; 76 - dev->resource->start = base; 77 - dev->resource->end = dev->resource->start + 0x01000000; 78 - } 79 - 80 - dev->dev.parent = &superhyway_bus_device; 81 - dev->dev.bus = &superhyway_bus_type; 82 - dev->dev.release = superhyway_device_release; 83 - dev->id.id = dev->vcr.mod_id; 84 - 85 - sprintf(dev->name, "SuperHyway device %04x", dev->id.id); 86 - dev_set_name(&dev->dev, "%02x", superhyway_devices); 87 - 88 - superhyway_devices++; 89 - 90 - return device_register(&dev->dev); 91 - } 92 - 93 - int superhyway_add_devices(struct superhyway_bus *bus, 94 - struct superhyway_device **devices, 95 - int nr_devices) 96 - { 97 - int i, ret = 0; 98 - 99 - for (i = 0; i < nr_devices; i++) { 100 - struct superhyway_device *dev = devices[i]; 101 - ret |= superhyway_add_device(dev->resource[0].start, dev, bus); 102 - } 103 - 104 - return ret; 105 - } 106 - 107 - static int __init superhyway_init(void) 108 - { 109 - struct superhyway_bus *bus; 110 - int ret; 111 - 112 - ret = device_register(&superhyway_bus_device); 113 - if (unlikely(ret)) 114 - return ret; 115 - 116 - for (bus = superhyway_channels; bus->ops; bus++) 117 - ret |= superhyway_scan_bus(bus); 118 - 119 - return ret; 120 - } 121 - postcore_initcall(superhyway_init); 122 - 123 - static const struct superhyway_device_id * 124 - superhyway_match_id(const struct superhyway_device_id *ids, 125 - struct superhyway_device *dev) 126 - { 127 - while (ids->id) { 128 - if (ids->id == dev->id.id) 129 - return ids; 130 - 131 - ids++; 132 - } 133 - 134 - return NULL; 135 - } 136 - 137 - static int superhyway_device_probe(struct device *dev) 138 - { 139 - struct superhyway_device *shyway_dev = to_superhyway_device(dev); 140 - struct superhyway_driver *shyway_drv = to_superhyway_driver(dev->driver); 141 - 142 - if (shyway_drv && shyway_drv->probe) { 143 - const struct superhyway_device_id *id; 144 - 145 - id = superhyway_match_id(shyway_drv->id_table, shyway_dev); 146 - if (id) 147 - return shyway_drv->probe(shyway_dev, id); 148 - } 149 - 150 - return -ENODEV; 151 - } 152 - 153 - static void superhyway_device_remove(struct device *dev) 154 - { 155 - struct superhyway_device *shyway_dev = to_superhyway_device(dev); 156 - struct superhyway_driver *shyway_drv = to_superhyway_driver(dev->driver); 157 - 158 - if (shyway_drv->remove) 159 - shyway_drv->remove(shyway_dev); 160 - } 161 - 162 - /** 163 - * superhyway_register_driver - Register a new SuperHyway driver 164 - * @drv: SuperHyway driver to register. 165 - * 166 - * This registers the passed in @drv. Any devices matching the id table will 167 - * automatically be populated and handed off to the driver's specified probe 168 - * routine. 169 - */ 170 - int superhyway_register_driver(struct superhyway_driver *drv) 171 - { 172 - drv->drv.name = drv->name; 173 - drv->drv.bus = &superhyway_bus_type; 174 - 175 - return driver_register(&drv->drv); 176 - } 177 - 178 - /** 179 - * superhyway_unregister_driver - Unregister a SuperHyway driver 180 - * @drv: SuperHyway driver to unregister. 181 - * 182 - * This cleans up after superhyway_register_driver(), and should be invoked in 183 - * the exit path of any module drivers. 184 - */ 185 - void superhyway_unregister_driver(struct superhyway_driver *drv) 186 - { 187 - driver_unregister(&drv->drv); 188 - } 189 - 190 - static int superhyway_bus_match(struct device *dev, struct device_driver *drv) 191 - { 192 - struct superhyway_device *shyway_dev = to_superhyway_device(dev); 193 - struct superhyway_driver *shyway_drv = to_superhyway_driver(drv); 194 - const struct superhyway_device_id *ids = shyway_drv->id_table; 195 - 196 - if (!ids) 197 - return -EINVAL; 198 - if (superhyway_match_id(ids, shyway_dev)) 199 - return 1; 200 - 201 - return -ENODEV; 202 - } 203 - 204 - struct bus_type superhyway_bus_type = { 205 - .name = "superhyway", 206 - .match = superhyway_bus_match, 207 - #ifdef CONFIG_SYSFS 208 - .dev_groups = superhyway_dev_groups, 209 - #endif 210 - .probe = superhyway_device_probe, 211 - .remove = superhyway_device_remove, 212 - }; 213 - 214 - static int __init superhyway_bus_init(void) 215 - { 216 - return bus_register(&superhyway_bus_type); 217 - } 218 - 219 - static void __exit superhyway_bus_exit(void) 220 - { 221 - device_unregister(&superhyway_bus_device); 222 - bus_unregister(&superhyway_bus_type); 223 - } 224 - 225 - core_initcall(superhyway_bus_init); 226 - module_exit(superhyway_bus_exit); 227 - 228 - EXPORT_SYMBOL(superhyway_bus_type); 229 - EXPORT_SYMBOL(superhyway_add_device); 230 - EXPORT_SYMBOL(superhyway_add_devices); 231 - EXPORT_SYMBOL(superhyway_register_driver); 232 - EXPORT_SYMBOL(superhyway_unregister_driver); 233 - 234 - MODULE_LICENSE("GPL");
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include/linux/superhyway.h
··· 1 - /* 2 - * include/linux/superhyway.h 3 - * 4 - * SuperHyway Bus definitions 5 - * 6 - * Copyright (C) 2004, 2005 Paul Mundt <lethal@linux-sh.org> 7 - * 8 - * This file is subject to the terms and conditions of the GNU General Public 9 - * License. See the file "COPYING" in the main directory of this archive 10 - * for more details. 11 - */ 12 - #ifndef __LINUX_SUPERHYWAY_H 13 - #define __LINUX_SUPERHYWAY_H 14 - 15 - #include <linux/device.h> 16 - 17 - /* 18 - * SuperHyway IDs 19 - */ 20 - #define SUPERHYWAY_DEVICE_ID_SH5_DMAC 0x0183 21 - 22 - struct superhyway_vcr_info { 23 - u8 perr_flags; /* P-port Error flags */ 24 - u8 merr_flags; /* Module Error flags */ 25 - u16 mod_vers; /* Module Version */ 26 - u16 mod_id; /* Module ID */ 27 - u8 bot_mb; /* Bottom Memory block */ 28 - u8 top_mb; /* Top Memory block */ 29 - }; 30 - 31 - struct superhyway_ops { 32 - int (*read_vcr)(unsigned long base, struct superhyway_vcr_info *vcr); 33 - int (*write_vcr)(unsigned long base, struct superhyway_vcr_info vcr); 34 - }; 35 - 36 - struct superhyway_bus { 37 - struct superhyway_ops *ops; 38 - }; 39 - 40 - extern struct superhyway_bus superhyway_channels[]; 41 - 42 - struct superhyway_device_id { 43 - unsigned int id; 44 - unsigned long driver_data; 45 - }; 46 - 47 - struct superhyway_device; 48 - extern struct bus_type superhyway_bus_type; 49 - 50 - struct superhyway_driver { 51 - char *name; 52 - 53 - const struct superhyway_device_id *id_table; 54 - struct device_driver drv; 55 - 56 - int (*probe)(struct superhyway_device *dev, const struct superhyway_device_id *id); 57 - void (*remove)(struct superhyway_device *dev); 58 - }; 59 - 60 - #define to_superhyway_driver(d) container_of((d), struct superhyway_driver, drv) 61 - 62 - struct superhyway_device { 63 - char name[32]; 64 - 65 - struct device dev; 66 - 67 - struct superhyway_device_id id; 68 - struct superhyway_driver *drv; 69 - struct superhyway_bus *bus; 70 - 71 - int num_resources; 72 - struct resource *resource; 73 - struct superhyway_vcr_info vcr; 74 - }; 75 - 76 - #define to_superhyway_device(d) container_of((d), struct superhyway_device, dev) 77 - 78 - #define superhyway_get_drvdata(d) dev_get_drvdata(&(d)->dev) 79 - #define superhyway_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, (p)) 80 - 81 - static inline int 82 - superhyway_read_vcr(struct superhyway_device *dev, unsigned long base, 83 - struct superhyway_vcr_info *vcr) 84 - { 85 - return dev->bus->ops->read_vcr(base, vcr); 86 - } 87 - 88 - static inline int 89 - superhyway_write_vcr(struct superhyway_device *dev, unsigned long base, 90 - struct superhyway_vcr_info vcr) 91 - { 92 - return dev->bus->ops->write_vcr(base, vcr); 93 - } 94 - 95 - extern int superhyway_scan_bus(struct superhyway_bus *); 96 - 97 - /* drivers/sh/superhyway/superhyway.c */ 98 - int superhyway_register_driver(struct superhyway_driver *); 99 - void superhyway_unregister_driver(struct superhyway_driver *); 100 - int superhyway_add_device(unsigned long base, struct superhyway_device *, struct superhyway_bus *); 101 - int superhyway_add_devices(struct superhyway_bus *bus, struct superhyway_device **devices, int nr_devices); 102 - 103 - /* drivers/sh/superhyway/superhyway-sysfs.c */ 104 - extern const struct attribute_group *superhyway_dev_groups[]; 105 - 106 - #endif /* __LINUX_SUPERHYWAY_H */ 107 -