tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: cannonlake: Use generic flag for special GPIO base treatment
Since we have a generic flag for special GPIO base treatment,
use it in the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+28
-30
+28
-30
drivers/pinctrl/intel/pinctrl-cannonlake.c
+28
-30
drivers/pinctrl/intel/pinctrl-cannonlake.c
···
30
30
.gpio_base = (g), \
31
31
}
32
32
33
-
#define CNL_NO_GPIO -1
34
-
35
33
#define CNL_COMMUNITY(b, s, e, o, g) \
36
34
{ \
37
35
.barno = (b), \
···
375
377
};
376
378
377
379
static const struct intel_padgroup cnlh_community1_gpps[] = {
378
-
CNL_GPP(0, 51, 74, 64), /* GPP_C */
379
-
CNL_GPP(1, 75, 98, 96), /* GPP_D */
380
-
CNL_GPP(2, 99, 106, 128), /* GPP_G */
381
-
CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */
382
-
CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
383
-
CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */
380
+
CNL_GPP(0, 51, 74, 64), /* GPP_C */
381
+
CNL_GPP(1, 75, 98, 96), /* GPP_D */
382
+
CNL_GPP(2, 99, 106, 128), /* GPP_G */
383
+
CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
384
+
CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
385
+
CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
384
386
};
385
387
386
388
static const struct intel_padgroup cnlh_community3_gpps[] = {
387
-
CNL_GPP(0, 155, 178, 192), /* GPP_K */
388
-
CNL_GPP(1, 179, 202, 224), /* GPP_H */
389
-
CNL_GPP(2, 203, 215, 256), /* GPP_E */
390
-
CNL_GPP(3, 216, 239, 288), /* GPP_F */
391
-
CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */
389
+
CNL_GPP(0, 155, 178, 192), /* GPP_K */
390
+
CNL_GPP(1, 179, 202, 224), /* GPP_H */
391
+
CNL_GPP(2, 203, 215, 256), /* GPP_E */
392
+
CNL_GPP(3, 216, 239, 288), /* GPP_F */
393
+
CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
392
394
};
393
395
394
396
static const struct intel_padgroup cnlh_community4_gpps[] = {
395
-
CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */
396
-
CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */
397
-
CNL_GPP(2, 269, 286, 320), /* GPP_I */
398
-
CNL_GPP(3, 287, 298, 352), /* GPP_J */
397
+
CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
398
+
CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
399
+
CNL_GPP(2, 269, 286, 320), /* GPP_I */
400
+
CNL_GPP(3, 287, 298, 352), /* GPP_J */
399
401
};
400
402
401
403
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
···
788
790
};
789
791
790
792
static const struct intel_padgroup cnllp_community0_gpps[] = {
791
-
CNL_GPP(0, 0, 24, 0), /* GPP_A */
792
-
CNL_GPP(1, 25, 50, 32), /* GPP_B */
793
-
CNL_GPP(2, 51, 58, 64), /* GPP_G */
794
-
CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */
793
+
CNL_GPP(0, 0, 24, 0), /* GPP_A */
794
+
CNL_GPP(1, 25, 50, 32), /* GPP_B */
795
+
CNL_GPP(2, 51, 58, 64), /* GPP_G */
796
+
CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
795
797
};
796
798
797
799
static const struct intel_padgroup cnllp_community1_gpps[] = {
798
-
CNL_GPP(0, 68, 92, 96), /* GPP_D */
799
-
CNL_GPP(1, 93, 116, 128), /* GPP_F */
800
-
CNL_GPP(2, 117, 140, 160), /* GPP_H */
801
-
CNL_GPP(3, 141, 172, 192), /* vGPIO */
802
-
CNL_GPP(4, 173, 180, 224), /* vGPIO */
800
+
CNL_GPP(0, 68, 92, 96), /* GPP_D */
801
+
CNL_GPP(1, 93, 116, 128), /* GPP_F */
802
+
CNL_GPP(2, 117, 140, 160), /* GPP_H */
803
+
CNL_GPP(3, 141, 172, 192), /* vGPIO */
804
+
CNL_GPP(4, 173, 180, 224), /* vGPIO */
803
805
};
804
806
805
807
static const struct intel_padgroup cnllp_community4_gpps[] = {
806
-
CNL_GPP(0, 181, 204, 256), /* GPP_C */
807
-
CNL_GPP(1, 205, 228, 288), /* GPP_E */
808
-
CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */
809
-
CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */
808
+
CNL_GPP(0, 181, 204, 256), /* GPP_C */
809
+
CNL_GPP(1, 205, 228, 288), /* GPP_E */
810
+
CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
811
+
CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
810
812
};
811
813
812
814
static const struct intel_community cnllp_communities[] = {