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phy: qcom-qmp: pcs-ufs: Add v6 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated
header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Abel Vesa
and committed by
Vinod Koul
5b8154ce
c9736600
+32
+31
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+31
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
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#define QCOM_PHY_QMP_PCS_UFS_V6_H_
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/* Only for QMP V6 PHY - UFS PCS registers */
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#define QPHY_V6_PCS_UFS_PHY_START 0x000
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#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V6_PCS_UFS_SW_RESET 0x008
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
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#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
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#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
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#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
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#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
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#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
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#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
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#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
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#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
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#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
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#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
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#endif