Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

net: atm: remove support for Madge Horizon ATM devices

This driver received nothing but automated fixes since git era begun.
Since it's using virt_to_bus it's unlikely to be used on any modern
platform.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Jakub Kicinski and committed by
David S. Miller
5b74a20d 41c335c8

-3372
-1
arch/mips/configs/gpr_defconfig
··· 181 181 CONFIG_ATM_ZATM=m 182 182 CONFIG_ATM_NICSTAR=m 183 183 CONFIG_ATM_IDT77252=m 184 - CONFIG_ATM_HORIZON=m 185 184 CONFIG_ATM_IA=m 186 185 CONFIG_ATM_FORE200E=m 187 186 CONFIG_ATM_HE=m
-1
arch/mips/configs/mtx1_defconfig
··· 258 258 CONFIG_ATM_ZATM=m 259 259 CONFIG_ATM_NICSTAR=m 260 260 CONFIG_ATM_IDT77252=m 261 - CONFIG_ATM_HORIZON=m 262 261 CONFIG_ATM_IA=m 263 262 CONFIG_ATM_FORE200E=m 264 263 CONFIG_ATM_HE=m
-24
drivers/atm/Kconfig
··· 234 234 depends on ATM_IDT77252 235 235 default y 236 236 237 - config ATM_HORIZON 238 - tristate "Madge Horizon [Ultra] (Collage PCI 25 and Collage PCI 155 Client)" 239 - depends on PCI && VIRT_TO_BUS 240 - help 241 - This is a driver for the Horizon chipset ATM adapter cards once 242 - produced by Madge Networks Ltd. Say Y (or M to compile as a module 243 - named horizon) here if you have one of these cards. 244 - 245 - config ATM_HORIZON_DEBUG 246 - bool "Enable debugging messages" 247 - depends on ATM_HORIZON 248 - help 249 - Somewhat useful debugging messages are available. The choice of 250 - messages is controlled by a bitmap. This may be specified as a 251 - module argument (kernel command line argument as well?), changed 252 - dynamically using an ioctl (not yet) or changed by sending the 253 - string "Dxxxx" to VCI 1023 (where x is a hex digit). See the file 254 - <file:drivers/atm/horizon.h> for the meanings of the bits in the 255 - mask. 256 - 257 - When active, these messages can have a significant impact on the 258 - speed of the driver, and the size of your syslog files! When 259 - inactive, they will have only a modest impact on performance. 260 - 261 237 config ATM_IA 262 238 tristate "Interphase ATM PCI x575/x525/x531" 263 239 depends on PCI
-1
drivers/atm/Makefile
··· 7 7 8 8 obj-$(CONFIG_ATM_ZATM) += zatm.o uPD98402.o 9 9 obj-$(CONFIG_ATM_NICSTAR) += nicstar.o 10 - obj-$(CONFIG_ATM_HORIZON) += horizon.o 11 10 obj-$(CONFIG_ATM_IA) += iphase.o suni.o 12 11 obj-$(CONFIG_ATM_FORE200E) += fore_200e.o 13 12 obj-$(CONFIG_ATM_ENI) += eni.o suni.o
-2853
drivers/atm/horizon.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - Madge Horizon ATM Adapter driver. 4 - Copyright (C) 1995-1999 Madge Networks Ltd. 5 - 6 - */ 7 - 8 - /* 9 - IMPORTANT NOTE: Madge Networks no longer makes the adapters 10 - supported by this driver and makes no commitment to maintain it. 11 - */ 12 - 13 - #include <linux/module.h> 14 - #include <linux/kernel.h> 15 - #include <linux/sched/signal.h> 16 - #include <linux/mm.h> 17 - #include <linux/pci.h> 18 - #include <linux/errno.h> 19 - #include <linux/atm.h> 20 - #include <linux/atmdev.h> 21 - #include <linux/sonet.h> 22 - #include <linux/skbuff.h> 23 - #include <linux/time.h> 24 - #include <linux/delay.h> 25 - #include <linux/uio.h> 26 - #include <linux/init.h> 27 - #include <linux/interrupt.h> 28 - #include <linux/ioport.h> 29 - #include <linux/wait.h> 30 - #include <linux/slab.h> 31 - 32 - #include <asm/io.h> 33 - #include <linux/atomic.h> 34 - #include <linux/uaccess.h> 35 - #include <asm/string.h> 36 - #include <asm/byteorder.h> 37 - 38 - #include "horizon.h" 39 - 40 - #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>" 41 - #define description_string "Madge ATM Horizon [Ultra] driver" 42 - #define version_string "1.2.1" 43 - 44 - static inline void __init show_version (void) { 45 - printk ("%s version %s\n", description_string, version_string); 46 - } 47 - 48 - /* 49 - 50 - CREDITS 51 - 52 - Driver and documentation by: 53 - 54 - Chris Aston Madge Networks 55 - Giuliano Procida Madge Networks 56 - Simon Benham Madge Networks 57 - Simon Johnson Madge Networks 58 - Various Others Madge Networks 59 - 60 - Some inspiration taken from other drivers by: 61 - 62 - Alexandru Cucos UTBv 63 - Kari Mettinen University of Helsinki 64 - Werner Almesberger EPFL LRC 65 - 66 - Theory of Operation 67 - 68 - I Hardware, detection, initialisation and shutdown. 69 - 70 - 1. Supported Hardware 71 - 72 - This driver should handle all variants of the PCI Madge ATM adapters 73 - with the Horizon chipset. These are all PCI cards supporting PIO, BM 74 - DMA and a form of MMIO (registers only, not internal RAM). 75 - 76 - The driver is only known to work with SONET and UTP Horizon Ultra 77 - cards at 155Mb/s. However, code is in place to deal with both the 78 - original Horizon and 25Mb/s operation. 79 - 80 - There are two revisions of the Horizon ASIC: the original and the 81 - Ultra. Details of hardware bugs are in section III. 82 - 83 - The ASIC version can be distinguished by chip markings but is NOT 84 - indicated by the PCI revision (all adapters seem to have PCI rev 1). 85 - 86 - I believe that: 87 - 88 - Horizon => Collage 25 PCI Adapter (UTP and STP) 89 - Horizon Ultra => Collage 155 PCI Client (UTP or SONET) 90 - Ambassador x => Collage 155 PCI Server (completely different) 91 - 92 - Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to 93 - have a Madge B154 plus glue logic serializer. I have also found a 94 - really ancient version of this with slightly different glue. It 95 - comes with the revision 0 (140-025-01) ASIC. 96 - 97 - Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink 98 - output (UTP) or an HP HFBR 5205 output (SONET). It has either 99 - Madge's SAMBA framer or a SUNI-lite device (early versions). It 100 - comes with the revision 1 (140-027-01) ASIC. 101 - 102 - 2. Detection 103 - 104 - All Horizon-based cards present with the same PCI Vendor and Device 105 - IDs. The standard Linux 2.2 PCI API is used to locate any cards and 106 - to enable bus-mastering (with appropriate latency). 107 - 108 - ATM_LAYER_STATUS in the control register distinguishes between the 109 - two possible physical layers (25 and 155). It is not clear whether 110 - the 155 cards can also operate at 25Mbps. We rely on the fact that a 111 - card operates at 155 if and only if it has the newer Horizon Ultra 112 - ASIC. 113 - 114 - For 155 cards the two possible framers are probed for and then set 115 - up for loop-timing. 116 - 117 - 3. Initialisation 118 - 119 - The card is reset and then put into a known state. The physical 120 - layer is configured for normal operation at the appropriate speed; 121 - in the case of the 155 cards, the framer is initialised with 122 - line-based timing; the internal RAM is zeroed and the allocation of 123 - buffers for RX and TX is made; the Burnt In Address is read and 124 - copied to the ATM ESI; various policy settings for RX (VPI bits, 125 - unknown VCs, oam cells) are made. Ideally all policy items should be 126 - configurable at module load (if not actually on-demand), however, 127 - only the vpi vs vci bit allocation can be specified at insmod. 128 - 129 - 4. Shutdown 130 - 131 - This is in response to module_cleaup. No VCs are in use and the card 132 - should be idle; it is reset. 133 - 134 - II Driver software (as it should be) 135 - 136 - 0. Traffic Parameters 137 - 138 - The traffic classes (not an enumeration) are currently: ATM_NONE (no 139 - traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS 140 - (compatible with everything). Together with (perhaps only some of) 141 - the following items they make up the traffic specification. 142 - 143 - struct atm_trafprm { 144 - unsigned char traffic_class; traffic class (ATM_UBR, ...) 145 - int max_pcr; maximum PCR in cells per second 146 - int pcr; desired PCR in cells per second 147 - int min_pcr; minimum PCR in cells per second 148 - int max_cdv; maximum CDV in microseconds 149 - int max_sdu; maximum SDU in bytes 150 - }; 151 - 152 - Note that these denote bandwidth available not bandwidth used; the 153 - possibilities according to ATMF are: 154 - 155 - Real Time (cdv and max CDT given) 156 - 157 - CBR(pcr) pcr bandwidth always available 158 - rtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too 159 - 160 - Non Real Time 161 - 162 - nrtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too 163 - UBR() 164 - ABR(mcr,pcr) mcr bandwidth always available, up to pcr (depending) too 165 - 166 - mbs is max burst size (bucket) 167 - pcr and scr have associated cdvt values 168 - mcr is like scr but has no cdtv 169 - cdtv may differ at each hop 170 - 171 - Some of the above items are qos items (as opposed to traffic 172 - parameters). We have nothing to do with qos. All except ABR can have 173 - their traffic parameters converted to GCRA parameters. The GCRA may 174 - be implemented as a (real-number) leaky bucket. The GCRA can be used 175 - in complicated ways by switches and in simpler ways by end-stations. 176 - It can be used both to filter incoming cells and shape out-going 177 - cells. 178 - 179 - ATM Linux actually supports: 180 - 181 - ATM_NONE() (no traffic in this direction) 182 - ATM_UBR(max_frame_size) 183 - ATM_CBR(max/min_pcr, max_cdv, max_frame_size) 184 - 185 - 0 or ATM_MAX_PCR are used to indicate maximum available PCR 186 - 187 - A traffic specification consists of the AAL type and separate 188 - traffic specifications for either direction. In ATM Linux it is: 189 - 190 - struct atm_qos { 191 - struct atm_trafprm txtp; 192 - struct atm_trafprm rxtp; 193 - unsigned char aal; 194 - }; 195 - 196 - AAL types are: 197 - 198 - ATM_NO_AAL AAL not specified 199 - ATM_AAL0 "raw" ATM cells 200 - ATM_AAL1 AAL1 (CBR) 201 - ATM_AAL2 AAL2 (VBR) 202 - ATM_AAL34 AAL3/4 (data) 203 - ATM_AAL5 AAL5 (data) 204 - ATM_SAAL signaling AAL 205 - 206 - The Horizon has support for AAL frame types: 0, 3/4 and 5. However, 207 - it does not implement AAL 3/4 SAR and it has a different notion of 208 - "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are 209 - supported by this driver. 210 - 211 - The Horizon has limited support for ABR (including UBR), VBR and 212 - CBR. Each TX channel has a bucket (containing up to 31 cell units) 213 - and two timers (PCR and SCR) associated with it that can be used to 214 - govern cell emissions and host notification (in the case of ABR this 215 - is presumably so that RM cells may be emitted at appropriate times). 216 - The timers may either be disabled or may be set to any of 240 values 217 - (determined by the clock crystal, a fixed (?) per-device divider, a 218 - configurable divider and a configurable timer preload value). 219 - 220 - At the moment only UBR and CBR are supported by the driver. VBR will 221 - be supported as soon as ATM for Linux supports it. ABR support is 222 - very unlikely as RM cell handling is completely up to the driver. 223 - 224 - 1. TX (TX channel setup and TX transfer) 225 - 226 - The TX half of the driver owns the TX Horizon registers. The TX 227 - component in the IRQ handler is the BM completion handler. This can 228 - only be entered when tx_busy is true (enforced by hardware). The 229 - other TX component can only be entered when tx_busy is false 230 - (enforced by driver). So TX is single-threaded. 231 - 232 - Apart from a minor optimisation to not re-select the last channel, 233 - the TX send component works as follows: 234 - 235 - Atomic test and set tx_busy until we succeed; we should implement 236 - some sort of timeout so that tx_busy will never be stuck at true. 237 - 238 - If no TX channel is set up for this VC we wait for an idle one (if 239 - necessary) and set it up. 240 - 241 - At this point we have a TX channel ready for use. We wait for enough 242 - buffers to become available then start a TX transmit (set the TX 243 - descriptor, schedule transfer, exit). 244 - 245 - The IRQ component handles TX completion (stats, free buffer, tx_busy 246 - unset, exit). We also re-schedule further transfers for the same 247 - frame if needed. 248 - 249 - TX setup in more detail: 250 - 251 - TX open is a nop, the relevant information is held in the hrz_vcc 252 - (vcc->dev_data) structure and is "cached" on the card. 253 - 254 - TX close gets the TX lock and clears the channel from the "cache". 255 - 256 - 2. RX (Data Available and RX transfer) 257 - 258 - The RX half of the driver owns the RX registers. There are two RX 259 - components in the IRQ handler: the data available handler deals with 260 - fresh data that has arrived on the card, the BM completion handler 261 - is very similar to the TX completion handler. The data available 262 - handler grabs the rx_lock and it is only released once the data has 263 - been discarded or completely transferred to the host. The BM 264 - completion handler only runs when the lock is held; the data 265 - available handler is locked out over the same period. 266 - 267 - Data available on the card triggers an interrupt. If the data is not 268 - suitable for our existing RX channels or we cannot allocate a buffer 269 - it is flushed. Otherwise an RX receive is scheduled. Multiple RX 270 - transfers may be scheduled for the same frame. 271 - 272 - RX setup in more detail: 273 - 274 - RX open... 275 - RX close... 276 - 277 - III Hardware Bugs 278 - 279 - 0. Byte vs Word addressing of adapter RAM. 280 - 281 - A design feature; see the .h file (especially the memory map). 282 - 283 - 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra) 284 - 285 - The host must not start a transmit direction transfer at a 286 - non-four-byte boundary in host memory. Instead the host should 287 - perform a byte, or a two byte, or one byte followed by two byte 288 - transfer in order to start the rest of the transfer on a four byte 289 - boundary. RX is OK. 290 - 291 - Simultaneous transmit and receive direction bus master transfers are 292 - not allowed. 293 - 294 - The simplest solution to these two is to always do PIO (never DMA) 295 - in the TX direction on the original Horizon. More complicated 296 - solutions are likely to hurt my brain. 297 - 298 - 2. Loss of buffer on close VC 299 - 300 - When a VC is being closed, the buffer associated with it is not 301 - returned to the pool. The host must store the reference to this 302 - buffer and when opening a new VC then give it to that new VC. 303 - 304 - The host intervention currently consists of stacking such a buffer 305 - pointer at VC close and checking the stack at VC open. 306 - 307 - 3. Failure to close a VC 308 - 309 - If a VC is currently receiving a frame then closing the VC may fail 310 - and the frame continues to be received. 311 - 312 - The solution is to make sure any received frames are flushed when 313 - ready. This is currently done just before the solution to 2. 314 - 315 - 4. PCI bus (original Horizon only, fixed in Ultra) 316 - 317 - Reading from the data port prior to initialisation will hang the PCI 318 - bus. Just don't do that then! We don't. 319 - 320 - IV To Do List 321 - 322 - . Timer code may be broken. 323 - 324 - . Allow users to specify buffer allocation split for TX and RX. 325 - 326 - . Deal once and for all with buggy VC close. 327 - 328 - . Handle interrupted and/or non-blocking operations. 329 - 330 - . Change some macros to functions and move from .h to .c. 331 - 332 - . Try to limit the number of TX frames each VC may have queued, in 333 - order to reduce the chances of TX buffer exhaustion. 334 - 335 - . Implement VBR (bucket and timers not understood) and ABR (need to 336 - do RM cells manually); also no Linux support for either. 337 - 338 - . Implement QoS changes on open VCs (involves extracting parts of VC open 339 - and close into separate functions and using them to make changes). 340 - 341 - */ 342 - 343 - /********** globals **********/ 344 - 345 - static void do_housekeeping (struct timer_list *t); 346 - 347 - static unsigned short debug = 0; 348 - static unsigned short vpi_bits = 0; 349 - static int max_tx_size = 9000; 350 - static int max_rx_size = 9000; 351 - static unsigned char pci_lat = 0; 352 - 353 - /********** access functions **********/ 354 - 355 - /* Read / Write Horizon registers */ 356 - static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) { 357 - outl (cpu_to_le32 (data), dev->iobase + reg); 358 - } 359 - 360 - static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) { 361 - return le32_to_cpu (inl (dev->iobase + reg)); 362 - } 363 - 364 - static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) { 365 - outw (cpu_to_le16 (data), dev->iobase + reg); 366 - } 367 - 368 - static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) { 369 - return le16_to_cpu (inw (dev->iobase + reg)); 370 - } 371 - 372 - static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { 373 - outsb (dev->iobase + reg, addr, len); 374 - } 375 - 376 - static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { 377 - insb (dev->iobase + reg, addr, len); 378 - } 379 - 380 - /* Read / Write to a given address in Horizon buffer memory. 381 - Interrupts must be disabled between the address register and data 382 - port accesses as these must form an atomic operation. */ 383 - static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) { 384 - // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr); 385 - wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); 386 - wr_regl (dev, MEMORY_PORT_OFF, data); 387 - } 388 - 389 - static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) { 390 - // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr); 391 - wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); 392 - return rd_regl (dev, MEMORY_PORT_OFF); 393 - } 394 - 395 - static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) { 396 - wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000); 397 - wr_regl (dev, MEMORY_PORT_OFF, data); 398 - } 399 - 400 - static inline u32 rd_framer (const hrz_dev * dev, u32 addr) { 401 - wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000); 402 - return rd_regl (dev, MEMORY_PORT_OFF); 403 - } 404 - 405 - /********** specialised access functions **********/ 406 - 407 - /* RX */ 408 - 409 - static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) { 410 - wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel); 411 - return; 412 - } 413 - 414 - static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) { 415 - while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL) 416 - ; 417 - return; 418 - } 419 - 420 - static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) { 421 - wr_regw (dev, RX_CHANNEL_PORT_OFF, channel); 422 - return; 423 - } 424 - 425 - static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) { 426 - while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS) 427 - ; 428 - return; 429 - } 430 - 431 - /* TX */ 432 - 433 - static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) { 434 - wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel); 435 - return; 436 - } 437 - 438 - /* Update or query one configuration parameter of a particular channel. */ 439 - 440 - static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) { 441 - wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF, 442 - chan * TX_CHANNEL_CONFIG_MULT | mode); 443 - wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value); 444 - return; 445 - } 446 - 447 - /********** dump functions **********/ 448 - 449 - static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) { 450 - #ifdef DEBUG_HORIZON 451 - unsigned int i; 452 - unsigned char * data = skb->data; 453 - PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc); 454 - for (i=0; i<skb->len && i < 256;i++) 455 - PRINTDM (DBG_DATA, "%02x ", data[i]); 456 - PRINTDE (DBG_DATA,""); 457 - #else 458 - (void) prefix; 459 - (void) vc; 460 - (void) skb; 461 - #endif 462 - return; 463 - } 464 - 465 - static inline void dump_regs (hrz_dev * dev) { 466 - #ifdef DEBUG_HORIZON 467 - PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG)); 468 - PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF)); 469 - PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF)); 470 - PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF)); 471 - PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF)); 472 - PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF)); 473 - #else 474 - (void) dev; 475 - #endif 476 - return; 477 - } 478 - 479 - static inline void dump_framer (hrz_dev * dev) { 480 - #ifdef DEBUG_HORIZON 481 - unsigned int i; 482 - PRINTDB (DBG_REGS, "framer registers:"); 483 - for (i = 0; i < 0x10; ++i) 484 - PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i)); 485 - PRINTDE (DBG_REGS,""); 486 - #else 487 - (void) dev; 488 - #endif 489 - return; 490 - } 491 - 492 - /********** VPI/VCI <-> (RX) channel conversions **********/ 493 - 494 - /* RX channels are 10 bit integers, these fns are quite paranoid */ 495 - 496 - static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) { 497 - unsigned short vci_bits = 10 - vpi_bits; 498 - if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) { 499 - *channel = vpi<<vci_bits | vci; 500 - return *channel ? 0 : -EINVAL; 501 - } 502 - return -EINVAL; 503 - } 504 - 505 - /********** decode RX queue entries **********/ 506 - 507 - static inline u16 rx_q_entry_to_length (u32 x) { 508 - return x & RX_Q_ENTRY_LENGTH_MASK; 509 - } 510 - 511 - static inline u16 rx_q_entry_to_rx_channel (u32 x) { 512 - return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK; 513 - } 514 - 515 - /* Cell Transmit Rate Values 516 - * 517 - * the cell transmit rate (cells per sec) can be set to a variety of 518 - * different values by specifying two parameters: a timer preload from 519 - * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of 520 - * an exponent from 0 to 14; the special value 15 disables the timer). 521 - * 522 - * cellrate = baserate / (preload * 2^divider) 523 - * 524 - * The maximum cell rate that can be specified is therefore just the 525 - * base rate. Halving the preload is equivalent to adding 1 to the 526 - * divider and so values 1 to 8 of the preload are redundant except 527 - * in the case of a maximal divider (14). 528 - * 529 - * Given a desired cell rate, an algorithm to determine the preload 530 - * and divider is: 531 - * 532 - * a) x = baserate / cellrate, want p * 2^d = x (as far as possible) 533 - * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done 534 - * if x <= 16 then set p = x, d = 0 (high rates), done 535 - * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to 536 - * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until 537 - * we find the range (n will be between 1 and 14), set d = n 538 - * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n 539 - * 540 - * The algorithm used below is a minor variant of the above. 541 - * 542 - * The base rate is derived from the oscillator frequency (Hz) using a 543 - * fixed divider: 544 - * 545 - * baserate = freq / 32 in the case of some Unknown Card 546 - * baserate = freq / 8 in the case of the Horizon 25 547 - * baserate = freq / 8 in the case of the Horizon Ultra 155 548 - * 549 - * The Horizon cards have oscillators and base rates as follows: 550 - * 551 - * Card Oscillator Base Rate 552 - * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq) 553 - * Horizon 25 32 MHz 4 MHz 554 - * Horizon Ultra 155 40 MHz 5 MHz 555 - * 556 - * The following defines give the base rates in Hz. These were 557 - * previously a factor of 100 larger, no doubt someone was using 558 - * cps*100. 559 - */ 560 - 561 - #define BR_UKN 1031250l 562 - #define BR_HRZ 4000000l 563 - #define BR_ULT 5000000l 564 - 565 - // d is an exponent 566 - #define CR_MIND 0 567 - #define CR_MAXD 14 568 - 569 - // p ranges from 1 to a power of 2 570 - #define CR_MAXPEXP 4 571 - 572 - static int make_rate (const hrz_dev * dev, u32 c, rounding r, 573 - u16 * bits, unsigned int * actual) 574 - { 575 - // note: rounding the rate down means rounding 'p' up 576 - const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ; 577 - 578 - u32 div = CR_MIND; 579 - u32 pre; 580 - 581 - // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in 582 - // the tests below. We could think harder about exact possibilities 583 - // of failure... 584 - 585 - unsigned long br_man = br; 586 - unsigned int br_exp = 0; 587 - 588 - PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c, 589 - r == round_up ? "up" : r == round_down ? "down" : "nearest"); 590 - 591 - // avoid div by zero 592 - if (!c) { 593 - PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!"); 594 - return -EINVAL; 595 - } 596 - 597 - while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) { 598 - br_man = br_man >> 1; 599 - ++br_exp; 600 - } 601 - // (br >>br_exp) <<br_exp == br and 602 - // br_exp <= CR_MAXPEXP+CR_MIND 603 - 604 - if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) { 605 - // Equivalent to: B <= (c << (MAXPEXP+MIND)) 606 - // take care of rounding 607 - switch (r) { 608 - case round_down: 609 - pre = DIV_ROUND_UP(br, c<<div); 610 - // but p must be non-zero 611 - if (!pre) 612 - pre = 1; 613 - break; 614 - case round_nearest: 615 - pre = DIV_ROUND_CLOSEST(br, c<<div); 616 - // but p must be non-zero 617 - if (!pre) 618 - pre = 1; 619 - break; 620 - default: /* round_up */ 621 - pre = br/(c<<div); 622 - // but p must be non-zero 623 - if (!pre) 624 - return -EINVAL; 625 - } 626 - PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div); 627 - goto got_it; 628 - } 629 - 630 - // at this point we have 631 - // d == MIND and (c << (MAXPEXP+MIND)) < B 632 - while (div < CR_MAXD) { 633 - div++; 634 - if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) { 635 - // Equivalent to: B <= (c << (MAXPEXP+d)) 636 - // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d) 637 - // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP 638 - // MAXP/2 < B/c2^d <= MAXP 639 - // take care of rounding 640 - switch (r) { 641 - case round_down: 642 - pre = DIV_ROUND_UP(br, c<<div); 643 - break; 644 - case round_nearest: 645 - pre = DIV_ROUND_CLOSEST(br, c<<div); 646 - break; 647 - default: /* round_up */ 648 - pre = br/(c<<div); 649 - } 650 - PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div); 651 - goto got_it; 652 - } 653 - } 654 - // at this point we have 655 - // d == MAXD and (c << (MAXPEXP+MAXD)) < B 656 - // but we cannot go any higher 657 - // take care of rounding 658 - if (r == round_down) 659 - return -EINVAL; 660 - pre = 1 << CR_MAXPEXP; 661 - PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div); 662 - got_it: 663 - // paranoia 664 - if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) { 665 - PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u", 666 - div, pre); 667 - return -EINVAL; 668 - } else { 669 - if (bits) 670 - *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1); 671 - if (actual) { 672 - *actual = DIV_ROUND_UP(br, pre<<div); 673 - PRINTD (DBG_QOS, "actual rate: %u", *actual); 674 - } 675 - return 0; 676 - } 677 - } 678 - 679 - static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol, 680 - u16 * bit_pattern, unsigned int * actual) { 681 - unsigned int my_actual; 682 - 683 - PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u", 684 - c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol); 685 - 686 - if (!actual) 687 - // actual rate is not returned 688 - actual = &my_actual; 689 - 690 - if (make_rate (dev, c, round_nearest, bit_pattern, actual)) 691 - // should never happen as round_nearest always succeeds 692 - return -1; 693 - 694 - if (c - tol <= *actual && *actual <= c + tol) 695 - // within tolerance 696 - return 0; 697 - else 698 - // intolerant, try rounding instead 699 - return make_rate (dev, c, r, bit_pattern, actual); 700 - } 701 - 702 - /********** Listen on a VC **********/ 703 - 704 - static int hrz_open_rx (hrz_dev * dev, u16 channel) { 705 - // is there any guarantee that we don't get two simulataneous 706 - // identical calls of this function from different processes? yes 707 - // rate_lock 708 - unsigned long flags; 709 - u32 channel_type; // u16? 710 - 711 - u16 buf_ptr = RX_CHANNEL_IDLE; 712 - 713 - rx_ch_desc * rx_desc = &memmap->rx_descs[channel]; 714 - 715 - PRINTD (DBG_FLOW, "hrz_open_rx %x", channel); 716 - 717 - spin_lock_irqsave (&dev->mem_lock, flags); 718 - channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK; 719 - spin_unlock_irqrestore (&dev->mem_lock, flags); 720 - 721 - // very serious error, should never occur 722 - if (channel_type != RX_CHANNEL_DISABLED) { 723 - PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open"); 724 - return -EBUSY; // clean up? 725 - } 726 - 727 - // Give back spare buffer 728 - if (dev->noof_spare_buffers) { 729 - buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers]; 730 - PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr); 731 - // should never occur 732 - if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) { 733 - // but easy to recover from 734 - PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE"); 735 - buf_ptr = RX_CHANNEL_IDLE; 736 - } 737 - } else { 738 - PRINTD (DBG_VCC, "using IDLE buffer pointer"); 739 - } 740 - 741 - // Channel is currently disabled so change its status to idle 742 - 743 - // do we really need to save the flags again? 744 - spin_lock_irqsave (&dev->mem_lock, flags); 745 - 746 - wr_mem (dev, &rx_desc->wr_buf_type, 747 - buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME); 748 - if (buf_ptr != RX_CHANNEL_IDLE) 749 - wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr); 750 - 751 - spin_unlock_irqrestore (&dev->mem_lock, flags); 752 - 753 - // rxer->rate = make_rate (qos->peak_cells); 754 - 755 - PRINTD (DBG_FLOW, "hrz_open_rx ok"); 756 - 757 - return 0; 758 - } 759 - 760 - #if 0 761 - /********** change vc rate for a given vc **********/ 762 - 763 - static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) { 764 - rxer->rate = make_rate (qos->peak_cells); 765 - } 766 - #endif 767 - 768 - /********** free an skb (as per ATM device driver documentation) **********/ 769 - 770 - static void hrz_kfree_skb (struct sk_buff * skb) { 771 - if (ATM_SKB(skb)->vcc->pop) { 772 - ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb); 773 - } else { 774 - dev_kfree_skb_any (skb); 775 - } 776 - } 777 - 778 - /********** cancel listen on a VC **********/ 779 - 780 - static void hrz_close_rx (hrz_dev * dev, u16 vc) { 781 - unsigned long flags; 782 - 783 - u32 value; 784 - 785 - u32 r1, r2; 786 - 787 - rx_ch_desc * rx_desc = &memmap->rx_descs[vc]; 788 - 789 - int was_idle = 0; 790 - 791 - spin_lock_irqsave (&dev->mem_lock, flags); 792 - value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK; 793 - spin_unlock_irqrestore (&dev->mem_lock, flags); 794 - 795 - if (value == RX_CHANNEL_DISABLED) { 796 - // I suppose this could happen once we deal with _NONE traffic properly 797 - PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc); 798 - return; 799 - } 800 - if (value == RX_CHANNEL_IDLE) 801 - was_idle = 1; 802 - 803 - spin_lock_irqsave (&dev->mem_lock, flags); 804 - 805 - for (;;) { 806 - wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED); 807 - 808 - if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED) 809 - break; 810 - 811 - was_idle = 0; 812 - } 813 - 814 - if (was_idle) { 815 - spin_unlock_irqrestore (&dev->mem_lock, flags); 816 - return; 817 - } 818 - 819 - WAIT_FLUSH_RX_COMPLETE(dev); 820 - 821 - // XXX Is this all really necessary? We can rely on the rx_data_av 822 - // handler to discard frames that remain queued for delivery. If the 823 - // worry is that immediately reopening the channel (perhaps by a 824 - // different process) may cause some data to be mis-delivered then 825 - // there may still be a simpler solution (such as busy-waiting on 826 - // rx_busy once the channel is disabled or before a new one is 827 - // opened - does this leave any holes?). Arguably setting up and 828 - // tearing down the TX and RX halves of each virtual circuit could 829 - // most safely be done within ?x_busy protected regions. 830 - 831 - // OK, current changes are that Simon's marker is disabled and we DO 832 - // look for NULL rxer elsewhere. The code here seems flush frames 833 - // and then remember the last dead cell belonging to the channel 834 - // just disabled - the cell gets relinked at the next vc_open. 835 - // However, when all VCs are closed or only a few opened there are a 836 - // handful of buffers that are unusable. 837 - 838 - // Does anyone feel like documenting spare_buffers properly? 839 - // Does anyone feel like fixing this in a nicer way? 840 - 841 - // Flush any data which is left in the channel 842 - for (;;) { 843 - // Change the rx channel port to something different to the RX 844 - // channel we are trying to close to force Horizon to flush the rx 845 - // channel read and write pointers. 846 - 847 - u16 other = vc^(RX_CHANS/2); 848 - 849 - SELECT_RX_CHANNEL (dev, other); 850 - WAIT_UPDATE_COMPLETE (dev); 851 - 852 - r1 = rd_mem (dev, &rx_desc->rd_buf_type); 853 - 854 - // Select this RX channel. Flush doesn't seem to work unless we 855 - // select an RX channel before hand 856 - 857 - SELECT_RX_CHANNEL (dev, vc); 858 - WAIT_UPDATE_COMPLETE (dev); 859 - 860 - // Attempt to flush a frame on this RX channel 861 - 862 - FLUSH_RX_CHANNEL (dev, vc); 863 - WAIT_FLUSH_RX_COMPLETE (dev); 864 - 865 - // Force Horizon to flush rx channel read and write pointers as before 866 - 867 - SELECT_RX_CHANNEL (dev, other); 868 - WAIT_UPDATE_COMPLETE (dev); 869 - 870 - r2 = rd_mem (dev, &rx_desc->rd_buf_type); 871 - 872 - PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2); 873 - 874 - if (r1 == r2) { 875 - dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1; 876 - break; 877 - } 878 - } 879 - 880 - #if 0 881 - { 882 - rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)]; 883 - rx_q_entry * rd_ptr = dev->rx_q_entry; 884 - 885 - PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr); 886 - 887 - while (rd_ptr != wr_ptr) { 888 - u32 x = rd_mem (dev, (HDW *) rd_ptr); 889 - 890 - if (vc == rx_q_entry_to_rx_channel (x)) { 891 - x |= SIMONS_DODGEY_MARKER; 892 - 893 - PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey"); 894 - 895 - wr_mem (dev, (HDW *) rd_ptr, x); 896 - } 897 - 898 - if (rd_ptr == dev->rx_q_wrap) 899 - rd_ptr = dev->rx_q_reset; 900 - else 901 - rd_ptr++; 902 - } 903 - } 904 - #endif 905 - 906 - spin_unlock_irqrestore (&dev->mem_lock, flags); 907 - 908 - return; 909 - } 910 - 911 - /********** schedule RX transfers **********/ 912 - 913 - // Note on tail recursion: a GCC developer said that it is not likely 914 - // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you 915 - // are sure it does as you may otherwise overflow the kernel stack. 916 - 917 - // giving this fn a return value would help GCC, allegedly 918 - 919 - static void rx_schedule (hrz_dev * dev, int irq) { 920 - unsigned int rx_bytes; 921 - 922 - int pio_instead = 0; 923 - #ifndef TAILRECURSIONWORKS 924 - pio_instead = 1; 925 - while (pio_instead) { 926 - #endif 927 - // bytes waiting for RX transfer 928 - rx_bytes = dev->rx_bytes; 929 - 930 - #if 0 931 - spin_count = 0; 932 - while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) { 933 - PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!"); 934 - if (++spin_count > 10) { 935 - PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion"); 936 - wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 937 - clear_bit (rx_busy, &dev->flags); 938 - hrz_kfree_skb (dev->rx_skb); 939 - return; 940 - } 941 - } 942 - #endif 943 - 944 - // this code follows the TX code but (at the moment) there is only 945 - // one region - the skb itself. I don't know if this will change, 946 - // but it doesn't hurt to have the code here, disabled. 947 - 948 - if (rx_bytes) { 949 - // start next transfer within same region 950 - if (rx_bytes <= MAX_PIO_COUNT) { 951 - PRINTD (DBG_RX|DBG_BUS, "(pio)"); 952 - pio_instead = 1; 953 - } 954 - if (rx_bytes <= MAX_TRANSFER_COUNT) { 955 - PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)"); 956 - dev->rx_bytes = 0; 957 - } else { 958 - PRINTD (DBG_RX|DBG_BUS, "(continuing multi)"); 959 - dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT; 960 - rx_bytes = MAX_TRANSFER_COUNT; 961 - } 962 - } else { 963 - // rx_bytes == 0 -- we're between regions 964 - // regions remaining to transfer 965 - #if 0 966 - unsigned int rx_regions = dev->rx_regions; 967 - #else 968 - unsigned int rx_regions = 0; 969 - #endif 970 - 971 - if (rx_regions) { 972 - #if 0 973 - // start a new region 974 - dev->rx_addr = dev->rx_iovec->iov_base; 975 - rx_bytes = dev->rx_iovec->iov_len; 976 - ++dev->rx_iovec; 977 - dev->rx_regions = rx_regions - 1; 978 - 979 - if (rx_bytes <= MAX_PIO_COUNT) { 980 - PRINTD (DBG_RX|DBG_BUS, "(pio)"); 981 - pio_instead = 1; 982 - } 983 - if (rx_bytes <= MAX_TRANSFER_COUNT) { 984 - PRINTD (DBG_RX|DBG_BUS, "(full region)"); 985 - dev->rx_bytes = 0; 986 - } else { 987 - PRINTD (DBG_RX|DBG_BUS, "(start multi region)"); 988 - dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT; 989 - rx_bytes = MAX_TRANSFER_COUNT; 990 - } 991 - #endif 992 - } else { 993 - // rx_regions == 0 994 - // that's all folks - end of frame 995 - struct sk_buff * skb = dev->rx_skb; 996 - // dev->rx_iovec = 0; 997 - 998 - FLUSH_RX_CHANNEL (dev, dev->rx_channel); 999 - 1000 - dump_skb ("<<<", dev->rx_channel, skb); 1001 - 1002 - PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len); 1003 - 1004 - { 1005 - struct atm_vcc * vcc = ATM_SKB(skb)->vcc; 1006 - // VC layer stats 1007 - atomic_inc(&vcc->stats->rx); 1008 - __net_timestamp(skb); 1009 - // end of our responsibility 1010 - vcc->push (vcc, skb); 1011 - } 1012 - } 1013 - } 1014 - 1015 - // note: writing RX_COUNT clears any interrupt condition 1016 - if (rx_bytes) { 1017 - if (pio_instead) { 1018 - if (irq) 1019 - wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 1020 - rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes); 1021 - } else { 1022 - wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr)); 1023 - wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes); 1024 - } 1025 - dev->rx_addr += rx_bytes; 1026 - } else { 1027 - if (irq) 1028 - wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 1029 - // allow another RX thread to start 1030 - YELLOW_LED_ON(dev); 1031 - clear_bit (rx_busy, &dev->flags); 1032 - PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev); 1033 - } 1034 - 1035 - #ifdef TAILRECURSIONWORKS 1036 - // and we all bless optimised tail calls 1037 - if (pio_instead) 1038 - return rx_schedule (dev, 0); 1039 - return; 1040 - #else 1041 - // grrrrrrr! 1042 - irq = 0; 1043 - } 1044 - return; 1045 - #endif 1046 - } 1047 - 1048 - /********** handle RX bus master complete events **********/ 1049 - 1050 - static void rx_bus_master_complete_handler (hrz_dev * dev) { 1051 - if (test_bit (rx_busy, &dev->flags)) { 1052 - rx_schedule (dev, 1); 1053 - } else { 1054 - PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion"); 1055 - // clear interrupt condition on adapter 1056 - wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 1057 - } 1058 - return; 1059 - } 1060 - 1061 - /********** (queue to) become the next TX thread **********/ 1062 - 1063 - static int tx_hold (hrz_dev * dev) { 1064 - PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags); 1065 - wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags))); 1066 - PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags); 1067 - if (signal_pending (current)) 1068 - return -1; 1069 - PRINTD (DBG_TX, "set tx_busy for dev %p", dev); 1070 - return 0; 1071 - } 1072 - 1073 - /********** allow another TX thread to start **********/ 1074 - 1075 - static inline void tx_release (hrz_dev * dev) { 1076 - clear_bit (tx_busy, &dev->flags); 1077 - PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev); 1078 - wake_up_interruptible (&dev->tx_queue); 1079 - } 1080 - 1081 - /********** schedule TX transfers **********/ 1082 - 1083 - static void tx_schedule (hrz_dev * const dev, int irq) { 1084 - unsigned int tx_bytes; 1085 - 1086 - int append_desc = 0; 1087 - 1088 - int pio_instead = 0; 1089 - #ifndef TAILRECURSIONWORKS 1090 - pio_instead = 1; 1091 - while (pio_instead) { 1092 - #endif 1093 - // bytes in current region waiting for TX transfer 1094 - tx_bytes = dev->tx_bytes; 1095 - 1096 - #if 0 1097 - spin_count = 0; 1098 - while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) { 1099 - PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!"); 1100 - if (++spin_count > 10) { 1101 - PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion"); 1102 - wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1103 - tx_release (dev); 1104 - hrz_kfree_skb (dev->tx_skb); 1105 - return; 1106 - } 1107 - } 1108 - #endif 1109 - 1110 - if (tx_bytes) { 1111 - // start next transfer within same region 1112 - if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) { 1113 - PRINTD (DBG_TX|DBG_BUS, "(pio)"); 1114 - pio_instead = 1; 1115 - } 1116 - if (tx_bytes <= MAX_TRANSFER_COUNT) { 1117 - PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)"); 1118 - if (!dev->tx_iovec) { 1119 - // end of last region 1120 - append_desc = 1; 1121 - } 1122 - dev->tx_bytes = 0; 1123 - } else { 1124 - PRINTD (DBG_TX|DBG_BUS, "(continuing multi)"); 1125 - dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT; 1126 - tx_bytes = MAX_TRANSFER_COUNT; 1127 - } 1128 - } else { 1129 - // tx_bytes == 0 -- we're between regions 1130 - // regions remaining to transfer 1131 - unsigned int tx_regions = dev->tx_regions; 1132 - 1133 - if (tx_regions) { 1134 - // start a new region 1135 - dev->tx_addr = dev->tx_iovec->iov_base; 1136 - tx_bytes = dev->tx_iovec->iov_len; 1137 - ++dev->tx_iovec; 1138 - dev->tx_regions = tx_regions - 1; 1139 - 1140 - if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) { 1141 - PRINTD (DBG_TX|DBG_BUS, "(pio)"); 1142 - pio_instead = 1; 1143 - } 1144 - if (tx_bytes <= MAX_TRANSFER_COUNT) { 1145 - PRINTD (DBG_TX|DBG_BUS, "(full region)"); 1146 - dev->tx_bytes = 0; 1147 - } else { 1148 - PRINTD (DBG_TX|DBG_BUS, "(start multi region)"); 1149 - dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT; 1150 - tx_bytes = MAX_TRANSFER_COUNT; 1151 - } 1152 - } else { 1153 - // tx_regions == 0 1154 - // that's all folks - end of frame 1155 - struct sk_buff * skb = dev->tx_skb; 1156 - dev->tx_iovec = NULL; 1157 - 1158 - // VC layer stats 1159 - atomic_inc(&ATM_SKB(skb)->vcc->stats->tx); 1160 - 1161 - // free the skb 1162 - hrz_kfree_skb (skb); 1163 - } 1164 - } 1165 - 1166 - // note: writing TX_COUNT clears any interrupt condition 1167 - if (tx_bytes) { 1168 - if (pio_instead) { 1169 - if (irq) 1170 - wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1171 - wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes); 1172 - if (append_desc) 1173 - wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len)); 1174 - } else { 1175 - wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr)); 1176 - if (append_desc) 1177 - wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len)); 1178 - wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 1179 - append_desc 1180 - ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC 1181 - : tx_bytes); 1182 - } 1183 - dev->tx_addr += tx_bytes; 1184 - } else { 1185 - if (irq) 1186 - wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1187 - YELLOW_LED_ON(dev); 1188 - tx_release (dev); 1189 - } 1190 - 1191 - #ifdef TAILRECURSIONWORKS 1192 - // and we all bless optimised tail calls 1193 - if (pio_instead) 1194 - return tx_schedule (dev, 0); 1195 - return; 1196 - #else 1197 - // grrrrrrr! 1198 - irq = 0; 1199 - } 1200 - return; 1201 - #endif 1202 - } 1203 - 1204 - /********** handle TX bus master complete events **********/ 1205 - 1206 - static void tx_bus_master_complete_handler (hrz_dev * dev) { 1207 - if (test_bit (tx_busy, &dev->flags)) { 1208 - tx_schedule (dev, 1); 1209 - } else { 1210 - PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion"); 1211 - // clear interrupt condition on adapter 1212 - wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1213 - } 1214 - return; 1215 - } 1216 - 1217 - /********** move RX Q pointer to next item in circular buffer **********/ 1218 - 1219 - // called only from IRQ sub-handler 1220 - static u32 rx_queue_entry_next (hrz_dev * dev) { 1221 - u32 rx_queue_entry; 1222 - spin_lock (&dev->mem_lock); 1223 - rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry); 1224 - if (dev->rx_q_entry == dev->rx_q_wrap) 1225 - dev->rx_q_entry = dev->rx_q_reset; 1226 - else 1227 - dev->rx_q_entry++; 1228 - wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset); 1229 - spin_unlock (&dev->mem_lock); 1230 - return rx_queue_entry; 1231 - } 1232 - 1233 - /********** handle RX data received by device **********/ 1234 - 1235 - // called from IRQ handler 1236 - static void rx_data_av_handler (hrz_dev * dev) { 1237 - u32 rx_queue_entry; 1238 - u32 rx_queue_entry_flags; 1239 - u16 rx_len; 1240 - u16 rx_channel; 1241 - 1242 - PRINTD (DBG_FLOW, "hrz_data_av_handler"); 1243 - 1244 - // try to grab rx lock (not possible during RX bus mastering) 1245 - if (test_and_set_bit (rx_busy, &dev->flags)) { 1246 - PRINTD (DBG_RX, "locked out of rx lock"); 1247 - return; 1248 - } 1249 - PRINTD (DBG_RX, "set rx_busy for dev %p", dev); 1250 - // lock is cleared if we fail now, o/w after bus master completion 1251 - 1252 - YELLOW_LED_OFF(dev); 1253 - 1254 - rx_queue_entry = rx_queue_entry_next (dev); 1255 - 1256 - rx_len = rx_q_entry_to_length (rx_queue_entry); 1257 - rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry); 1258 - 1259 - WAIT_FLUSH_RX_COMPLETE (dev); 1260 - 1261 - SELECT_RX_CHANNEL (dev, rx_channel); 1262 - 1263 - PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry); 1264 - rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER); 1265 - 1266 - if (!rx_len) { 1267 - // (at least) bus-mastering breaks if we try to handle a 1268 - // zero-length frame, besides AAL5 does not support them 1269 - PRINTK (KERN_ERR, "zero-length frame!"); 1270 - rx_queue_entry_flags &= ~RX_COMPLETE_FRAME; 1271 - } 1272 - 1273 - if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) { 1274 - PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!"); 1275 - } 1276 - if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) { 1277 - struct atm_vcc * atm_vcc; 1278 - 1279 - PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len); 1280 - 1281 - atm_vcc = dev->rxer[rx_channel]; 1282 - // if no vcc is assigned to this channel, we should drop the frame 1283 - // (is this what SIMONS etc. was trying to achieve?) 1284 - 1285 - if (atm_vcc) { 1286 - 1287 - if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) { 1288 - 1289 - if (rx_len <= atm_vcc->qos.rxtp.max_sdu) { 1290 - 1291 - struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC); 1292 - if (skb) { 1293 - // remember this so we can push it later 1294 - dev->rx_skb = skb; 1295 - // remember this so we can flush it later 1296 - dev->rx_channel = rx_channel; 1297 - 1298 - // prepare socket buffer 1299 - skb_put (skb, rx_len); 1300 - ATM_SKB(skb)->vcc = atm_vcc; 1301 - 1302 - // simple transfer 1303 - // dev->rx_regions = 0; 1304 - // dev->rx_iovec = 0; 1305 - dev->rx_bytes = rx_len; 1306 - dev->rx_addr = skb->data; 1307 - PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)", 1308 - skb->data, rx_len); 1309 - 1310 - // do the business 1311 - rx_schedule (dev, 0); 1312 - return; 1313 - 1314 - } else { 1315 - PRINTD (DBG_SKB|DBG_WARN, "failed to get skb"); 1316 - } 1317 - 1318 - } else { 1319 - PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel); 1320 - // do we count this? 1321 - } 1322 - 1323 - } else { 1324 - PRINTK (KERN_WARNING, "dropped over-size frame"); 1325 - // do we count this? 1326 - } 1327 - 1328 - } else { 1329 - PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)"); 1330 - // do we count this? 1331 - } 1332 - 1333 - } else { 1334 - // Wait update complete ? SPONG 1335 - } 1336 - 1337 - // RX was aborted 1338 - YELLOW_LED_ON(dev); 1339 - 1340 - FLUSH_RX_CHANNEL (dev,rx_channel); 1341 - clear_bit (rx_busy, &dev->flags); 1342 - 1343 - return; 1344 - } 1345 - 1346 - /********** interrupt handler **********/ 1347 - 1348 - static irqreturn_t interrupt_handler(int irq, void *dev_id) 1349 - { 1350 - hrz_dev *dev = dev_id; 1351 - u32 int_source; 1352 - unsigned int irq_ok; 1353 - 1354 - PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id); 1355 - 1356 - // definitely for us 1357 - irq_ok = 0; 1358 - while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF) 1359 - & INTERESTING_INTERRUPTS)) { 1360 - // In the interests of fairness, the handlers below are 1361 - // called in sequence and without immediate return to the head of 1362 - // the while loop. This is only of issue for slow hosts (or when 1363 - // debugging messages are on). Really slow hosts may find a fast 1364 - // sender keeps them permanently in the IRQ handler. :( 1365 - 1366 - // (only an issue for slow hosts) RX completion goes before 1367 - // rx_data_av as the former implies rx_busy and so the latter 1368 - // would just abort. If it reschedules another transfer 1369 - // (continuing the same frame) then it will not clear rx_busy. 1370 - 1371 - // (only an issue for slow hosts) TX completion goes before RX 1372 - // data available as it is a much shorter routine - there is the 1373 - // chance that any further transfers it schedules will be complete 1374 - // by the time of the return to the head of the while loop 1375 - 1376 - if (int_source & RX_BUS_MASTER_COMPLETE) { 1377 - ++irq_ok; 1378 - PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted"); 1379 - rx_bus_master_complete_handler (dev); 1380 - } 1381 - if (int_source & TX_BUS_MASTER_COMPLETE) { 1382 - ++irq_ok; 1383 - PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted"); 1384 - tx_bus_master_complete_handler (dev); 1385 - } 1386 - if (int_source & RX_DATA_AV) { 1387 - ++irq_ok; 1388 - PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted"); 1389 - rx_data_av_handler (dev); 1390 - } 1391 - } 1392 - if (irq_ok) { 1393 - PRINTD (DBG_IRQ, "work done: %u", irq_ok); 1394 - } else { 1395 - PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source); 1396 - } 1397 - 1398 - PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id); 1399 - if (irq_ok) 1400 - return IRQ_HANDLED; 1401 - return IRQ_NONE; 1402 - } 1403 - 1404 - /********** housekeeping **********/ 1405 - 1406 - static void do_housekeeping (struct timer_list *t) { 1407 - // just stats at the moment 1408 - hrz_dev * dev = from_timer(dev, t, housekeeping); 1409 - 1410 - // collect device-specific (not driver/atm-linux) stats here 1411 - dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF); 1412 - dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF); 1413 - dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF); 1414 - dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF); 1415 - 1416 - mod_timer (&dev->housekeeping, jiffies + HZ/10); 1417 - 1418 - return; 1419 - } 1420 - 1421 - /********** find an idle channel for TX and set it up **********/ 1422 - 1423 - // called with tx_busy set 1424 - static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) { 1425 - unsigned short idle_channels; 1426 - short tx_channel = -1; 1427 - unsigned int spin_count; 1428 - PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev); 1429 - 1430 - // better would be to fail immediately, the caller can then decide whether 1431 - // to wait or drop (depending on whether this is UBR etc.) 1432 - spin_count = 0; 1433 - while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) { 1434 - PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel"); 1435 - // delay a bit here 1436 - if (++spin_count > 100) { 1437 - PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel"); 1438 - return -EBUSY; 1439 - } 1440 - } 1441 - 1442 - // got an idle channel 1443 - { 1444 - // tx_idle ensures we look for idle channels in RR order 1445 - int chan = dev->tx_idle; 1446 - 1447 - int keep_going = 1; 1448 - while (keep_going) { 1449 - if (idle_channels & (1<<chan)) { 1450 - tx_channel = chan; 1451 - keep_going = 0; 1452 - } 1453 - ++chan; 1454 - if (chan == TX_CHANS) 1455 - chan = 0; 1456 - } 1457 - 1458 - dev->tx_idle = chan; 1459 - } 1460 - 1461 - // set up the channel we found 1462 - { 1463 - // Initialise the cell header in the transmit channel descriptor 1464 - // a.k.a. prepare the channel and remember that we have done so. 1465 - 1466 - tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel]; 1467 - u32 rd_ptr; 1468 - u32 wr_ptr; 1469 - u16 channel = vcc->channel; 1470 - 1471 - unsigned long flags; 1472 - spin_lock_irqsave (&dev->mem_lock, flags); 1473 - 1474 - // Update the transmit channel record. 1475 - dev->tx_channel_record[tx_channel] = channel; 1476 - 1477 - // xBR channel 1478 - update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS, 1479 - vcc->tx_xbr_bits); 1480 - 1481 - // Update the PCR counter preload value etc. 1482 - update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS, 1483 - vcc->tx_pcr_bits); 1484 - 1485 - #if 0 1486 - if (vcc->tx_xbr_bits == VBR_RATE_TYPE) { 1487 - // SCR timer 1488 - update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS, 1489 - vcc->tx_scr_bits); 1490 - 1491 - // Bucket size... 1492 - update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS, 1493 - vcc->tx_bucket_bits); 1494 - 1495 - // ... and fullness 1496 - update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS, 1497 - vcc->tx_bucket_bits); 1498 - } 1499 - #endif 1500 - 1501 - // Initialise the read and write buffer pointers 1502 - rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK; 1503 - wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK; 1504 - 1505 - // idle TX channels should have identical pointers 1506 - if (rd_ptr != wr_ptr) { 1507 - PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!"); 1508 - // spin_unlock... return -E... 1509 - // I wonder if gcc would get rid of one of the pointer aliases 1510 - } 1511 - PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.", 1512 - rd_ptr, wr_ptr); 1513 - 1514 - switch (vcc->aal) { 1515 - case aal0: 1516 - PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0"); 1517 - rd_ptr |= CHANNEL_TYPE_RAW_CELLS; 1518 - wr_ptr |= CHANNEL_TYPE_RAW_CELLS; 1519 - break; 1520 - case aal34: 1521 - PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34"); 1522 - rd_ptr |= CHANNEL_TYPE_AAL3_4; 1523 - wr_ptr |= CHANNEL_TYPE_AAL3_4; 1524 - break; 1525 - case aal5: 1526 - rd_ptr |= CHANNEL_TYPE_AAL5; 1527 - wr_ptr |= CHANNEL_TYPE_AAL5; 1528 - // Initialise the CRC 1529 - wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC); 1530 - break; 1531 - } 1532 - 1533 - wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr); 1534 - wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr); 1535 - 1536 - // Write the Cell Header 1537 - // Payload Type, CLP and GFC would go here if non-zero 1538 - wr_mem (dev, &tx_desc->cell_header, channel); 1539 - 1540 - spin_unlock_irqrestore (&dev->mem_lock, flags); 1541 - } 1542 - 1543 - return tx_channel; 1544 - } 1545 - 1546 - /********** send a frame **********/ 1547 - 1548 - static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) { 1549 - unsigned int spin_count; 1550 - int free_buffers; 1551 - hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 1552 - hrz_vcc * vcc = HRZ_VCC(atm_vcc); 1553 - u16 channel = vcc->channel; 1554 - 1555 - u32 buffers_required; 1556 - 1557 - /* signed for error return */ 1558 - short tx_channel; 1559 - 1560 - PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u", 1561 - channel, skb->data, skb->len); 1562 - 1563 - dump_skb (">>>", channel, skb); 1564 - 1565 - if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) { 1566 - PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel); 1567 - hrz_kfree_skb (skb); 1568 - return -EIO; 1569 - } 1570 - 1571 - // don't understand this 1572 - ATM_SKB(skb)->vcc = atm_vcc; 1573 - 1574 - if (skb->len > atm_vcc->qos.txtp.max_sdu) { 1575 - PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping..."); 1576 - hrz_kfree_skb (skb); 1577 - return -EIO; 1578 - } 1579 - 1580 - if (!channel) { 1581 - PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel"); 1582 - hrz_kfree_skb (skb); 1583 - return -EIO; 1584 - } 1585 - 1586 - #if 0 1587 - { 1588 - // where would be a better place for this? housekeeping? 1589 - u16 status; 1590 - pci_read_config_word (dev->pci_dev, PCI_STATUS, &status); 1591 - if (status & PCI_STATUS_REC_MASTER_ABORT) { 1592 - PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)"); 1593 - status &= ~PCI_STATUS_REC_MASTER_ABORT; 1594 - pci_write_config_word (dev->pci_dev, PCI_STATUS, status); 1595 - if (test_bit (tx_busy, &dev->flags)) { 1596 - hrz_kfree_skb (dev->tx_skb); 1597 - tx_release (dev); 1598 - } 1599 - } 1600 - } 1601 - #endif 1602 - 1603 - #ifdef DEBUG_HORIZON 1604 - /* wey-hey! */ 1605 - if (channel == 1023) { 1606 - unsigned int i; 1607 - unsigned short d = 0; 1608 - char * s = skb->data; 1609 - if (*s++ == 'D') { 1610 - for (i = 0; i < 4; ++i) 1611 - d = (d << 4) | hex_to_bin(*s++); 1612 - PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d); 1613 - } 1614 - } 1615 - #endif 1616 - 1617 - // wait until TX is free and grab lock 1618 - if (tx_hold (dev)) { 1619 - hrz_kfree_skb (skb); 1620 - return -ERESTARTSYS; 1621 - } 1622 - 1623 - // Wait for enough space to be available in transmit buffer memory. 1624 - 1625 - // should be number of cells needed + 2 (according to hardware docs) 1626 - // = ((framelen+8)+47) / 48 + 2 1627 - // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX 1628 - buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3; 1629 - 1630 - // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry) 1631 - spin_count = 0; 1632 - while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) { 1633 - PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d", 1634 - free_buffers, buffers_required); 1635 - // what is the appropriate delay? implement a timeout? (depending on line speed?) 1636 - // mdelay (1); 1637 - // what happens if we kill (current_pid, SIGKILL) ? 1638 - schedule(); 1639 - if (++spin_count > 1000) { 1640 - PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d", 1641 - free_buffers, buffers_required); 1642 - tx_release (dev); 1643 - hrz_kfree_skb (skb); 1644 - return -ERESTARTSYS; 1645 - } 1646 - } 1647 - 1648 - // Select a channel to transmit the frame on. 1649 - if (channel == dev->last_vc) { 1650 - PRINTD (DBG_TX, "last vc hack: hit"); 1651 - tx_channel = dev->tx_last; 1652 - } else { 1653 - PRINTD (DBG_TX, "last vc hack: miss"); 1654 - // Are we currently transmitting this VC on one of the channels? 1655 - for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel) 1656 - if (dev->tx_channel_record[tx_channel] == channel) { 1657 - PRINTD (DBG_TX, "vc already on channel: hit"); 1658 - break; 1659 - } 1660 - if (tx_channel == TX_CHANS) { 1661 - PRINTD (DBG_TX, "vc already on channel: miss"); 1662 - // Find and set up an idle channel. 1663 - tx_channel = setup_idle_tx_channel (dev, vcc); 1664 - if (tx_channel < 0) { 1665 - PRINTD (DBG_TX|DBG_ERR, "failed to get channel"); 1666 - tx_release (dev); 1667 - return tx_channel; 1668 - } 1669 - } 1670 - 1671 - PRINTD (DBG_TX, "got channel"); 1672 - SELECT_TX_CHANNEL(dev, tx_channel); 1673 - 1674 - dev->last_vc = channel; 1675 - dev->tx_last = tx_channel; 1676 - } 1677 - 1678 - PRINTD (DBG_TX, "using channel %u", tx_channel); 1679 - 1680 - YELLOW_LED_OFF(dev); 1681 - 1682 - // TX start transfer 1683 - 1684 - { 1685 - unsigned int tx_len = skb->len; 1686 - unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags; 1687 - // remember this so we can free it later 1688 - dev->tx_skb = skb; 1689 - 1690 - if (tx_iovcnt) { 1691 - // scatter gather transfer 1692 - dev->tx_regions = tx_iovcnt; 1693 - dev->tx_iovec = NULL; /* @@@ needs rewritten */ 1694 - dev->tx_bytes = 0; 1695 - PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)", 1696 - skb->data, tx_len); 1697 - tx_release (dev); 1698 - hrz_kfree_skb (skb); 1699 - return -EIO; 1700 - } else { 1701 - // simple transfer 1702 - dev->tx_regions = 0; 1703 - dev->tx_iovec = NULL; 1704 - dev->tx_bytes = tx_len; 1705 - dev->tx_addr = skb->data; 1706 - PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)", 1707 - skb->data, tx_len); 1708 - } 1709 - 1710 - // and do the business 1711 - tx_schedule (dev, 0); 1712 - 1713 - } 1714 - 1715 - return 0; 1716 - } 1717 - 1718 - /********** reset a card **********/ 1719 - 1720 - static void hrz_reset (const hrz_dev * dev) { 1721 - u32 control_0_reg = rd_regl (dev, CONTROL_0_REG); 1722 - 1723 - // why not set RESET_HORIZON to one and wait for the card to 1724 - // reassert that bit as zero? Like so: 1725 - control_0_reg = control_0_reg & RESET_HORIZON; 1726 - wr_regl (dev, CONTROL_0_REG, control_0_reg); 1727 - while (control_0_reg & RESET_HORIZON) 1728 - control_0_reg = rd_regl (dev, CONTROL_0_REG); 1729 - 1730 - // old reset code retained: 1731 - wr_regl (dev, CONTROL_0_REG, control_0_reg | 1732 - RESET_ATM | RESET_RX | RESET_TX | RESET_HOST); 1733 - // just guessing here 1734 - udelay (1000); 1735 - 1736 - wr_regl (dev, CONTROL_0_REG, control_0_reg); 1737 - } 1738 - 1739 - /********** read the burnt in address **********/ 1740 - 1741 - static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl) 1742 - { 1743 - wr_regl (dev, CONTROL_0_REG, ctrl); 1744 - udelay (5); 1745 - } 1746 - 1747 - static void CLOCK_IT (const hrz_dev *dev, u32 ctrl) 1748 - { 1749 - // DI must be valid around rising SK edge 1750 - WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK); 1751 - WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK); 1752 - } 1753 - 1754 - static u16 read_bia(const hrz_dev *dev, u16 addr) 1755 - { 1756 - u32 ctrl = rd_regl (dev, CONTROL_0_REG); 1757 - 1758 - const unsigned int addr_bits = 6; 1759 - const unsigned int data_bits = 16; 1760 - 1761 - unsigned int i; 1762 - 1763 - u16 res; 1764 - 1765 - ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI); 1766 - WRITE_IT_WAIT(dev, ctrl); 1767 - 1768 - // wake Serial EEPROM and send 110 (READ) command 1769 - ctrl |= (SEEPROM_CS | SEEPROM_DI); 1770 - CLOCK_IT(dev, ctrl); 1771 - 1772 - ctrl |= SEEPROM_DI; 1773 - CLOCK_IT(dev, ctrl); 1774 - 1775 - ctrl &= ~SEEPROM_DI; 1776 - CLOCK_IT(dev, ctrl); 1777 - 1778 - for (i=0; i<addr_bits; i++) { 1779 - if (addr & (1 << (addr_bits-1))) 1780 - ctrl |= SEEPROM_DI; 1781 - else 1782 - ctrl &= ~SEEPROM_DI; 1783 - 1784 - CLOCK_IT(dev, ctrl); 1785 - 1786 - addr = addr << 1; 1787 - } 1788 - 1789 - // we could check that we have DO = 0 here 1790 - ctrl &= ~SEEPROM_DI; 1791 - 1792 - res = 0; 1793 - for (i=0;i<data_bits;i++) { 1794 - res = res >> 1; 1795 - 1796 - CLOCK_IT(dev, ctrl); 1797 - 1798 - if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO) 1799 - res |= (1 << (data_bits-1)); 1800 - } 1801 - 1802 - ctrl &= ~(SEEPROM_SK | SEEPROM_CS); 1803 - WRITE_IT_WAIT(dev, ctrl); 1804 - 1805 - return res; 1806 - } 1807 - 1808 - /********** initialise a card **********/ 1809 - 1810 - static int hrz_init(hrz_dev *dev) 1811 - { 1812 - int onefivefive; 1813 - 1814 - u16 chan; 1815 - 1816 - int buff_count; 1817 - 1818 - HDW * mem; 1819 - 1820 - cell_buf * tx_desc; 1821 - cell_buf * rx_desc; 1822 - 1823 - u32 ctrl; 1824 - 1825 - ctrl = rd_regl (dev, CONTROL_0_REG); 1826 - PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl); 1827 - onefivefive = ctrl & ATM_LAYER_STATUS; 1828 - 1829 - if (onefivefive) 1830 - printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)"); 1831 - else 1832 - printk (DEV_LABEL ": Horizon (at 25 MBps)"); 1833 - 1834 - printk (":"); 1835 - // Reset the card to get everything in a known state 1836 - 1837 - printk (" reset"); 1838 - hrz_reset (dev); 1839 - 1840 - // Clear all the buffer memory 1841 - 1842 - printk (" clearing memory"); 1843 - 1844 - for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem) 1845 - wr_mem (dev, mem, 0); 1846 - 1847 - printk (" tx channels"); 1848 - 1849 - // All transmit eight channels are set up as AAL5 ABR channels with 1850 - // a 16us cell spacing. Why? 1851 - 1852 - // Channel 0 gets the free buffer at 100h, channel 1 gets the free 1853 - // buffer at 110h etc. 1854 - 1855 - for (chan = 0; chan < TX_CHANS; ++chan) { 1856 - tx_ch_desc * tx_desc = &memmap->tx_descs[chan]; 1857 - cell_buf * buf = &memmap->inittxbufs[chan]; 1858 - 1859 - // initialise the read and write buffer pointers 1860 - wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf)); 1861 - wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf)); 1862 - 1863 - // set the status of the initial buffers to empty 1864 - wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY); 1865 - } 1866 - 1867 - // Use space bufn3 at the moment for tx buffers 1868 - 1869 - printk (" tx buffers"); 1870 - 1871 - tx_desc = memmap->bufn3; 1872 - 1873 - wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY); 1874 - 1875 - for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) { 1876 - wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY); 1877 - tx_desc++; 1878 - } 1879 - 1880 - wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY); 1881 - 1882 - // Initialise the transmit free buffer count 1883 - wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE); 1884 - 1885 - printk (" rx channels"); 1886 - 1887 - // Initialise all of the receive channels to be AAL5 disabled with 1888 - // an interrupt threshold of 0 1889 - 1890 - for (chan = 0; chan < RX_CHANS; ++chan) { 1891 - rx_ch_desc * rx_desc = &memmap->rx_descs[chan]; 1892 - 1893 - wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED); 1894 - } 1895 - 1896 - printk (" rx buffers"); 1897 - 1898 - // Use space bufn4 at the moment for rx buffers 1899 - 1900 - rx_desc = memmap->bufn4; 1901 - 1902 - wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY); 1903 - 1904 - for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) { 1905 - wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY); 1906 - 1907 - rx_desc++; 1908 - } 1909 - 1910 - wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY); 1911 - 1912 - // Initialise the receive free buffer count 1913 - wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE); 1914 - 1915 - // Initialize Horizons registers 1916 - 1917 - // TX config 1918 - wr_regw (dev, TX_CONFIG_OFF, 1919 - ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE); 1920 - 1921 - // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0. 1922 - wr_regw (dev, RX_CONFIG_OFF, 1923 - DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits); 1924 - 1925 - // RX line config 1926 - wr_regw (dev, RX_LINE_CONFIG_OFF, 1927 - LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4); 1928 - 1929 - // Set the max AAL5 cell count to be just enough to contain the 1930 - // largest AAL5 frame that the user wants to receive 1931 - wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF, 1932 - DIV_ROUND_UP(max_rx_size + ATM_AAL5_TRAILER, ATM_CELL_PAYLOAD)); 1933 - 1934 - // Enable receive 1935 - wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE); 1936 - 1937 - printk (" control"); 1938 - 1939 - // Drive the OE of the LEDs then turn the green LED on 1940 - ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED; 1941 - wr_regl (dev, CONTROL_0_REG, ctrl); 1942 - 1943 - // Test for a 155-capable card 1944 - 1945 - if (onefivefive) { 1946 - // Select 155 mode... make this a choice (or: how do we detect 1947 - // external line speed and switch?) 1948 - ctrl |= ATM_LAYER_SELECT; 1949 - wr_regl (dev, CONTROL_0_REG, ctrl); 1950 - 1951 - // test SUNI-lite vs SAMBA 1952 - 1953 - // Register 0x00 in the SUNI will have some of bits 3-7 set, and 1954 - // they will always be zero for the SAMBA. Ha! Bloody hardware 1955 - // engineers. It'll never work. 1956 - 1957 - if (rd_framer (dev, 0) & 0x00f0) { 1958 - // SUNI 1959 - printk (" SUNI"); 1960 - 1961 - // Reset, just in case 1962 - wr_framer (dev, 0x00, 0x0080); 1963 - wr_framer (dev, 0x00, 0x0000); 1964 - 1965 - // Configure transmit FIFO 1966 - wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002); 1967 - 1968 - // Set line timed mode 1969 - wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001); 1970 - } else { 1971 - // SAMBA 1972 - printk (" SAMBA"); 1973 - 1974 - // Reset, just in case 1975 - wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001); 1976 - wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001); 1977 - 1978 - // Turn off diagnostic loopback and enable line-timed mode 1979 - wr_framer (dev, 0, 0x0002); 1980 - 1981 - // Turn on transmit outputs 1982 - wr_framer (dev, 2, 0x0B80); 1983 - } 1984 - } else { 1985 - // Select 25 mode 1986 - ctrl &= ~ATM_LAYER_SELECT; 1987 - 1988 - // Madge B154 setup 1989 - // none required? 1990 - } 1991 - 1992 - printk (" LEDs"); 1993 - 1994 - GREEN_LED_ON(dev); 1995 - YELLOW_LED_ON(dev); 1996 - 1997 - printk (" ESI="); 1998 - 1999 - { 2000 - u16 b = 0; 2001 - int i; 2002 - u8 * esi = dev->atm_dev->esi; 2003 - 2004 - // in the card I have, EEPROM 2005 - // addresses 0, 1, 2 contain 0 2006 - // addresess 5, 6 etc. contain ffff 2007 - // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order) 2008 - // the read_bia routine gets the BIA in Ethernet bit order 2009 - 2010 - for (i=0; i < ESI_LEN; ++i) { 2011 - if (i % 2 == 0) 2012 - b = read_bia (dev, i/2 + 2); 2013 - else 2014 - b = b >> 8; 2015 - esi[i] = b & 0xFF; 2016 - printk ("%02x", esi[i]); 2017 - } 2018 - } 2019 - 2020 - // Enable RX_Q and ?X_COMPLETE interrupts only 2021 - wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS); 2022 - printk (" IRQ on"); 2023 - 2024 - printk (".\n"); 2025 - 2026 - return onefivefive; 2027 - } 2028 - 2029 - /********** check max_sdu **********/ 2030 - 2031 - static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) { 2032 - PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu"); 2033 - 2034 - switch (aal) { 2035 - case aal0: 2036 - if (!(tp->max_sdu)) { 2037 - PRINTD (DBG_QOS, "defaulting max_sdu"); 2038 - tp->max_sdu = ATM_AAL0_SDU; 2039 - } else if (tp->max_sdu != ATM_AAL0_SDU) { 2040 - PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu"); 2041 - return -EINVAL; 2042 - } 2043 - break; 2044 - case aal34: 2045 - if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) { 2046 - PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default"); 2047 - tp->max_sdu = ATM_MAX_AAL34_PDU; 2048 - } 2049 - break; 2050 - case aal5: 2051 - if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) { 2052 - PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default"); 2053 - tp->max_sdu = max_frame_size; 2054 - } 2055 - break; 2056 - } 2057 - return 0; 2058 - } 2059 - 2060 - /********** check pcr **********/ 2061 - 2062 - // something like this should be part of ATM Linux 2063 - static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) { 2064 - // we are assuming non-UBR, and non-special values of pcr 2065 - if (tp->min_pcr == ATM_MAX_PCR) 2066 - PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR"); 2067 - else if (tp->min_pcr < 0) 2068 - PRINTD (DBG_QOS, "luser gave negative min_pcr"); 2069 - else if (tp->min_pcr && tp->min_pcr > pcr) 2070 - PRINTD (DBG_QOS, "pcr less than min_pcr"); 2071 - else 2072 - // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1) 2073 - // easier to #define ATM_MAX_PCR 0 and have all rates unsigned? 2074 - // [this would get rid of next two conditionals] 2075 - if ((0) && tp->max_pcr == ATM_MAX_PCR) 2076 - PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR"); 2077 - else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0) 2078 - PRINTD (DBG_QOS, "luser gave negative max_pcr"); 2079 - else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr) 2080 - PRINTD (DBG_QOS, "pcr greater than max_pcr"); 2081 - else { 2082 - // each limit unspecified or not violated 2083 - PRINTD (DBG_QOS, "xBR(pcr) OK"); 2084 - return 0; 2085 - } 2086 - PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d", 2087 - pcr, tp->min_pcr, tp->pcr, tp->max_pcr); 2088 - return -EINVAL; 2089 - } 2090 - 2091 - /********** open VC **********/ 2092 - 2093 - static int hrz_open (struct atm_vcc *atm_vcc) 2094 - { 2095 - int error; 2096 - u16 channel; 2097 - 2098 - struct atm_qos * qos; 2099 - struct atm_trafprm * txtp; 2100 - struct atm_trafprm * rxtp; 2101 - 2102 - hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 2103 - hrz_vcc vcc; 2104 - hrz_vcc * vccp; // allocated late 2105 - short vpi = atm_vcc->vpi; 2106 - int vci = atm_vcc->vci; 2107 - PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci); 2108 - 2109 - #ifdef ATM_VPI_UNSPEC 2110 - // UNSPEC is deprecated, remove this code eventually 2111 - if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) { 2112 - PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)"); 2113 - return -EINVAL; 2114 - } 2115 - #endif 2116 - 2117 - error = vpivci_to_channel (&channel, vpi, vci); 2118 - if (error) { 2119 - PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci); 2120 - return error; 2121 - } 2122 - 2123 - vcc.channel = channel; 2124 - // max speed for the moment 2125 - vcc.tx_rate = 0x0; 2126 - 2127 - qos = &atm_vcc->qos; 2128 - 2129 - // check AAL and remember it 2130 - switch (qos->aal) { 2131 - case ATM_AAL0: 2132 - // we would if it were 48 bytes and not 52! 2133 - PRINTD (DBG_QOS|DBG_VCC, "AAL0"); 2134 - vcc.aal = aal0; 2135 - break; 2136 - case ATM_AAL34: 2137 - // we would if I knew how do the SAR! 2138 - PRINTD (DBG_QOS|DBG_VCC, "AAL3/4"); 2139 - vcc.aal = aal34; 2140 - break; 2141 - case ATM_AAL5: 2142 - PRINTD (DBG_QOS|DBG_VCC, "AAL5"); 2143 - vcc.aal = aal5; 2144 - break; 2145 - default: 2146 - PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!"); 2147 - return -EINVAL; 2148 - } 2149 - 2150 - // TX traffic parameters 2151 - 2152 - // there are two, interrelated problems here: 1. the reservation of 2153 - // PCR is not a binary choice, we are given bounds and/or a 2154 - // desirable value; 2. the device is only capable of certain values, 2155 - // most of which are not integers. It is almost certainly acceptable 2156 - // to be off by a maximum of 1 to 10 cps. 2157 - 2158 - // Pragmatic choice: always store an integral PCR as that which has 2159 - // been allocated, even if we allocate a little (or a lot) less, 2160 - // after rounding. The actual allocation depends on what we can 2161 - // manage with our rate selection algorithm. The rate selection 2162 - // algorithm is given an integral PCR and a tolerance and told 2163 - // whether it should round the value up or down if the tolerance is 2164 - // exceeded; it returns: a) the actual rate selected (rounded up to 2165 - // the nearest integer), b) a bit pattern to feed to the timer 2166 - // register, and c) a failure value if no applicable rate exists. 2167 - 2168 - // Part of the job is done by atm_pcr_goal which gives us a PCR 2169 - // specification which says: EITHER grab the maximum available PCR 2170 - // (and perhaps a lower bound which we must not pass), OR grab this 2171 - // amount, rounding down if you have to (and perhaps a lower bound 2172 - // which we must not pass) OR grab this amount, rounding up if you 2173 - // have to (and perhaps an upper bound which we must not pass). If any 2174 - // bounds ARE passed we fail. Note that rounding is only rounding to 2175 - // match device limitations, we do not round down to satisfy 2176 - // bandwidth availability even if this would not violate any given 2177 - // lower bound. 2178 - 2179 - // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s 2180 - // (say) so this is not even a binary fixpoint cell rate (but this 2181 - // device can do it). To avoid this sort of hassle we use a 2182 - // tolerance parameter (currently fixed at 10 cps). 2183 - 2184 - PRINTD (DBG_QOS, "TX:"); 2185 - 2186 - txtp = &qos->txtp; 2187 - 2188 - // set up defaults for no traffic 2189 - vcc.tx_rate = 0; 2190 - // who knows what would actually happen if you try and send on this? 2191 - vcc.tx_xbr_bits = IDLE_RATE_TYPE; 2192 - vcc.tx_pcr_bits = CLOCK_DISABLE; 2193 - #if 0 2194 - vcc.tx_scr_bits = CLOCK_DISABLE; 2195 - vcc.tx_bucket_bits = 0; 2196 - #endif 2197 - 2198 - if (txtp->traffic_class != ATM_NONE) { 2199 - error = check_max_sdu (vcc.aal, txtp, max_tx_size); 2200 - if (error) { 2201 - PRINTD (DBG_QOS, "TX max_sdu check failed"); 2202 - return error; 2203 - } 2204 - 2205 - switch (txtp->traffic_class) { 2206 - case ATM_UBR: { 2207 - // we take "the PCR" as a rate-cap 2208 - // not reserved 2209 - vcc.tx_rate = 0; 2210 - make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL); 2211 - vcc.tx_xbr_bits = ABR_RATE_TYPE; 2212 - break; 2213 - } 2214 - #if 0 2215 - case ATM_ABR: { 2216 - // reserve min, allow up to max 2217 - vcc.tx_rate = 0; // ? 2218 - make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0); 2219 - vcc.tx_xbr_bits = ABR_RATE_TYPE; 2220 - break; 2221 - } 2222 - #endif 2223 - case ATM_CBR: { 2224 - int pcr = atm_pcr_goal (txtp); 2225 - rounding r; 2226 - if (!pcr) { 2227 - // down vs. up, remaining bandwidth vs. unlimited bandwidth!! 2228 - // should really have: once someone gets unlimited bandwidth 2229 - // that no more non-UBR channels can be opened until the 2230 - // unlimited one closes?? For the moment, round_down means 2231 - // greedy people actually get something and not nothing 2232 - r = round_down; 2233 - // slight race (no locking) here so we may get -EAGAIN 2234 - // later; the greedy bastards would deserve it :) 2235 - PRINTD (DBG_QOS, "snatching all remaining TX bandwidth"); 2236 - pcr = dev->tx_avail; 2237 - } else if (pcr < 0) { 2238 - r = round_down; 2239 - pcr = -pcr; 2240 - } else { 2241 - r = round_up; 2242 - } 2243 - error = make_rate_with_tolerance (dev, pcr, r, 10, 2244 - &vcc.tx_pcr_bits, &vcc.tx_rate); 2245 - if (error) { 2246 - PRINTD (DBG_QOS, "could not make rate from TX PCR"); 2247 - return error; 2248 - } 2249 - // not really clear what further checking is needed 2250 - error = atm_pcr_check (txtp, vcc.tx_rate); 2251 - if (error) { 2252 - PRINTD (DBG_QOS, "TX PCR failed consistency check"); 2253 - return error; 2254 - } 2255 - vcc.tx_xbr_bits = CBR_RATE_TYPE; 2256 - break; 2257 - } 2258 - #if 0 2259 - case ATM_VBR: { 2260 - int pcr = atm_pcr_goal (txtp); 2261 - // int scr = atm_scr_goal (txtp); 2262 - int scr = pcr/2; // just for fun 2263 - unsigned int mbs = 60; // just for fun 2264 - rounding pr; 2265 - rounding sr; 2266 - unsigned int bucket; 2267 - if (!pcr) { 2268 - pr = round_nearest; 2269 - pcr = 1<<30; 2270 - } else if (pcr < 0) { 2271 - pr = round_down; 2272 - pcr = -pcr; 2273 - } else { 2274 - pr = round_up; 2275 - } 2276 - error = make_rate_with_tolerance (dev, pcr, pr, 10, 2277 - &vcc.tx_pcr_bits, 0); 2278 - if (!scr) { 2279 - // see comments for PCR with CBR above 2280 - sr = round_down; 2281 - // slight race (no locking) here so we may get -EAGAIN 2282 - // later; the greedy bastards would deserve it :) 2283 - PRINTD (DBG_QOS, "snatching all remaining TX bandwidth"); 2284 - scr = dev->tx_avail; 2285 - } else if (scr < 0) { 2286 - sr = round_down; 2287 - scr = -scr; 2288 - } else { 2289 - sr = round_up; 2290 - } 2291 - error = make_rate_with_tolerance (dev, scr, sr, 10, 2292 - &vcc.tx_scr_bits, &vcc.tx_rate); 2293 - if (error) { 2294 - PRINTD (DBG_QOS, "could not make rate from TX SCR"); 2295 - return error; 2296 - } 2297 - // not really clear what further checking is needed 2298 - // error = atm_scr_check (txtp, vcc.tx_rate); 2299 - if (error) { 2300 - PRINTD (DBG_QOS, "TX SCR failed consistency check"); 2301 - return error; 2302 - } 2303 - // bucket calculations (from a piece of paper...) cell bucket 2304 - // capacity must be largest integer smaller than m(p-s)/p + 1 2305 - // where m = max burst size, p = pcr, s = scr 2306 - bucket = mbs*(pcr-scr)/pcr; 2307 - if (bucket*pcr != mbs*(pcr-scr)) 2308 - bucket += 1; 2309 - if (bucket > BUCKET_MAX_SIZE) { 2310 - PRINTD (DBG_QOS, "shrinking bucket from %u to %u", 2311 - bucket, BUCKET_MAX_SIZE); 2312 - bucket = BUCKET_MAX_SIZE; 2313 - } 2314 - vcc.tx_xbr_bits = VBR_RATE_TYPE; 2315 - vcc.tx_bucket_bits = bucket; 2316 - break; 2317 - } 2318 - #endif 2319 - default: { 2320 - PRINTD (DBG_QOS, "unsupported TX traffic class"); 2321 - return -EINVAL; 2322 - } 2323 - } 2324 - } 2325 - 2326 - // RX traffic parameters 2327 - 2328 - PRINTD (DBG_QOS, "RX:"); 2329 - 2330 - rxtp = &qos->rxtp; 2331 - 2332 - // set up defaults for no traffic 2333 - vcc.rx_rate = 0; 2334 - 2335 - if (rxtp->traffic_class != ATM_NONE) { 2336 - error = check_max_sdu (vcc.aal, rxtp, max_rx_size); 2337 - if (error) { 2338 - PRINTD (DBG_QOS, "RX max_sdu check failed"); 2339 - return error; 2340 - } 2341 - switch (rxtp->traffic_class) { 2342 - case ATM_UBR: { 2343 - // not reserved 2344 - break; 2345 - } 2346 - #if 0 2347 - case ATM_ABR: { 2348 - // reserve min 2349 - vcc.rx_rate = 0; // ? 2350 - break; 2351 - } 2352 - #endif 2353 - case ATM_CBR: { 2354 - int pcr = atm_pcr_goal (rxtp); 2355 - if (!pcr) { 2356 - // slight race (no locking) here so we may get -EAGAIN 2357 - // later; the greedy bastards would deserve it :) 2358 - PRINTD (DBG_QOS, "snatching all remaining RX bandwidth"); 2359 - pcr = dev->rx_avail; 2360 - } else if (pcr < 0) { 2361 - pcr = -pcr; 2362 - } 2363 - vcc.rx_rate = pcr; 2364 - // not really clear what further checking is needed 2365 - error = atm_pcr_check (rxtp, vcc.rx_rate); 2366 - if (error) { 2367 - PRINTD (DBG_QOS, "RX PCR failed consistency check"); 2368 - return error; 2369 - } 2370 - break; 2371 - } 2372 - #if 0 2373 - case ATM_VBR: { 2374 - // int scr = atm_scr_goal (rxtp); 2375 - int scr = 1<<16; // just for fun 2376 - if (!scr) { 2377 - // slight race (no locking) here so we may get -EAGAIN 2378 - // later; the greedy bastards would deserve it :) 2379 - PRINTD (DBG_QOS, "snatching all remaining RX bandwidth"); 2380 - scr = dev->rx_avail; 2381 - } else if (scr < 0) { 2382 - scr = -scr; 2383 - } 2384 - vcc.rx_rate = scr; 2385 - // not really clear what further checking is needed 2386 - // error = atm_scr_check (rxtp, vcc.rx_rate); 2387 - if (error) { 2388 - PRINTD (DBG_QOS, "RX SCR failed consistency check"); 2389 - return error; 2390 - } 2391 - break; 2392 - } 2393 - #endif 2394 - default: { 2395 - PRINTD (DBG_QOS, "unsupported RX traffic class"); 2396 - return -EINVAL; 2397 - } 2398 - } 2399 - } 2400 - 2401 - 2402 - // late abort useful for diagnostics 2403 - if (vcc.aal != aal5) { 2404 - PRINTD (DBG_QOS, "AAL not supported"); 2405 - return -EINVAL; 2406 - } 2407 - 2408 - // get space for our vcc stuff and copy parameters into it 2409 - vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL); 2410 - if (!vccp) { 2411 - PRINTK (KERN_ERR, "out of memory!"); 2412 - return -ENOMEM; 2413 - } 2414 - *vccp = vcc; 2415 - 2416 - // clear error and grab cell rate resource lock 2417 - error = 0; 2418 - spin_lock (&dev->rate_lock); 2419 - 2420 - if (vcc.tx_rate > dev->tx_avail) { 2421 - PRINTD (DBG_QOS, "not enough TX PCR left"); 2422 - error = -EAGAIN; 2423 - } 2424 - 2425 - if (vcc.rx_rate > dev->rx_avail) { 2426 - PRINTD (DBG_QOS, "not enough RX PCR left"); 2427 - error = -EAGAIN; 2428 - } 2429 - 2430 - if (!error) { 2431 - // really consume cell rates 2432 - dev->tx_avail -= vcc.tx_rate; 2433 - dev->rx_avail -= vcc.rx_rate; 2434 - PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR", 2435 - vcc.tx_rate, vcc.rx_rate); 2436 - } 2437 - 2438 - // release lock and exit on error 2439 - spin_unlock (&dev->rate_lock); 2440 - if (error) { 2441 - PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources"); 2442 - kfree (vccp); 2443 - return error; 2444 - } 2445 - 2446 - // this is "immediately before allocating the connection identifier 2447 - // in hardware" - so long as the next call does not fail :) 2448 - set_bit(ATM_VF_ADDR,&atm_vcc->flags); 2449 - 2450 - // any errors here are very serious and should never occur 2451 - 2452 - if (rxtp->traffic_class != ATM_NONE) { 2453 - if (dev->rxer[channel]) { 2454 - PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX"); 2455 - error = -EBUSY; 2456 - } 2457 - if (!error) 2458 - error = hrz_open_rx (dev, channel); 2459 - if (error) { 2460 - kfree (vccp); 2461 - return error; 2462 - } 2463 - // this link allows RX frames through 2464 - dev->rxer[channel] = atm_vcc; 2465 - } 2466 - 2467 - // success, set elements of atm_vcc 2468 - atm_vcc->dev_data = (void *) vccp; 2469 - 2470 - // indicate readiness 2471 - set_bit(ATM_VF_READY,&atm_vcc->flags); 2472 - 2473 - return 0; 2474 - } 2475 - 2476 - /********** close VC **********/ 2477 - 2478 - static void hrz_close (struct atm_vcc * atm_vcc) { 2479 - hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 2480 - hrz_vcc * vcc = HRZ_VCC(atm_vcc); 2481 - u16 channel = vcc->channel; 2482 - PRINTD (DBG_VCC|DBG_FLOW, "hrz_close"); 2483 - 2484 - // indicate unreadiness 2485 - clear_bit(ATM_VF_READY,&atm_vcc->flags); 2486 - 2487 - if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) { 2488 - unsigned int i; 2489 - 2490 - // let any TX on this channel that has started complete 2491 - // no restart, just keep trying 2492 - while (tx_hold (dev)) 2493 - ; 2494 - // remove record of any tx_channel having been setup for this channel 2495 - for (i = 0; i < TX_CHANS; ++i) 2496 - if (dev->tx_channel_record[i] == channel) { 2497 - dev->tx_channel_record[i] = -1; 2498 - break; 2499 - } 2500 - if (dev->last_vc == channel) 2501 - dev->tx_last = -1; 2502 - tx_release (dev); 2503 - } 2504 - 2505 - if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) { 2506 - // disable RXing - it tries quite hard 2507 - hrz_close_rx (dev, channel); 2508 - // forget the vcc - no more skbs will be pushed 2509 - if (atm_vcc != dev->rxer[channel]) 2510 - PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p", 2511 - "arghhh! we're going to die!", 2512 - atm_vcc, dev->rxer[channel]); 2513 - dev->rxer[channel] = NULL; 2514 - } 2515 - 2516 - // atomically release our rate reservation 2517 - spin_lock (&dev->rate_lock); 2518 - PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR", 2519 - vcc->tx_rate, vcc->rx_rate); 2520 - dev->tx_avail += vcc->tx_rate; 2521 - dev->rx_avail += vcc->rx_rate; 2522 - spin_unlock (&dev->rate_lock); 2523 - 2524 - // free our structure 2525 - kfree (vcc); 2526 - // say the VPI/VCI is free again 2527 - clear_bit(ATM_VF_ADDR,&atm_vcc->flags); 2528 - } 2529 - 2530 - #if 0 2531 - static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) { 2532 - hrz_dev * dev = HRZ_DEV(atm_dev); 2533 - PRINTD (DBG_FLOW, "hrz_ioctl"); 2534 - return -1; 2535 - } 2536 - 2537 - unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) { 2538 - hrz_dev * dev = HRZ_DEV(atm_dev); 2539 - PRINTD (DBG_FLOW, "hrz_phy_get"); 2540 - return 0; 2541 - } 2542 - 2543 - static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value, 2544 - unsigned long addr) { 2545 - hrz_dev * dev = HRZ_DEV(atm_dev); 2546 - PRINTD (DBG_FLOW, "hrz_phy_put"); 2547 - } 2548 - 2549 - static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) { 2550 - hrz_dev * dev = HRZ_DEV(vcc->dev); 2551 - PRINTD (DBG_FLOW, "hrz_change_qos"); 2552 - return -1; 2553 - } 2554 - #endif 2555 - 2556 - /********** proc file contents **********/ 2557 - 2558 - static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) { 2559 - hrz_dev * dev = HRZ_DEV(atm_dev); 2560 - int left = *pos; 2561 - PRINTD (DBG_FLOW, "hrz_proc_read"); 2562 - 2563 - /* more diagnostics here? */ 2564 - 2565 - #if 0 2566 - if (!left--) { 2567 - unsigned int count = sprintf (page, "vbr buckets:"); 2568 - unsigned int i; 2569 - for (i = 0; i < TX_CHANS; ++i) 2570 - count += sprintf (page, " %u/%u", 2571 - query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS), 2572 - query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS)); 2573 - count += sprintf (page+count, ".\n"); 2574 - return count; 2575 - } 2576 - #endif 2577 - 2578 - if (!left--) 2579 - return sprintf (page, 2580 - "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n", 2581 - dev->tx_cell_count, dev->rx_cell_count, 2582 - dev->hec_error_count, dev->unassigned_cell_count); 2583 - 2584 - if (!left--) 2585 - return sprintf (page, 2586 - "free cell buffers: TX %hu, RX %hu+%hu.\n", 2587 - rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF), 2588 - rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF), 2589 - dev->noof_spare_buffers); 2590 - 2591 - if (!left--) 2592 - return sprintf (page, 2593 - "cps remaining: TX %u, RX %u\n", 2594 - dev->tx_avail, dev->rx_avail); 2595 - 2596 - return 0; 2597 - } 2598 - 2599 - static const struct atmdev_ops hrz_ops = { 2600 - .open = hrz_open, 2601 - .close = hrz_close, 2602 - .send = hrz_send, 2603 - .proc_read = hrz_proc_read, 2604 - .owner = THIS_MODULE, 2605 - }; 2606 - 2607 - static int hrz_probe(struct pci_dev *pci_dev, 2608 - const struct pci_device_id *pci_ent) 2609 - { 2610 - hrz_dev * dev; 2611 - int err = 0; 2612 - 2613 - // adapter slot free, read resources from PCI configuration space 2614 - u32 iobase = pci_resource_start (pci_dev, 0); 2615 - u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1)); 2616 - unsigned int irq; 2617 - unsigned char lat; 2618 - 2619 - PRINTD (DBG_FLOW, "hrz_probe"); 2620 - 2621 - if (pci_enable_device(pci_dev)) 2622 - return -EINVAL; 2623 - 2624 - /* XXX DEV_LABEL is a guess */ 2625 - if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) { 2626 - err = -EINVAL; 2627 - goto out_disable; 2628 - } 2629 - 2630 - dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL); 2631 - if (!dev) { 2632 - // perhaps we should be nice: deregister all adapters and abort? 2633 - PRINTD(DBG_ERR, "out of memory"); 2634 - err = -ENOMEM; 2635 - goto out_release; 2636 - } 2637 - 2638 - pci_set_drvdata(pci_dev, dev); 2639 - 2640 - // grab IRQ and install handler - move this someplace more sensible 2641 - irq = pci_dev->irq; 2642 - if (request_irq(irq, 2643 - interrupt_handler, 2644 - IRQF_SHARED, /* irqflags guess */ 2645 - DEV_LABEL, /* name guess */ 2646 - dev)) { 2647 - PRINTD(DBG_WARN, "request IRQ failed!"); 2648 - err = -EINVAL; 2649 - goto out_free; 2650 - } 2651 - 2652 - PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p", 2653 - iobase, irq, membase); 2654 - 2655 - dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1, 2656 - NULL); 2657 - if (!(dev->atm_dev)) { 2658 - PRINTD(DBG_ERR, "failed to register Madge ATM adapter"); 2659 - err = -EINVAL; 2660 - goto out_free_irq; 2661 - } 2662 - 2663 - PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p", 2664 - dev->atm_dev->number, dev, dev->atm_dev); 2665 - dev->atm_dev->dev_data = (void *) dev; 2666 - dev->pci_dev = pci_dev; 2667 - 2668 - // enable bus master accesses 2669 - pci_set_master(pci_dev); 2670 - 2671 - // frobnicate latency (upwards, usually) 2672 - pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat); 2673 - if (pci_lat) { 2674 - PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu", 2675 - "changing", lat, pci_lat); 2676 - pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat); 2677 - } else if (lat < MIN_PCI_LATENCY) { 2678 - PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu", 2679 - "increasing", lat, MIN_PCI_LATENCY); 2680 - pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY); 2681 - } 2682 - 2683 - dev->iobase = iobase; 2684 - dev->irq = irq; 2685 - dev->membase = membase; 2686 - 2687 - dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0]; 2688 - dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1]; 2689 - 2690 - // these next three are performance hacks 2691 - dev->last_vc = -1; 2692 - dev->tx_last = -1; 2693 - dev->tx_idle = 0; 2694 - 2695 - dev->tx_regions = 0; 2696 - dev->tx_bytes = 0; 2697 - dev->tx_skb = NULL; 2698 - dev->tx_iovec = NULL; 2699 - 2700 - dev->tx_cell_count = 0; 2701 - dev->rx_cell_count = 0; 2702 - dev->hec_error_count = 0; 2703 - dev->unassigned_cell_count = 0; 2704 - 2705 - dev->noof_spare_buffers = 0; 2706 - 2707 - { 2708 - unsigned int i; 2709 - for (i = 0; i < TX_CHANS; ++i) 2710 - dev->tx_channel_record[i] = -1; 2711 - } 2712 - 2713 - dev->flags = 0; 2714 - 2715 - // Allocate cell rates and remember ASIC version 2716 - // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53 2717 - // Copper: (WRONG) we want 6 into the above, close to 25Mb/s 2718 - // Copper: (plagarise!) 25600000/8/270*260/53 - n/53 2719 - 2720 - if (hrz_init(dev)) { 2721 - // to be really pedantic, this should be ATM_OC3c_PCR 2722 - dev->tx_avail = ATM_OC3_PCR; 2723 - dev->rx_avail = ATM_OC3_PCR; 2724 - set_bit(ultra, &dev->flags); // NOT "|= ultra" ! 2725 - } else { 2726 - dev->tx_avail = ((25600000/8)*26)/(27*53); 2727 - dev->rx_avail = ((25600000/8)*26)/(27*53); 2728 - PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering."); 2729 - } 2730 - 2731 - // rate changes spinlock 2732 - spin_lock_init(&dev->rate_lock); 2733 - 2734 - // on-board memory access spinlock; we want atomic reads and 2735 - // writes to adapter memory (handles IRQ and SMP) 2736 - spin_lock_init(&dev->mem_lock); 2737 - 2738 - init_waitqueue_head(&dev->tx_queue); 2739 - 2740 - // vpi in 0..4, vci in 6..10 2741 - dev->atm_dev->ci_range.vpi_bits = vpi_bits; 2742 - dev->atm_dev->ci_range.vci_bits = 10-vpi_bits; 2743 - 2744 - timer_setup(&dev->housekeeping, do_housekeeping, 0); 2745 - mod_timer(&dev->housekeeping, jiffies); 2746 - 2747 - out: 2748 - return err; 2749 - 2750 - out_free_irq: 2751 - free_irq(irq, dev); 2752 - out_free: 2753 - kfree(dev); 2754 - out_release: 2755 - release_region(iobase, HRZ_IO_EXTENT); 2756 - out_disable: 2757 - pci_disable_device(pci_dev); 2758 - goto out; 2759 - } 2760 - 2761 - static void hrz_remove_one(struct pci_dev *pci_dev) 2762 - { 2763 - hrz_dev *dev; 2764 - 2765 - dev = pci_get_drvdata(pci_dev); 2766 - 2767 - PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev); 2768 - del_timer_sync(&dev->housekeeping); 2769 - hrz_reset(dev); 2770 - atm_dev_deregister(dev->atm_dev); 2771 - free_irq(dev->irq, dev); 2772 - release_region(dev->iobase, HRZ_IO_EXTENT); 2773 - kfree(dev); 2774 - 2775 - pci_disable_device(pci_dev); 2776 - } 2777 - 2778 - static void __init hrz_check_args (void) { 2779 - #ifdef DEBUG_HORIZON 2780 - PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK); 2781 - #else 2782 - if (debug) 2783 - PRINTK (KERN_NOTICE, "no debug support in this image"); 2784 - #endif 2785 - 2786 - if (vpi_bits > HRZ_MAX_VPI) 2787 - PRINTK (KERN_ERR, "vpi_bits has been limited to %hu", 2788 - vpi_bits = HRZ_MAX_VPI); 2789 - 2790 - if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT) 2791 - PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu", 2792 - max_tx_size = TX_AAL5_LIMIT); 2793 - 2794 - if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT) 2795 - PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu", 2796 - max_rx_size = RX_AAL5_LIMIT); 2797 - 2798 - return; 2799 - } 2800 - 2801 - MODULE_AUTHOR(maintainer_string); 2802 - MODULE_DESCRIPTION(description_string); 2803 - MODULE_LICENSE("GPL"); 2804 - module_param(debug, ushort, 0644); 2805 - module_param(vpi_bits, ushort, 0); 2806 - module_param(max_tx_size, int, 0); 2807 - module_param(max_rx_size, int, 0); 2808 - module_param(pci_lat, byte, 0); 2809 - MODULE_PARM_DESC(debug, "debug bitmap, see .h file"); 2810 - MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs"); 2811 - MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames"); 2812 - MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames"); 2813 - MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles"); 2814 - 2815 - static const struct pci_device_id hrz_pci_tbl[] = { 2816 - { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID, 2817 - 0, 0, 0 }, 2818 - { 0, } 2819 - }; 2820 - 2821 - MODULE_DEVICE_TABLE(pci, hrz_pci_tbl); 2822 - 2823 - static struct pci_driver hrz_driver = { 2824 - .name = "horizon", 2825 - .probe = hrz_probe, 2826 - .remove = hrz_remove_one, 2827 - .id_table = hrz_pci_tbl, 2828 - }; 2829 - 2830 - /********** module entry **********/ 2831 - 2832 - static int __init hrz_module_init (void) { 2833 - BUILD_BUG_ON(sizeof(struct MEMMAP) != 128*1024/4); 2834 - 2835 - show_version(); 2836 - 2837 - // check arguments 2838 - hrz_check_args(); 2839 - 2840 - // get the juice 2841 - return pci_register_driver(&hrz_driver); 2842 - } 2843 - 2844 - /********** module exit **********/ 2845 - 2846 - static void __exit hrz_module_exit (void) { 2847 - PRINTD (DBG_FLOW, "cleanup_module"); 2848 - 2849 - pci_unregister_driver(&hrz_driver); 2850 - } 2851 - 2852 - module_init(hrz_module_init); 2853 - module_exit(hrz_module_exit);
-492
drivers/atm/horizon.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - Madge Horizon ATM Adapter driver. 4 - Copyright (C) 1995-1999 Madge Networks Ltd. 5 - 6 - */ 7 - 8 - /* 9 - IMPORTANT NOTE: Madge Networks no longer makes the adapters 10 - supported by this driver and makes no commitment to maintain it. 11 - */ 12 - 13 - /* too many macros - change to inline functions */ 14 - 15 - #ifndef DRIVER_ATM_HORIZON_H 16 - #define DRIVER_ATM_HORIZON_H 17 - 18 - 19 - #ifdef CONFIG_ATM_HORIZON_DEBUG 20 - #define DEBUG_HORIZON 21 - #endif 22 - 23 - #define DEV_LABEL "hrz" 24 - 25 - #ifndef PCI_VENDOR_ID_MADGE 26 - #define PCI_VENDOR_ID_MADGE 0x10B6 27 - #endif 28 - #ifndef PCI_DEVICE_ID_MADGE_HORIZON 29 - #define PCI_DEVICE_ID_MADGE_HORIZON 0x1000 30 - #endif 31 - 32 - // diagnostic output 33 - 34 - #define PRINTK(severity,format,args...) \ 35 - printk(severity DEV_LABEL ": " format "\n" , ## args) 36 - 37 - #ifdef DEBUG_HORIZON 38 - 39 - #define DBG_ERR 0x0001 40 - #define DBG_WARN 0x0002 41 - #define DBG_INFO 0x0004 42 - #define DBG_VCC 0x0008 43 - #define DBG_QOS 0x0010 44 - #define DBG_TX 0x0020 45 - #define DBG_RX 0x0040 46 - #define DBG_SKB 0x0080 47 - #define DBG_IRQ 0x0100 48 - #define DBG_FLOW 0x0200 49 - #define DBG_BUS 0x0400 50 - #define DBG_REGS 0x0800 51 - #define DBG_DATA 0x1000 52 - #define DBG_MASK 0x1fff 53 - 54 - /* the ## prevents the annoying double expansion of the macro arguments */ 55 - /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */ 56 - #define PRINTDB(bits,format,args...) \ 57 - ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 ) 58 - #define PRINTDM(bits,format,args...) \ 59 - ( (debug & (bits)) ? printk (format , ## args) : 1 ) 60 - #define PRINTDE(bits,format,args...) \ 61 - ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 ) 62 - #define PRINTD(bits,format,args...) \ 63 - ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 ) 64 - 65 - #else 66 - 67 - #define PRINTD(bits,format,args...) 68 - #define PRINTDB(bits,format,args...) 69 - #define PRINTDM(bits,format,args...) 70 - #define PRINTDE(bits,format,args...) 71 - 72 - #endif 73 - 74 - #define PRINTDD(sec,fmt,args...) 75 - #define PRINTDDB(sec,fmt,args...) 76 - #define PRINTDDM(sec,fmt,args...) 77 - #define PRINTDDE(sec,fmt,args...) 78 - 79 - // fixed constants 80 - 81 - #define SPARE_BUFFER_POOL_SIZE MAX_VCS 82 - #define HRZ_MAX_VPI 4 83 - #define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL 84 - 85 - /* Horizon specific bits */ 86 - /* Register offsets */ 87 - 88 - #define HRZ_IO_EXTENT 0x80 89 - 90 - #define DATA_PORT_OFF 0x00 91 - #define TX_CHANNEL_PORT_OFF 0x04 92 - #define TX_DESCRIPTOR_PORT_OFF 0x08 93 - #define MEMORY_PORT_OFF 0x0C 94 - #define MEM_WR_ADDR_REG_OFF 0x14 95 - #define MEM_RD_ADDR_REG_OFF 0x18 96 - #define CONTROL_0_REG 0x1C 97 - #define INT_SOURCE_REG_OFF 0x20 98 - #define INT_ENABLE_REG_OFF 0x24 99 - #define MASTER_RX_ADDR_REG_OFF 0x28 100 - #define MASTER_RX_COUNT_REG_OFF 0x2C 101 - #define MASTER_TX_ADDR_REG_OFF 0x30 102 - #define MASTER_TX_COUNT_REG_OFF 0x34 103 - #define TX_DESCRIPTOR_REG_OFF 0x38 104 - #define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40 105 - #define TX_CHANNEL_CONFIG_DATA_OFF 0x44 106 - #define TX_FREE_BUFFER_COUNT_OFF 0x48 107 - #define RX_FREE_BUFFER_COUNT_OFF 0x4C 108 - #define TX_CONFIG_OFF 0x50 109 - #define TX_STATUS_OFF 0x54 110 - #define RX_CONFIG_OFF 0x58 111 - #define RX_LINE_CONFIG_OFF 0x5C 112 - #define RX_QUEUE_RD_PTR_OFF 0x60 113 - #define RX_QUEUE_WR_PTR_OFF 0x64 114 - #define MAX_AAL5_CELL_COUNT_OFF 0x68 115 - #define RX_CHANNEL_PORT_OFF 0x6C 116 - #define TX_CELL_COUNT_OFF 0x70 117 - #define RX_CELL_COUNT_OFF 0x74 118 - #define HEC_ERROR_COUNT_OFF 0x78 119 - #define UNASSIGNED_CELL_COUNT_OFF 0x7C 120 - 121 - /* Register bit definitions */ 122 - 123 - /* Control 0 register */ 124 - 125 - #define SEEPROM_DO 0x00000001 126 - #define SEEPROM_DI 0x00000002 127 - #define SEEPROM_SK 0x00000004 128 - #define SEEPROM_CS 0x00000008 129 - #define DEBUG_BIT_0 0x00000010 130 - #define DEBUG_BIT_1 0x00000020 131 - #define DEBUG_BIT_2 0x00000040 132 - // RESERVED 0x00000080 133 - #define DEBUG_BIT_0_OE 0x00000100 134 - #define DEBUG_BIT_1_OE 0x00000200 135 - #define DEBUG_BIT_2_OE 0x00000400 136 - // RESERVED 0x00000800 137 - #define DEBUG_BIT_0_STATE 0x00001000 138 - #define DEBUG_BIT_1_STATE 0x00002000 139 - #define DEBUG_BIT_2_STATE 0x00004000 140 - // RESERVED 0x00008000 141 - #define GENERAL_BIT_0 0x00010000 142 - #define GENERAL_BIT_1 0x00020000 143 - #define GENERAL_BIT_2 0x00040000 144 - #define GENERAL_BIT_3 0x00080000 145 - #define RESET_HORIZON 0x00100000 146 - #define RESET_ATM 0x00200000 147 - #define RESET_RX 0x00400000 148 - #define RESET_TX 0x00800000 149 - #define RESET_HOST 0x01000000 150 - // RESERVED 0x02000000 151 - #define TARGET_RETRY_DISABLE 0x04000000 152 - #define ATM_LAYER_SELECT 0x08000000 153 - #define ATM_LAYER_STATUS 0x10000000 154 - // RESERVED 0xE0000000 155 - 156 - /* Interrupt source and enable registers */ 157 - 158 - #define RX_DATA_AV 0x00000001 159 - #define RX_DISABLED 0x00000002 160 - #define TIMING_MARKER 0x00000004 161 - #define FORCED 0x00000008 162 - #define RX_BUS_MASTER_COMPLETE 0x00000010 163 - #define TX_BUS_MASTER_COMPLETE 0x00000020 164 - #define ABR_TX_CELL_COUNT_INT 0x00000040 165 - #define DEBUG_INT 0x00000080 166 - // RESERVED 0xFFFFFF00 167 - 168 - /* PIO and Bus Mastering */ 169 - 170 - #define MAX_PIO_COUNT 0x000000ff // 255 - make tunable? 171 - // 8188 is a hard limit for bus mastering 172 - #define MAX_TRANSFER_COUNT 0x00001ffc // 8188 173 - #define MASTER_TX_AUTO_APPEND_DESC 0x80000000 174 - 175 - /* TX channel config command port */ 176 - 177 - #define PCR_TIMER_ACCESS 0x0000 178 - #define SCR_TIMER_ACCESS 0x0001 179 - #define BUCKET_CAPACITY_ACCESS 0x0002 180 - #define BUCKET_FULLNESS_ACCESS 0x0003 181 - #define RATE_TYPE_ACCESS 0x0004 182 - // UNUSED 0x00F8 183 - #define TX_CHANNEL_CONFIG_MULT 0x0100 184 - // UNUSED 0xF800 185 - #define BUCKET_MAX_SIZE 0x003f 186 - 187 - /* TX channel config data port */ 188 - 189 - #define CLOCK_SELECT_SHIFT 4 190 - #define CLOCK_DISABLE 0x00ff 191 - 192 - #define IDLE_RATE_TYPE 0x0 193 - #define ABR_RATE_TYPE 0x1 194 - #define VBR_RATE_TYPE 0x2 195 - #define CBR_RATE_TYPE 0x3 196 - 197 - /* TX config register */ 198 - 199 - #define DRVR_DRVRBAR_ENABLE 0x0001 200 - #define TXCLK_MUX_SELECT_RCLK 0x0002 201 - #define TRANSMIT_TIMING_MARKER 0x0004 202 - #define LOOPBACK_TIMING_MARKER 0x0008 203 - #define TX_TEST_MODE_16MHz 0x0000 204 - #define TX_TEST_MODE_8MHz 0x0010 205 - #define TX_TEST_MODE_5_33MHz 0x0020 206 - #define TX_TEST_MODE_4MHz 0x0030 207 - #define TX_TEST_MODE_3_2MHz 0x0040 208 - #define TX_TEST_MODE_2_66MHz 0x0050 209 - #define TX_TEST_MODE_2_29MHz 0x0060 210 - #define TX_NORMAL_OPERATION 0x0070 211 - #define ABR_ROUND_ROBIN 0x0080 212 - 213 - /* TX status register */ 214 - 215 - #define IDLE_CHANNELS_MASK 0x00FF 216 - #define ABR_CELL_COUNT_REACHED_MULT 0x0100 217 - #define ABR_CELL_COUNT_REACHED_MASK 0xFF 218 - 219 - /* RX config register */ 220 - 221 - #define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008 222 - #define RX_ENABLE 0x0010 223 - #define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000 224 - #define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020 225 - #define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040 226 - 227 - /* RX line config register */ 228 - 229 - #define SIGNAL_LOSS 0x0001 230 - #define FREQUENCY_DETECT_ERROR 0x0002 231 - #define LOCK_DETECT_ERROR 0x0004 232 - #define SELECT_INTERNAL_LOOPBACK 0x0008 233 - #define LOCK_DETECT_ENABLE 0x0010 234 - #define FREQUENCY_DETECT_ENABLE 0x0020 235 - #define USER_FRAQ 0x0040 236 - #define GXTALOUT_SELECT_DIV4 0x0080 237 - #define GXTALOUT_SELECT_NO_GATING 0x0100 238 - #define TIMING_MARKER_RECEIVED 0x0200 239 - 240 - /* RX channel port */ 241 - 242 - #define RX_CHANNEL_MASK 0x03FF 243 - // UNUSED 0x3C00 244 - #define FLUSH_CHANNEL 0x4000 245 - #define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000 246 - 247 - /* Receive queue entry */ 248 - 249 - #define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF 250 - #define RX_Q_ENTRY_CHANNEL_SHIFT 16 251 - #define SIMONS_DODGEY_MARKER 0x08000000 252 - #define RX_CONGESTION_EXPERIENCED 0x10000000 253 - #define RX_CRC_10_OK 0x20000000 254 - #define RX_CRC_32_OK 0x40000000 255 - #define RX_COMPLETE_FRAME 0x80000000 256 - 257 - /* Offsets and constants for use with the buffer memory */ 258 - 259 - /* Buffer pointers and channel types */ 260 - 261 - #define BUFFER_PTR_MASK 0x0000FFFF 262 - #define RX_INT_THRESHOLD_MULT 0x00010000 263 - #define RX_INT_THRESHOLD_MASK 0x07FF 264 - #define INT_EVERY_N_CELLS 0x08000000 265 - #define CONGESTION_EXPERIENCED 0x10000000 266 - #define FIRST_CELL_OF_AAL5_FRAME 0x20000000 267 - #define CHANNEL_TYPE_AAL5 0x00000000 268 - #define CHANNEL_TYPE_RAW_CELLS 0x40000000 269 - #define CHANNEL_TYPE_AAL3_4 0x80000000 270 - 271 - /* Buffer status stuff */ 272 - 273 - #define BUFF_STATUS_MASK 0x00030000 274 - #define BUFF_STATUS_EMPTY 0x00000000 275 - #define BUFF_STATUS_CELL_AV 0x00010000 276 - #define BUFF_STATUS_LAST_CELL_AV 0x00020000 277 - 278 - /* Transmit channel stuff */ 279 - 280 - /* Receive channel stuff */ 281 - 282 - #define RX_CHANNEL_DISABLED 0x00000000 283 - #define RX_CHANNEL_IDLE 0x00000001 284 - 285 - /* General things */ 286 - 287 - #define INITIAL_CRC 0xFFFFFFFF 288 - 289 - // A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit) 290 - // word addresses and so standard C pointer operations break (as they 291 - // assume byte addresses); so we pretend that Horizon words (and word 292 - // pointers) are bytes (and byte pointers) for the purposes of having 293 - // a memory map that works. 294 - 295 - typedef u8 HDW; 296 - 297 - typedef struct cell_buf { 298 - HDW payload[12]; 299 - HDW next; 300 - HDW cell_count; // AAL5 rx bufs 301 - HDW res; 302 - union { 303 - HDW partial_crc; // AAL5 rx bufs 304 - HDW cell_header; // RAW bufs 305 - } u; 306 - } cell_buf; 307 - 308 - typedef struct tx_ch_desc { 309 - HDW rd_buf_type; 310 - HDW wr_buf_type; 311 - HDW partial_crc; 312 - HDW cell_header; 313 - } tx_ch_desc; 314 - 315 - typedef struct rx_ch_desc { 316 - HDW wr_buf_type; 317 - HDW rd_buf_type; 318 - } rx_ch_desc; 319 - 320 - typedef struct rx_q_entry { 321 - HDW entry; 322 - } rx_q_entry; 323 - 324 - #define TX_CHANS 8 325 - #define RX_CHANS 1024 326 - #define RX_QS 1024 327 - #define MAX_VCS RX_CHANS 328 - 329 - /* Horizon buffer memory map */ 330 - 331 - // TX Channel Descriptors 2 332 - // TX Initial Buffers 8 // TX_CHANS 333 - #define BUFN1_SIZE 118 // (126 - TX_CHANS) 334 - // RX/TX Start/End Buffers 4 335 - #define BUFN2_SIZE 124 336 - // RX Queue Entries 64 337 - #define BUFN3_SIZE 192 338 - // RX Channel Descriptors 128 339 - #define BUFN4_SIZE 1408 340 - // TOTAL cell_buff chunks 2048 341 - 342 - // cell_buf bufs[2048]; 343 - // HDW dws[32768]; 344 - 345 - typedef struct MEMMAP { 346 - tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020 347 - cell_buf inittxbufs[TX_CHANS]; // these are really 348 - cell_buf bufn1[BUFN1_SIZE]; // part of this pool 349 - cell_buf txfreebufstart; 350 - cell_buf txfreebufend; 351 - cell_buf rxfreebufstart; 352 - cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254 353 - cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000 354 - rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400 355 - cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000 356 - rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800 357 - cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000 358 - } MEMMAP; 359 - 360 - #define memmap ((MEMMAP *)0) 361 - 362 - /* end horizon specific bits */ 363 - 364 - typedef enum { 365 - aal0, 366 - aal34, 367 - aal5 368 - } hrz_aal; 369 - 370 - typedef enum { 371 - tx_busy, 372 - rx_busy, 373 - ultra 374 - } hrz_flags; 375 - 376 - // a single struct pointed to by atm_vcc->dev_data 377 - 378 - typedef struct { 379 - unsigned int tx_rate; 380 - unsigned int rx_rate; 381 - u16 channel; 382 - u16 tx_xbr_bits; 383 - u16 tx_pcr_bits; 384 - #if 0 385 - u16 tx_scr_bits; 386 - u16 tx_bucket_bits; 387 - #endif 388 - hrz_aal aal; 389 - } hrz_vcc; 390 - 391 - struct hrz_dev { 392 - 393 - u32 iobase; 394 - u32 * membase; 395 - 396 - struct sk_buff * rx_skb; // skb being RXed 397 - unsigned int rx_bytes; // bytes remaining to RX within region 398 - void * rx_addr; // addr to send bytes to (for PIO) 399 - unsigned int rx_channel; // channel that the skb is going out on 400 - 401 - struct sk_buff * tx_skb; // skb being TXed 402 - unsigned int tx_bytes; // bytes remaining to TX within region 403 - void * tx_addr; // addr to send bytes from (for PIO) 404 - struct iovec * tx_iovec; // remaining regions 405 - unsigned int tx_regions; // number of remaining regions 406 - 407 - spinlock_t mem_lock; 408 - wait_queue_head_t tx_queue; 409 - 410 - u8 irq; 411 - unsigned long flags; 412 - u8 tx_last; 413 - u8 tx_idle; 414 - 415 - rx_q_entry * rx_q_reset; 416 - rx_q_entry * rx_q_entry; 417 - rx_q_entry * rx_q_wrap; 418 - 419 - struct atm_dev * atm_dev; 420 - 421 - u32 last_vc; 422 - 423 - int noof_spare_buffers; 424 - u16 spare_buffers[SPARE_BUFFER_POOL_SIZE]; 425 - 426 - u16 tx_channel_record[TX_CHANS]; 427 - 428 - // this is what we follow when we get incoming data 429 - u32 txer[MAX_VCS/32]; 430 - struct atm_vcc * rxer[MAX_VCS]; 431 - 432 - // cell rate allocation 433 - spinlock_t rate_lock; 434 - unsigned int rx_avail; 435 - unsigned int tx_avail; 436 - 437 - // dev stats 438 - unsigned long tx_cell_count; 439 - unsigned long rx_cell_count; 440 - unsigned long hec_error_count; 441 - unsigned long unassigned_cell_count; 442 - 443 - struct pci_dev * pci_dev; 444 - struct timer_list housekeeping; 445 - }; 446 - 447 - typedef struct hrz_dev hrz_dev; 448 - 449 - /* macros for use later */ 450 - 451 - #define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0) 452 - 453 - #define INTERESTING_INTERRUPTS \ 454 - (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE) 455 - 456 - // 190 cells by default (192 TX buffers - 2 elbow room, see docs) 457 - #define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112 458 - 459 - // Have enough RX buffers (unless we allow other buffer splits) 460 - #define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU 461 - 462 - /* multi-statement macro protector */ 463 - #define DW(x) do{ x } while(0) 464 - 465 - #define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data) 466 - #define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data) 467 - 468 - /* Turn the LEDs on and off */ 469 - // The LEDs bits are upside down in that setting the bit in the debug 470 - // register will turn the appropriate LED off. 471 - 472 - #define YELLOW_LED DEBUG_BIT_0 473 - #define GREEN_LED DEBUG_BIT_1 474 - #define YELLOW_LED_OE DEBUG_BIT_0_OE 475 - #define GREEN_LED_OE DEBUG_BIT_1_OE 476 - 477 - #define GREEN_LED_OFF(dev) \ 478 - wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED) 479 - #define GREEN_LED_ON(dev) \ 480 - wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED) 481 - #define YELLOW_LED_OFF(dev) \ 482 - wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED) 483 - #define YELLOW_LED_ON(dev) \ 484 - wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED) 485 - 486 - typedef enum { 487 - round_up, 488 - round_down, 489 - round_nearest 490 - } rounding; 491 - 492 - #endif /* DRIVER_ATM_HORIZON_H */