Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3424/2: ixp23xx: fix uncompress.h for recent CRLF decompressor change
[ARM] 3434/1: pxa i2s amsl define
[ARM] 3425/1: xsc3: need to include pgtable-hwdef.h
[ARM] Allow un-muxed syscalls to be available for everyone
[ARM] 3420/1: Missing clobber in example code
[ARM] nommu: fixups for the exception vectors
[ARM] nommu: add nommu specific Kconfig and MMUEXT variable in Makefile
[ARM] nommu: start-up code
[ARM] nommu: MPU support in boot/compressed/head.S
+8
arch/arm/Kconfig
+8
arch/arm/Kconfig
···
77
77
config ARCH_MTD_XIP
78
78
bool
79
79
80
+
config VECTORS_BASE
81
+
hex
82
+
default 0xffff0000 if MMU
83
+
default DRAM_BASE if REMAP_VECTORS_TO_RAM
84
+
default 0x00000000
85
+
help
86
+
The base address of exception vectors.
87
+
80
88
source "init/Kconfig"
81
89
82
90
menu "System Type"
+44
arch/arm/Kconfig-nommu
+44
arch/arm/Kconfig-nommu
···
1
+
#
2
+
# Kconfig for uClinux(non-paged MM) depend configurations
3
+
# Hyok S. Choi <hyok.choi@samsung.com>
4
+
#
5
+
6
+
config SET_MEM_PARAM
7
+
bool "Set flash/sdram size and base addr"
8
+
help
9
+
Say Y to manually set the base addresses and sizes.
10
+
otherwise, the default values are assigned.
11
+
12
+
config DRAM_BASE
13
+
hex '(S)DRAM Base Address' if SET_MEM_PARAM
14
+
default 0x00800000
15
+
16
+
config DRAM_SIZE
17
+
hex '(S)DRAM SIZE' if SET_MEM_PARAM
18
+
default 0x00800000
19
+
20
+
config FLASH_MEM_BASE
21
+
hex 'FLASH Base Address' if SET_MEM_PARAM
22
+
default 0x00400000
23
+
24
+
config FLASH_SIZE
25
+
hex 'FLASH Size' if SET_MEM_PARAM
26
+
default 0x00400000
27
+
28
+
config REMAP_VECTORS_TO_RAM
29
+
bool 'Install vectors to the begining of RAM' if DRAM_BASE
30
+
depends on DRAM_BASE
31
+
help
32
+
The kernel needs to change the hardware exception vectors.
33
+
In nommu mode, the hardware exception vectors are normally
34
+
placed at address 0x00000000. However, this region may be
35
+
occupied by read-only memory depending on H/W design.
36
+
37
+
If the region contains read-write memory, say 'n' here.
38
+
39
+
If your CPU provides a remap facility which allows the exception
40
+
vectors to be mapped to writable memory, say 'n' here.
41
+
42
+
Otherwise, say 'y' here. In this case, the kernel will require
43
+
external support to redirect the hardware exception vectors to
44
+
the writable versions located at DRAM_BASE.
+7
-2
arch/arm/Makefile
+7
-2
arch/arm/Makefile
···
20
20
# Select a platform tht is kept up-to-date
21
21
KBUILD_DEFCONFIG := versatile_defconfig
22
22
23
+
# defines filename extension depending memory manement type.
24
+
ifeq ($(CONFIG_MMU),)
25
+
MMUEXT := -nommu
26
+
endif
27
+
23
28
ifeq ($(CONFIG_FRAME_POINTER),y)
24
29
CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
25
30
endif
···
78
73
CHECKFLAGS += -D__arm__
79
74
80
75
#Default value
81
-
head-y := arch/arm/kernel/head.o arch/arm/kernel/init_task.o
76
+
head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
82
77
textofs-y := 0x00008000
83
78
84
79
machine-$(CONFIG_ARCH_RPC) := rpc
···
138
133
MACHINE :=
139
134
endif
140
135
141
-
export TEXT_OFFSET GZFLAGS
136
+
export TEXT_OFFSET GZFLAGS MMUEXT
142
137
143
138
# Do we have FASTFPE?
144
139
FASTFPE :=arch/arm/fastfpe
+106
arch/arm/boot/compressed/head.S
+106
arch/arm/boot/compressed/head.S
···
2
2
* linux/arch/arm/boot/compressed/head.S
3
3
*
4
4
* Copyright (C) 1996-2002 Russell King
5
+
* Copyright (C) 2004 Hyok S. Choi (MPU support)
5
6
*
6
7
* This program is free software; you can redistribute it and/or modify
7
8
* it under the terms of the GNU General Public License version 2 as
···
321
320
cache_on: mov r3, #8 @ cache_on function
322
321
b call_cache_fn
323
322
323
+
/*
324
+
* Initialize the highest priority protection region, PR7
325
+
* to cover all 32bit address and cacheable and bufferable.
326
+
*/
327
+
__armv4_mpu_cache_on:
328
+
mov r0, #0x3f @ 4G, the whole
329
+
mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
330
+
mcr p15, 0, r0, c6, c7, 1
331
+
332
+
mov r0, #0x80 @ PR7
333
+
mcr p15, 0, r0, c2, c0, 0 @ D-cache on
334
+
mcr p15, 0, r0, c2, c0, 1 @ I-cache on
335
+
mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
336
+
337
+
mov r0, #0xc000
338
+
mcr p15, 0, r0, c5, c0, 1 @ I-access permission
339
+
mcr p15, 0, r0, c5, c0, 0 @ D-access permission
340
+
341
+
mov r0, #0
342
+
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
343
+
mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
344
+
mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
345
+
mrc p15, 0, r0, c1, c0, 0 @ read control reg
346
+
@ ...I .... ..D. WC.M
347
+
orr r0, r0, #0x002d @ .... .... ..1. 11.1
348
+
orr r0, r0, #0x1000 @ ...1 .... .... ....
349
+
350
+
mcr p15, 0, r0, c1, c0, 0 @ write control reg
351
+
352
+
mov r0, #0
353
+
mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
354
+
mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
355
+
mov pc, lr
356
+
357
+
__armv3_mpu_cache_on:
358
+
mov r0, #0x3f @ 4G, the whole
359
+
mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
360
+
361
+
mov r0, #0x80 @ PR7
362
+
mcr p15, 0, r0, c2, c0, 0 @ cache on
363
+
mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
364
+
365
+
mov r0, #0xc000
366
+
mcr p15, 0, r0, c5, c0, 0 @ access permission
367
+
368
+
mov r0, #0
369
+
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
370
+
mrc p15, 0, r0, c1, c0, 0 @ read control reg
371
+
@ .... .... .... WC.M
372
+
orr r0, r0, #0x000d @ .... .... .... 11.1
373
+
mov r0, #0
374
+
mcr p15, 0, r0, c1, c0, 0 @ write control reg
375
+
376
+
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
377
+
mov pc, lr
378
+
324
379
__setup_mmu: sub r3, r4, #16384 @ Page directory size
325
380
bic r3, r3, #0xff @ Align the pointer
326
381
bic r3, r3, #0x3f00
···
553
496
b __armv4_mmu_cache_off
554
497
mov pc, lr
555
498
499
+
.word 0x41007400 @ ARM74x
500
+
.word 0xff00ff00
501
+
b __armv3_mpu_cache_on
502
+
b __armv3_mpu_cache_off
503
+
b __armv3_mpu_cache_flush
504
+
505
+
.word 0x41009400 @ ARM94x
506
+
.word 0xff00ff00
507
+
b __armv4_mpu_cache_on
508
+
b __armv4_mpu_cache_off
509
+
b __armv4_mpu_cache_flush
510
+
556
511
.word 0x00007000 @ ARM7 IDs
557
512
.word 0x0000f000
558
513
mov pc, lr
···
631
562
cache_off: mov r3, #12 @ cache_off function
632
563
b call_cache_fn
633
564
565
+
__armv4_mpu_cache_off:
566
+
mrc p15, 0, r0, c1, c0
567
+
bic r0, r0, #0x000d
568
+
mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
569
+
mov r0, #0
570
+
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
571
+
mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
572
+
mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
573
+
mov pc, lr
574
+
575
+
__armv3_mpu_cache_off:
576
+
mrc p15, 0, r0, c1, c0
577
+
bic r0, r0, #0x000d
578
+
mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
579
+
mov r0, #0
580
+
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
581
+
mov pc, lr
582
+
634
583
__armv4_mmu_cache_off:
635
584
mrc p15, 0, r0, c1, c0
636
585
bic r0, r0, #0x000d
···
688
601
mov r3, #16
689
602
b call_cache_fn
690
603
604
+
__armv4_mpu_cache_flush:
605
+
mov r2, #1
606
+
mov r3, #0
607
+
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
608
+
mov r1, #7 << 5 @ 8 segments
609
+
1: orr r3, r1, #63 << 26 @ 64 entries
610
+
2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
611
+
subs r3, r3, #1 << 26
612
+
bcs 2b @ entries 63 to 0
613
+
subs r1, r1, #1 << 5
614
+
bcs 1b @ segments 7 to 0
615
+
616
+
teq r2, #0
617
+
mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
618
+
mcr p15, 0, ip, c7, c10, 4 @ drain WB
619
+
mov pc, lr
620
+
621
+
691
622
__armv6_mmu_cache_flush:
692
623
mov r1, #0
693
624
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
···
743
638
mov pc, lr
744
639
745
640
__armv3_mmu_cache_flush:
641
+
__armv3_mpu_cache_flush:
746
642
mov r1, #0
747
643
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
748
644
mov pc, lr
+1
-1
arch/arm/kernel/entry-armv.S
+1
-1
arch/arm/kernel/entry-armv.S
+217
arch/arm/kernel/head-common.S
+217
arch/arm/kernel/head-common.S
···
1
+
/*
2
+
* linux/arch/arm/kernel/head-common.S
3
+
*
4
+
* Copyright (C) 1994-2002 Russell King
5
+
* Copyright (c) 2003 ARM Limited
6
+
* All Rights Reserved
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*
12
+
*/
13
+
14
+
.type __switch_data, %object
15
+
__switch_data:
16
+
.long __mmap_switched
17
+
.long __data_loc @ r4
18
+
.long __data_start @ r5
19
+
.long __bss_start @ r6
20
+
.long _end @ r7
21
+
.long processor_id @ r4
22
+
.long __machine_arch_type @ r5
23
+
.long cr_alignment @ r6
24
+
.long init_thread_union + THREAD_START_SP @ sp
25
+
26
+
/*
27
+
* The following fragment of code is executed with the MMU on in MMU mode,
28
+
* and uses absolute addresses; this is not position independent.
29
+
*
30
+
* r0 = cp#15 control register
31
+
* r1 = machine ID
32
+
* r9 = processor ID
33
+
*/
34
+
.type __mmap_switched, %function
35
+
__mmap_switched:
36
+
adr r3, __switch_data + 4
37
+
38
+
ldmia r3!, {r4, r5, r6, r7}
39
+
cmp r4, r5 @ Copy data segment if needed
40
+
1: cmpne r5, r6
41
+
ldrne fp, [r4], #4
42
+
strne fp, [r5], #4
43
+
bne 1b
44
+
45
+
mov fp, #0 @ Clear BSS (and zero fp)
46
+
1: cmp r6, r7
47
+
strcc fp, [r6],#4
48
+
bcc 1b
49
+
50
+
ldmia r3, {r4, r5, r6, sp}
51
+
str r9, [r4] @ Save processor ID
52
+
str r1, [r5] @ Save machine type
53
+
bic r4, r0, #CR_A @ Clear 'A' bit
54
+
stmia r6, {r0, r4} @ Save control register values
55
+
b start_kernel
56
+
57
+
/*
58
+
* Exception handling. Something went wrong and we can't proceed. We
59
+
* ought to tell the user, but since we don't have any guarantee that
60
+
* we're even running on the right architecture, we do virtually nothing.
61
+
*
62
+
* If CONFIG_DEBUG_LL is set we try to print out something about the error
63
+
* and hope for the best (useful if bootloader fails to pass a proper
64
+
* machine ID for example).
65
+
*/
66
+
67
+
.type __error_p, %function
68
+
__error_p:
69
+
#ifdef CONFIG_DEBUG_LL
70
+
adr r0, str_p1
71
+
bl printascii
72
+
b __error
73
+
str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
74
+
.align
75
+
#endif
76
+
77
+
.type __error_a, %function
78
+
__error_a:
79
+
#ifdef CONFIG_DEBUG_LL
80
+
mov r4, r1 @ preserve machine ID
81
+
adr r0, str_a1
82
+
bl printascii
83
+
mov r0, r4
84
+
bl printhex8
85
+
adr r0, str_a2
86
+
bl printascii
87
+
adr r3, 3f
88
+
ldmia r3, {r4, r5, r6} @ get machine desc list
89
+
sub r4, r3, r4 @ get offset between virt&phys
90
+
add r5, r5, r4 @ convert virt addresses to
91
+
add r6, r6, r4 @ physical address space
92
+
1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type
93
+
bl printhex8
94
+
mov r0, #'\t'
95
+
bl printch
96
+
ldr r0, [r5, #MACHINFO_NAME] @ get machine name
97
+
add r0, r0, r4
98
+
bl printascii
99
+
mov r0, #'\n'
100
+
bl printch
101
+
add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
102
+
cmp r5, r6
103
+
blo 1b
104
+
adr r0, str_a3
105
+
bl printascii
106
+
b __error
107
+
str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x"
108
+
str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n"
109
+
str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n"
110
+
.align
111
+
#endif
112
+
113
+
.type __error, %function
114
+
__error:
115
+
#ifdef CONFIG_ARCH_RPC
116
+
/*
117
+
* Turn the screen red on a error - RiscPC only.
118
+
*/
119
+
mov r0, #0x02000000
120
+
mov r3, #0x11
121
+
orr r3, r3, r3, lsl #8
122
+
orr r3, r3, r3, lsl #16
123
+
str r3, [r0], #4
124
+
str r3, [r0], #4
125
+
str r3, [r0], #4
126
+
str r3, [r0], #4
127
+
#endif
128
+
1: mov r0, r0
129
+
b 1b
130
+
131
+
132
+
/*
133
+
* Read processor ID register (CP#15, CR0), and look up in the linker-built
134
+
* supported processor list. Note that we can't use the absolute addresses
135
+
* for the __proc_info lists since we aren't running with the MMU on
136
+
* (and therefore, we are not in the correct address space). We have to
137
+
* calculate the offset.
138
+
*
139
+
* r9 = cpuid
140
+
* Returns:
141
+
* r3, r4, r6 corrupted
142
+
* r5 = proc_info pointer in physical address space
143
+
* r9 = cpuid (preserved)
144
+
*/
145
+
.type __lookup_processor_type, %function
146
+
__lookup_processor_type:
147
+
adr r3, 3f
148
+
ldmda r3, {r5 - r7}
149
+
sub r3, r3, r7 @ get offset between virt&phys
150
+
add r5, r5, r3 @ convert virt addresses to
151
+
add r6, r6, r3 @ physical address space
152
+
1: ldmia r5, {r3, r4} @ value, mask
153
+
and r4, r4, r9 @ mask wanted bits
154
+
teq r3, r4
155
+
beq 2f
156
+
add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
157
+
cmp r5, r6
158
+
blo 1b
159
+
mov r5, #0 @ unknown processor
160
+
2: mov pc, lr
161
+
162
+
/*
163
+
* This provides a C-API version of the above function.
164
+
*/
165
+
ENTRY(lookup_processor_type)
166
+
stmfd sp!, {r4 - r7, r9, lr}
167
+
mov r9, r0
168
+
bl __lookup_processor_type
169
+
mov r0, r5
170
+
ldmfd sp!, {r4 - r7, r9, pc}
171
+
172
+
/*
173
+
* Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
174
+
* more information about the __proc_info and __arch_info structures.
175
+
*/
176
+
.long __proc_info_begin
177
+
.long __proc_info_end
178
+
3: .long .
179
+
.long __arch_info_begin
180
+
.long __arch_info_end
181
+
182
+
/*
183
+
* Lookup machine architecture in the linker-build list of architectures.
184
+
* Note that we can't use the absolute addresses for the __arch_info
185
+
* lists since we aren't running with the MMU on (and therefore, we are
186
+
* not in the correct address space). We have to calculate the offset.
187
+
*
188
+
* r1 = machine architecture number
189
+
* Returns:
190
+
* r3, r4, r6 corrupted
191
+
* r5 = mach_info pointer in physical address space
192
+
*/
193
+
.type __lookup_machine_type, %function
194
+
__lookup_machine_type:
195
+
adr r3, 3b
196
+
ldmia r3, {r4, r5, r6}
197
+
sub r3, r3, r4 @ get offset between virt&phys
198
+
add r5, r5, r3 @ convert virt addresses to
199
+
add r6, r6, r3 @ physical address space
200
+
1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type
201
+
teq r3, r1 @ matches loader number?
202
+
beq 2f @ found
203
+
add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
204
+
cmp r5, r6
205
+
blo 1b
206
+
mov r5, #0 @ unknown machine
207
+
2: mov pc, lr
208
+
209
+
/*
210
+
* This provides a C-API version of the above function.
211
+
*/
212
+
ENTRY(lookup_machine_type)
213
+
stmfd sp!, {r4 - r6, lr}
214
+
mov r1, r0
215
+
bl __lookup_machine_type
216
+
mov r0, r5
217
+
ldmfd sp!, {r4 - r6, pc}
+83
arch/arm/kernel/head-nommu.S
+83
arch/arm/kernel/head-nommu.S
···
1
+
/*
2
+
* linux/arch/arm/kernel/head-nommu.S
3
+
*
4
+
* Copyright (C) 1994-2002 Russell King
5
+
* Copyright (C) 2003-2006 Hyok S. Choi
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*
11
+
* Common kernel startup code (non-paged MM)
12
+
* for 32-bit CPUs which has a process ID register(CP15).
13
+
*
14
+
*/
15
+
#include <linux/config.h>
16
+
#include <linux/linkage.h>
17
+
#include <linux/init.h>
18
+
19
+
#include <asm/assembler.h>
20
+
#include <asm/mach-types.h>
21
+
#include <asm/procinfo.h>
22
+
#include <asm/ptrace.h>
23
+
#include <asm/constants.h>
24
+
#include <asm/system.h>
25
+
26
+
#define PROCINFO_INITFUNC 12
27
+
28
+
/*
29
+
* Kernel startup entry point.
30
+
* ---------------------------
31
+
*
32
+
* This is normally called from the decompressor code. The requirements
33
+
* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
34
+
* r1 = machine nr.
35
+
*
36
+
* See linux/arch/arm/tools/mach-types for the complete list of machine
37
+
* numbers for r1.
38
+
*
39
+
*/
40
+
__INIT
41
+
.type stext, %function
42
+
ENTRY(stext)
43
+
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
44
+
@ and irqs disabled
45
+
mrc p15, 0, r9, c0, c0 @ get processor id
46
+
bl __lookup_processor_type @ r5=procinfo r9=cpuid
47
+
movs r10, r5 @ invalid processor (r5=0)?
48
+
beq __error_p @ yes, error 'p'
49
+
bl __lookup_machine_type @ r5=machinfo
50
+
movs r8, r5 @ invalid machine (r5=0)?
51
+
beq __error_a @ yes, error 'a'
52
+
53
+
ldr r13, __switch_data @ address to jump to after
54
+
@ the initialization is done
55
+
adr lr, __after_proc_init @ return (PIC) address
56
+
add pc, r10, #PROCINFO_INITFUNC
57
+
58
+
/*
59
+
* Set the Control Register and Read the process ID.
60
+
*/
61
+
.type __after_proc_init, %function
62
+
__after_proc_init:
63
+
mrc p15, 0, r0, c1, c0, 0 @ read control reg
64
+
#ifdef CONFIG_ALIGNMENT_TRAP
65
+
orr r0, r0, #CR_A
66
+
#else
67
+
bic r0, r0, #CR_A
68
+
#endif
69
+
#ifdef CONFIG_CPU_DCACHE_DISABLE
70
+
bic r0, r0, #CR_C
71
+
#endif
72
+
#ifdef CONFIG_CPU_BPREDICT_DISABLE
73
+
bic r0, r0, #CR_Z
74
+
#endif
75
+
#ifdef CONFIG_CPU_ICACHE_DISABLE
76
+
bic r0, r0, #CR_I
77
+
#endif
78
+
mcr p15, 0, r0, c1, c0, 0 @ write control reg
79
+
80
+
mov pc, r13 @ clear the BSS and jump
81
+
@ to start_kernel
82
+
83
+
#include "head-common.S"
+1
-206
arch/arm/kernel/head.S
+1
-206
arch/arm/kernel/head.S
···
102
102
adr lr, __enable_mmu @ return (PIC) address
103
103
add pc, r10, #PROCINFO_INITFUNC
104
104
105
-
.type __switch_data, %object
106
-
__switch_data:
107
-
.long __mmap_switched
108
-
.long __data_loc @ r4
109
-
.long __data_start @ r5
110
-
.long __bss_start @ r6
111
-
.long _end @ r7
112
-
.long processor_id @ r4
113
-
.long __machine_arch_type @ r5
114
-
.long cr_alignment @ r6
115
-
.long init_thread_union + THREAD_START_SP @ sp
116
-
117
-
/*
118
-
* The following fragment of code is executed with the MMU on, and uses
119
-
* absolute addresses; this is not position independent.
120
-
*
121
-
* r0 = cp#15 control register
122
-
* r1 = machine ID
123
-
* r9 = processor ID
124
-
*/
125
-
.type __mmap_switched, %function
126
-
__mmap_switched:
127
-
adr r3, __switch_data + 4
128
-
129
-
ldmia r3!, {r4, r5, r6, r7}
130
-
cmp r4, r5 @ Copy data segment if needed
131
-
1: cmpne r5, r6
132
-
ldrne fp, [r4], #4
133
-
strne fp, [r5], #4
134
-
bne 1b
135
-
136
-
mov fp, #0 @ Clear BSS (and zero fp)
137
-
1: cmp r6, r7
138
-
strcc fp, [r6],#4
139
-
bcc 1b
140
-
141
-
ldmia r3, {r4, r5, r6, sp}
142
-
str r9, [r4] @ Save processor ID
143
-
str r1, [r5] @ Save machine type
144
-
bic r4, r0, #CR_A @ Clear 'A' bit
145
-
stmia r6, {r0, r4} @ Save control register values
146
-
b start_kernel
147
-
148
105
#if defined(CONFIG_SMP)
149
106
.type secondary_startup, #function
150
107
ENTRY(secondary_startup)
···
324
367
mov pc, lr
325
368
.ltorg
326
369
327
-
328
-
329
-
/*
330
-
* Exception handling. Something went wrong and we can't proceed. We
331
-
* ought to tell the user, but since we don't have any guarantee that
332
-
* we're even running on the right architecture, we do virtually nothing.
333
-
*
334
-
* If CONFIG_DEBUG_LL is set we try to print out something about the error
335
-
* and hope for the best (useful if bootloader fails to pass a proper
336
-
* machine ID for example).
337
-
*/
338
-
339
-
.type __error_p, %function
340
-
__error_p:
341
-
#ifdef CONFIG_DEBUG_LL
342
-
adr r0, str_p1
343
-
bl printascii
344
-
b __error
345
-
str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
346
-
.align
347
-
#endif
348
-
349
-
.type __error_a, %function
350
-
__error_a:
351
-
#ifdef CONFIG_DEBUG_LL
352
-
mov r4, r1 @ preserve machine ID
353
-
adr r0, str_a1
354
-
bl printascii
355
-
mov r0, r4
356
-
bl printhex8
357
-
adr r0, str_a2
358
-
bl printascii
359
-
adr r3, 3f
360
-
ldmia r3, {r4, r5, r6} @ get machine desc list
361
-
sub r4, r3, r4 @ get offset between virt&phys
362
-
add r5, r5, r4 @ convert virt addresses to
363
-
add r6, r6, r4 @ physical address space
364
-
1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type
365
-
bl printhex8
366
-
mov r0, #'\t'
367
-
bl printch
368
-
ldr r0, [r5, #MACHINFO_NAME] @ get machine name
369
-
add r0, r0, r4
370
-
bl printascii
371
-
mov r0, #'\n'
372
-
bl printch
373
-
add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
374
-
cmp r5, r6
375
-
blo 1b
376
-
adr r0, str_a3
377
-
bl printascii
378
-
b __error
379
-
str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x"
380
-
str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n"
381
-
str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n"
382
-
.align
383
-
#endif
384
-
385
-
.type __error, %function
386
-
__error:
387
-
#ifdef CONFIG_ARCH_RPC
388
-
/*
389
-
* Turn the screen red on a error - RiscPC only.
390
-
*/
391
-
mov r0, #0x02000000
392
-
mov r3, #0x11
393
-
orr r3, r3, r3, lsl #8
394
-
orr r3, r3, r3, lsl #16
395
-
str r3, [r0], #4
396
-
str r3, [r0], #4
397
-
str r3, [r0], #4
398
-
str r3, [r0], #4
399
-
#endif
400
-
1: mov r0, r0
401
-
b 1b
402
-
403
-
404
-
/*
405
-
* Read processor ID register (CP#15, CR0), and look up in the linker-built
406
-
* supported processor list. Note that we can't use the absolute addresses
407
-
* for the __proc_info lists since we aren't running with the MMU on
408
-
* (and therefore, we are not in the correct address space). We have to
409
-
* calculate the offset.
410
-
*
411
-
* r9 = cpuid
412
-
* Returns:
413
-
* r3, r4, r6 corrupted
414
-
* r5 = proc_info pointer in physical address space
415
-
* r9 = cpuid (preserved)
416
-
*/
417
-
.type __lookup_processor_type, %function
418
-
__lookup_processor_type:
419
-
adr r3, 3f
420
-
ldmda r3, {r5 - r7}
421
-
sub r3, r3, r7 @ get offset between virt&phys
422
-
add r5, r5, r3 @ convert virt addresses to
423
-
add r6, r6, r3 @ physical address space
424
-
1: ldmia r5, {r3, r4} @ value, mask
425
-
and r4, r4, r9 @ mask wanted bits
426
-
teq r3, r4
427
-
beq 2f
428
-
add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
429
-
cmp r5, r6
430
-
blo 1b
431
-
mov r5, #0 @ unknown processor
432
-
2: mov pc, lr
433
-
434
-
/*
435
-
* This provides a C-API version of the above function.
436
-
*/
437
-
ENTRY(lookup_processor_type)
438
-
stmfd sp!, {r4 - r7, r9, lr}
439
-
mov r9, r0
440
-
bl __lookup_processor_type
441
-
mov r0, r5
442
-
ldmfd sp!, {r4 - r7, r9, pc}
443
-
444
-
/*
445
-
* Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
446
-
* more information about the __proc_info and __arch_info structures.
447
-
*/
448
-
.long __proc_info_begin
449
-
.long __proc_info_end
450
-
3: .long .
451
-
.long __arch_info_begin
452
-
.long __arch_info_end
453
-
454
-
/*
455
-
* Lookup machine architecture in the linker-build list of architectures.
456
-
* Note that we can't use the absolute addresses for the __arch_info
457
-
* lists since we aren't running with the MMU on (and therefore, we are
458
-
* not in the correct address space). We have to calculate the offset.
459
-
*
460
-
* r1 = machine architecture number
461
-
* Returns:
462
-
* r3, r4, r6 corrupted
463
-
* r5 = mach_info pointer in physical address space
464
-
*/
465
-
.type __lookup_machine_type, %function
466
-
__lookup_machine_type:
467
-
adr r3, 3b
468
-
ldmia r3, {r4, r5, r6}
469
-
sub r3, r3, r4 @ get offset between virt&phys
470
-
add r5, r5, r3 @ convert virt addresses to
471
-
add r6, r6, r3 @ physical address space
472
-
1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type
473
-
teq r3, r1 @ matches loader number?
474
-
beq 2f @ found
475
-
add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
476
-
cmp r5, r6
477
-
blo 1b
478
-
mov r5, #0 @ unknown machine
479
-
2: mov pc, lr
480
-
481
-
/*
482
-
* This provides a C-API version of the above function.
483
-
*/
484
-
ENTRY(lookup_machine_type)
485
-
stmfd sp!, {r4 - r6, lr}
486
-
mov r1, r0
487
-
bl __lookup_machine_type
488
-
mov r0, r5
489
-
ldmfd sp!, {r4 - r6, pc}
370
+
#include "head-common.S"
+1
-1
arch/arm/kernel/signal.h
+1
-1
arch/arm/kernel/signal.h
···
7
7
* it under the terms of the GNU General Public License version 2 as
8
8
* published by the Free Software Foundation.
9
9
*/
10
-
#define KERN_SIGRETURN_CODE 0xffff0500
10
+
#define KERN_SIGRETURN_CODE (CONFIG_VECTORS_BASE + 0x00000500)
11
11
12
12
extern const unsigned long sigreturn_codes[7];
+5
-4
arch/arm/kernel/traps.c
+5
-4
arch/arm/kernel/traps.c
···
688
688
689
689
void __init trap_init(void)
690
690
{
691
+
unsigned long vectors = CONFIG_VECTORS_BASE;
691
692
extern char __stubs_start[], __stubs_end[];
692
693
extern char __vectors_start[], __vectors_end[];
693
694
extern char __kuser_helper_start[], __kuser_helper_end[];
···
699
698
* into the vector page, mapped at 0xffff0000, and ensure these
700
699
* are visible to the instruction stream.
701
700
*/
702
-
memcpy((void *)0xffff0000, __vectors_start, __vectors_end - __vectors_start);
703
-
memcpy((void *)0xffff0200, __stubs_start, __stubs_end - __stubs_start);
704
-
memcpy((void *)0xffff1000 - kuser_sz, __kuser_helper_start, kuser_sz);
701
+
memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
702
+
memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
703
+
memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
705
704
706
705
/*
707
706
* Copy signal return handlers into the vector page, and
···
710
709
memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
711
710
sizeof(sigreturn_codes));
712
711
713
-
flush_icache_range(0xffff0000, 0xffff0000 + PAGE_SIZE);
712
+
flush_icache_range(vectors, vectors + PAGE_SIZE);
714
713
modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
715
714
}
+1
arch/arm/mm/proc-xsc3.S
+1
arch/arm/mm/proc-xsc3.S
+3
-8
include/asm-arm/arch-ixp23xx/uncompress.h
+3
-8
include/asm-arm/arch-ixp23xx/uncompress.h
···
16
16
17
17
#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS)
18
18
19
-
static __inline__ void putc(char c)
19
+
static inline void putc(char c)
20
20
{
21
21
int j;
22
22
23
23
for (j = 0; j < 0x1000; j++) {
24
24
if (UART_BASE[UART_LSR] & UART_LSR_THRE)
25
25
break;
26
+
barrier();
26
27
}
27
28
28
29
UART_BASE[UART_TX] = c;
29
30
}
30
31
31
-
static void putstr(const char *s)
32
+
static inline void flush(void)
32
33
{
33
-
while (*s) {
34
-
putc(*s);
35
-
if (*s == '\n')
36
-
putc('\r');
37
-
s++;
38
-
}
39
34
}
40
35
41
36
#define arch_decomp_setup()
+1
-1
include/asm-arm/arch-pxa/pxa-regs.h
+1
-1
include/asm-arm/arch-pxa/pxa-regs.h
···
485
485
#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
486
486
#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
487
487
#define SACR1_DREC (1 << 3) /* Disable Recording Function */
488
-
#define SACR1_AMSL (1 << 1) /* Specify Alternate Mode */
488
+
#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
489
489
490
490
#define SASR0_I2SOFF (1 << 7) /* Controller Status */
491
491
#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
-11
include/asm-arm/unistd.h
-11
include/asm-arm/unistd.h
···
308
308
#define __NR_mq_notify (__NR_SYSCALL_BASE+278)
309
309
#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279)
310
310
#define __NR_waitid (__NR_SYSCALL_BASE+280)
311
-
312
-
#if defined(__ARM_EABI__) /* reserve these for un-muxing socketcall */
313
311
#define __NR_socket (__NR_SYSCALL_BASE+281)
314
312
#define __NR_bind (__NR_SYSCALL_BASE+282)
315
313
#define __NR_connect (__NR_SYSCALL_BASE+283)
···
325
327
#define __NR_getsockopt (__NR_SYSCALL_BASE+295)
326
328
#define __NR_sendmsg (__NR_SYSCALL_BASE+296)
327
329
#define __NR_recvmsg (__NR_SYSCALL_BASE+297)
328
-
#endif
329
-
330
-
#if defined(__ARM_EABI__) /* reserve these for un-muxing ipc */
331
330
#define __NR_semop (__NR_SYSCALL_BASE+298)
332
331
#define __NR_semget (__NR_SYSCALL_BASE+299)
333
332
#define __NR_semctl (__NR_SYSCALL_BASE+300)
···
336
341
#define __NR_shmdt (__NR_SYSCALL_BASE+306)
337
342
#define __NR_shmget (__NR_SYSCALL_BASE+307)
338
343
#define __NR_shmctl (__NR_SYSCALL_BASE+308)
339
-
#endif
340
-
341
344
#define __NR_add_key (__NR_SYSCALL_BASE+309)
342
345
#define __NR_request_key (__NR_SYSCALL_BASE+310)
343
346
#define __NR_keyctl (__NR_SYSCALL_BASE+311)
344
-
345
-
#if defined(__ARM_EABI__) /* reserved for un-muxing ipc */
346
347
#define __NR_semtimedop (__NR_SYSCALL_BASE+312)
347
-
#endif
348
-
349
348
#define __NR_vserver (__NR_SYSCALL_BASE+313)
350
349
#define __NR_ioprio_set (__NR_SYSCALL_BASE+314)
351
350
#define __NR_ioprio_get (__NR_SYSCALL_BASE+315)