tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

pinctrl: Spelling s/reseved/reserved/

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Geert Uytterhoeven and committed by
Linus Walleij 5b441eba b3da97ee

+20 -20
+1 -1
drivers/pinctrl/nomadik/pinctrl-ab8505.c
··· 286 286 ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */ 287 287 ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ 288 288 ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */ 289 - ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */ 289 + ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reserved */ 290 290 ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ 291 291 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ 292 292 ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */
+19 -19
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
··· 6125 6125 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 6126 6126 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 6127 6127 3, 2, 2, 2, 1, 2, 2, 2) { 6128 - /* RESEVED [1] */ 6128 + /* RESERVED [1] */ 6129 6129 0, 0, 6130 6130 /* SEL_SCIF1 [2] */ 6131 6131 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, ··· 6152 6152 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 6153 6153 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 6154 6154 0, 0, 0, 6155 - /* RESEVED [2] */ 6155 + /* RESERVED [2] */ 6156 6156 0, 0, 0, 0, 6157 6157 /* SEL_VI1 [2] */ 6158 6158 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, 6159 - /* RESEVED [2] */ 6159 + /* RESERVED [2] */ 6160 6160 0, 0, 0, 0, 6161 6161 /* SEL_TMU [1] */ 6162 6162 FN_SEL_TMU1_0, FN_SEL_TMU1_1, ··· 6174 6174 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 6175 6175 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 6176 6176 0, 0, 0, 6177 - /* RESEVED [1] */ 6177 + /* RESERVED [1] */ 6178 6178 0, 0, 6179 6179 /* SEL_SCIF [1] */ 6180 6180 FN_SEL_SCIF_0, FN_SEL_SCIF_1, ··· 6184 6184 0, 0, 6185 6185 /* SEL_CAN1 [2] */ 6186 6186 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 6187 - /* RESEVED [1] */ 6187 + /* RESERVED [1] */ 6188 6188 0, 0, 6189 6189 /* SEL_SCIFA2 [1] */ 6190 6190 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 6191 6191 /* SEL_SCIF4 [2] */ 6192 6192 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, 6193 - /* RESEVED [2] */ 6193 + /* RESERVED [2] */ 6194 6194 0, 0, 0, 0, 6195 6195 /* SEL_ADG [1] */ 6196 6196 FN_SEL_ADG_0, FN_SEL_ADG_1, ··· 6200 6200 0, 0, 0, 6201 6201 /* SEL_SCIFA5 [2] */ 6202 6202 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, 6203 - /* RESEVED [1] */ 6203 + /* RESERVED [1] */ 6204 6204 0, 0, 6205 6205 /* SEL_GPS [2] */ 6206 6206 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, ··· 6210 6210 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, 6211 6211 /* SEL_SIM [1] */ 6212 6212 FN_SEL_SIM_0, FN_SEL_SIM_1, 6213 - /* RESEVED [1] */ 6213 + /* RESERVED [1] */ 6214 6214 0, 0, 6215 6215 /* SEL_SSI8 [1] */ 6216 6216 FN_SEL_SSI8_0, FN_SEL_SSI8_1, } ··· 6240 6240 FN_SEL_MMC_0, FN_SEL_MMC_1, 6241 6241 /* SEL_SCIF5 [1] */ 6242 6242 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 6243 - /* RESEVED [2] */ 6243 + /* RESERVED [2] */ 6244 6244 0, 0, 0, 0, 6245 6245 /* SEL_IIC2 [2] */ 6246 6246 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, ··· 6250 6250 0, 0, 0, 6251 6251 /* SEL_IIC0 [2] */ 6252 6252 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, 6253 - /* RESEVED [2] */ 6253 + /* RESERVED [2] */ 6254 6254 0, 0, 0, 0, 6255 - /* RESEVED [2] */ 6255 + /* RESERVED [2] */ 6256 6256 0, 0, 0, 0, 6257 - /* RESEVED [1] */ 6257 + /* RESERVED [1] */ 6258 6258 0, 0, } 6259 6259 }, 6260 6260 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, ··· 6268 6268 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, 6269 6269 /* SEL_DIS [2] */ 6270 6270 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, 6271 - /* RESEVED [1] */ 6271 + /* RESERVED [1] */ 6272 6272 0, 0, 6273 6273 /* SEL_RAD [1] */ 6274 6274 FN_SEL_RAD_0, FN_SEL_RAD_1, ··· 6280 6280 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 6281 6281 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 6282 6282 0, 0, 0, 6283 - /* RESEVED [2] */ 6283 + /* RESERVED [2] */ 6284 6284 0, 0, 0, 0, 6285 - /* RESEVED [2] */ 6285 + /* RESERVED [2] */ 6286 6286 0, 0, 0, 0, 6287 6287 /* SEL_SOF2 [3] */ 6288 6288 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, 6289 6289 FN_SEL_SOF2_3, FN_SEL_SOF2_4, 6290 6290 0, 0, 0, 6291 - /* RESEVED [1] */ 6291 + /* RESERVED [1] */ 6292 6292 0, 0, 6293 6293 /* SEL_SSI1 [1] */ 6294 6294 FN_SEL_SSI1_0, FN_SEL_SSI1_1, ··· 6296 6296 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 6297 6297 /* SEL_SSP [2] */ 6298 6298 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, 6299 - /* RESEVED [2] */ 6299 + /* RESERVED [2] */ 6300 6300 0, 0, 0, 0, 6301 - /* RESEVED [2] */ 6301 + /* RESERVED [2] */ 6302 6302 0, 0, 0, 0, 6303 - /* RESEVED [2] */ 6303 + /* RESERVED [2] */ 6304 6304 0, 0, 0, 0, } 6305 6305 }, 6306 6306 { },