clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU

Document DT bindings of the IMEM CMU providing clocks for the Exynos5433
Security SubSystem (SSS) and SlimSSS IPs.

Acked-by: Chanwoo Choi <[e-mail]>
Reviewed-by: Rob Herring <[e-mail]>
Acked-by: Stephen Boyd <[e-mail]>
Signed-off-by: Kamil Konieczny <[e-mail]>
[[e-mail]: edited commit description]
Signed-off-by: Sylwester Nawrocki <[e-mail]>

Documentation/devicetree/bindings/clock/exynos5433-clock.txt

···
     IPs.
   - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
     which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
+  - "samsung,exynos5433-cmu-imem"   - clock controller compatible for CMU_IMEM
+    which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
 
 - reg: physical base address of the controller and length of memory mapped
   region.
···
 		- aclk_cam1_333
 		- aclk_cam1_400
 		- aclk_cam1_552
+
+	Input clocks for imem clock controller:
+		- oscclk
+		- aclk_imem_sssx_266
+		- aclk_imem_266
+		- aclk_imem_200
 
 Optional properties:
   - power-domains: a phandle to respective power domain node as described by
···
 		       <&cmu_top CLK_ACLK_CAM1_400>,
 		       <&cmu_top CLK_ACLK_CAM1_552>;
 		power-domains = <&pd_cam1>;
+	};
+
+	cmu_imem: clock-controller@11060000 {
+		compatible = "samsung,exynos5433-cmu-imem";
+		reg = <0x11060000 0x1000>;
+		#clock-cells = <1>;
+
+		clock-names = "oscclk",
+			"aclk_imem_sssx_266",
+			"aclk_imem_266",
+			"aclk_imem_200";
+		clocks = <&xxti>,
+			<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
+			<&cmu_top CLK_DIV_ACLK_IMEM_266>,
+			<&cmu_top CLK_DIV_ACLK_IMEM_200>;
 	};
 
 Example 3: UART controller node that consumes the clock generated by the clock