tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: tegra: dfll: Add CVB tables for Tegra114

Extend the Tegra124 DFLL driver to include configuration settings
required for Tegra114 compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
[treding@nvidia.com: Use TEGRA210 instead of T210]
Signed-off-by: Thierry Reding <treding@nvidia.com>

authored by

Svyatoslav Ryhel and committed by
Thierry Reding 5aba939e 8e7bd526

+132 -28
+1 -1
drivers/clk/tegra/Kconfig
··· 4 4 depends on TEGRA_BPMP 5 5 6 6 config TEGRA_CLK_DFLL 7 - depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC 7 + depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC 8 8 select PM_OPP 9 9 def_bool y 10 10
+131 -27
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
··· 29 29 }; 30 30 31 31 /* Maximum CPU frequency, indexed by CPU speedo id */ 32 + static const unsigned long tegra114_cpu_max_freq_table[] = { 33 + [0] = 2040000000UL, 34 + [1] = 1810500000UL, 35 + [2] = 1912500000UL, 36 + [3] = 1810500000UL, 37 + }; 38 + 39 + #define T114_CPU_CVB_TABLE \ 40 + .min_millivolts = 1000, \ 41 + .max_millivolts = 1320, \ 42 + .speedo_scale = 100, \ 43 + .voltage_scale = 1000, \ 44 + .entries = { \ 45 + { 306000000UL, { 2190643, -141851, 3576 } }, \ 46 + { 408000000UL, { 2250968, -144331, 3576 } }, \ 47 + { 510000000UL, { 2313333, -146811, 3576 } }, \ 48 + { 612000000UL, { 2377738, -149291, 3576 } }, \ 49 + { 714000000UL, { 2444183, -151771, 3576 } }, \ 50 + { 816000000UL, { 2512669, -154251, 3576 } }, \ 51 + { 918000000UL, { 2583194, -156731, 3576 } }, \ 52 + { 1020000000UL, { 2655759, -159211, 3576 } }, \ 53 + { 1122000000UL, { 2730365, -161691, 3576 } }, \ 54 + { 1224000000UL, { 2807010, -164171, 3576 } }, \ 55 + { 1326000000UL, { 2885696, -166651, 3576 } }, \ 56 + { 1428000000UL, { 2966422, -169131, 3576 } }, \ 57 + { 1530000000UL, { 3049183, -171601, 3576 } }, \ 58 + { 1606500000UL, { 3112179, -173451, 3576 } }, \ 59 + { 1708500000UL, { 3198504, -175931, 3576 } }, \ 60 + { 1810500000UL, { 3304747, -179126, 3576 } }, \ 61 + { 1912500000UL, { 3395401, -181606, 3576 } }, \ 62 + { 0UL, { 0, 0, 0 } }, \ 63 + }, \ 64 + .cpu_dfll_data = { \ 65 + .tune0_low = 0x00b0039d, \ 66 + .tune0_high = 0x00b0009d, \ 67 + .tune1 = 0x0000001f, \ 68 + .tune_high_min_millivolts = 1050, \ 69 + } 70 + 71 + static const struct cvb_table tegra114_cpu_cvb_tables[] = { 72 + { 73 + .speedo_id = 0, 74 + .process_id = -1, 75 + .min_millivolts = 1000, 76 + .max_millivolts = 1250, 77 + .speedo_scale = 100, 78 + .voltage_scale = 100, 79 + .entries = { 80 + { 306000000UL, { 107330, -1569, 0 } }, 81 + { 408000000UL, { 111250, -1666, 0 } }, 82 + { 510000000UL, { 110000, -1460, 0 } }, 83 + { 612000000UL, { 117290, -1745, 0 } }, 84 + { 714000000UL, { 122700, -1910, 0 } }, 85 + { 816000000UL, { 125620, -1945, 0 } }, 86 + { 918000000UL, { 130560, -2076, 0 } }, 87 + { 1020000000UL, { 137280, -2303, 0 } }, 88 + { 1122000000UL, { 146440, -2660, 0 } }, 89 + { 1224000000UL, { 152190, -2825, 0 } }, 90 + { 1326000000UL, { 157520, -2953, 0 } }, 91 + { 1428000000UL, { 166100, -3261, 0 } }, 92 + { 1530000000UL, { 176410, -3647, 0 } }, 93 + { 1632000000UL, { 189620, -4186, 0 } }, 94 + { 1734000000UL, { 203190, -4725, 0 } }, 95 + { 1836000000UL, { 222670, -5573, 0 } }, 96 + { 1938000000UL, { 256210, -7165, 0 } }, 97 + { 2040000000UL, { 250050, -6544, 0 } }, 98 + { 0UL, { 0, 0, 0 } }, 99 + }, 100 + .cpu_dfll_data = { 101 + .tune0_low = 0x00b0019d, 102 + .tune0_high = 0x00b0019d, 103 + .tune1 = 0x0000001f, 104 + .tune_high_min_millivolts = 1000, 105 + } 106 + }, 107 + { 108 + .speedo_id = 1, 109 + .process_id = -1, 110 + T114_CPU_CVB_TABLE 111 + }, 112 + { 113 + .speedo_id = 2, 114 + .process_id = -1, 115 + T114_CPU_CVB_TABLE 116 + }, 117 + { 118 + .speedo_id = 3, 119 + .process_id = -1, 120 + T114_CPU_CVB_TABLE 121 + }, 122 + }; 123 + 124 + /* Maximum CPU frequency, indexed by CPU speedo id */ 32 125 static const unsigned long tegra124_cpu_max_freq_table[] = { 33 126 [0] = 2014500000UL, 34 127 [1] = 2320500000UL, ··· 186 93 [10] = 1504500000UL, 187 94 }; 188 95 189 - #define CPU_CVB_TABLE \ 96 + #define TEGRA210_CPU_CVB_TABLE \ 190 97 .speedo_scale = 100, \ 191 98 .voltage_scale = 1000, \ 192 99 .entries = { \ ··· 213 120 { 0UL, { 0, 0, 0 } }, \ 214 121 } 215 122 216 - #define CPU_CVB_TABLE_XA \ 123 + #define TEGRA210_CPU_CVB_TABLE_XA \ 217 124 .speedo_scale = 100, \ 218 125 .voltage_scale = 1000, \ 219 126 .entries = { \ ··· 236 143 { 0UL, { 0, 0, 0 } }, \ 237 144 } 238 145 239 - #define CPU_CVB_TABLE_EUCM1 \ 146 + #define TEGRA210_CPU_CVB_TABLE_EUCM1 \ 240 147 .speedo_scale = 100, \ 241 148 .voltage_scale = 1000, \ 242 149 .entries = { \ ··· 259 166 { 0UL, { 0, 0, 0 } }, \ 260 167 } 261 168 262 - #define CPU_CVB_TABLE_EUCM2 \ 169 + #define TEGRA210_CPU_CVB_TABLE_EUCM2 \ 263 170 .speedo_scale = 100, \ 264 171 .voltage_scale = 1000, \ 265 172 .entries = { \ ··· 281 188 { 0UL, { 0, 0, 0 } }, \ 282 189 } 283 190 284 - #define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ 191 + #define TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ 285 192 .speedo_scale = 100, \ 286 193 .voltage_scale = 1000, \ 287 194 .entries = { \ ··· 302 209 { 0UL, { 0, 0, 0 } }, \ 303 210 } 304 211 305 - #define CPU_CVB_TABLE_ODN \ 212 + #define TEGRA210_CPU_CVB_TABLE_ODN \ 306 213 .speedo_scale = 100, \ 307 214 .voltage_scale = 1000, \ 308 215 .entries = { \ ··· 331 238 .process_id = 0, 332 239 .min_millivolts = 840, 333 240 .max_millivolts = 1120, 334 - CPU_CVB_TABLE_EUCM2_JOINT_RAIL, 241 + TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL, 335 242 .cpu_dfll_data = { 336 243 .tune0_low = 0xffead0ff, 337 244 .tune0_high = 0xffead0ff, ··· 344 251 .process_id = 1, 345 252 .min_millivolts = 840, 346 253 .max_millivolts = 1120, 347 - CPU_CVB_TABLE_EUCM2_JOINT_RAIL, 254 + TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL, 348 255 .cpu_dfll_data = { 349 256 .tune0_low = 0xffead0ff, 350 257 .tune0_high = 0xffead0ff, ··· 357 264 .process_id = 0, 358 265 .min_millivolts = 900, 359 266 .max_millivolts = 1162, 360 - CPU_CVB_TABLE_EUCM2, 267 + TEGRA210_CPU_CVB_TABLE_EUCM2, 361 268 .cpu_dfll_data = { 362 269 .tune0_low = 0xffead0ff, 363 270 .tune0_high = 0xffead0ff, ··· 369 276 .process_id = 1, 370 277 .min_millivolts = 900, 371 278 .max_millivolts = 1162, 372 - CPU_CVB_TABLE_EUCM2, 279 + TEGRA210_CPU_CVB_TABLE_EUCM2, 373 280 .cpu_dfll_data = { 374 281 .tune0_low = 0xffead0ff, 375 282 .tune0_high = 0xffead0ff, ··· 381 288 .process_id = 0, 382 289 .min_millivolts = 900, 383 290 .max_millivolts = 1195, 384 - CPU_CVB_TABLE_EUCM2, 291 + TEGRA210_CPU_CVB_TABLE_EUCM2, 385 292 .cpu_dfll_data = { 386 293 .tune0_low = 0xffead0ff, 387 294 .tune0_high = 0xffead0ff, ··· 393 300 .process_id = 1, 394 301 .min_millivolts = 900, 395 302 .max_millivolts = 1195, 396 - CPU_CVB_TABLE_EUCM2, 303 + TEGRA210_CPU_CVB_TABLE_EUCM2, 397 304 .cpu_dfll_data = { 398 305 .tune0_low = 0xffead0ff, 399 306 .tune0_high = 0xffead0ff, ··· 405 312 .process_id = 0, 406 313 .min_millivolts = 841, 407 314 .max_millivolts = 1227, 408 - CPU_CVB_TABLE_EUCM1, 315 + TEGRA210_CPU_CVB_TABLE_EUCM1, 409 316 .cpu_dfll_data = { 410 317 .tune0_low = 0xffead0ff, 411 318 .tune0_high = 0xffead0ff, ··· 418 325 .process_id = 1, 419 326 .min_millivolts = 841, 420 327 .max_millivolts = 1227, 421 - CPU_CVB_TABLE_EUCM1, 328 + TEGRA210_CPU_CVB_TABLE_EUCM1, 422 329 .cpu_dfll_data = { 423 330 .tune0_low = 0xffead0ff, 424 331 .tune0_high = 0xffead0ff, ··· 431 338 .process_id = 0, 432 339 .min_millivolts = 870, 433 340 .max_millivolts = 1150, 434 - CPU_CVB_TABLE, 341 + TEGRA210_CPU_CVB_TABLE, 435 342 .cpu_dfll_data = { 436 343 .tune0_low = 0xffead0ff, 437 344 .tune1 = 0x20091d9, ··· 442 349 .process_id = 1, 443 350 .min_millivolts = 870, 444 351 .max_millivolts = 1150, 445 - CPU_CVB_TABLE, 352 + TEGRA210_CPU_CVB_TABLE, 446 353 .cpu_dfll_data = { 447 354 .tune0_low = 0xffead0ff, 448 355 .tune1 = 0x25501d0, ··· 453 360 .process_id = 0, 454 361 .min_millivolts = 818, 455 362 .max_millivolts = 1227, 456 - CPU_CVB_TABLE, 363 + TEGRA210_CPU_CVB_TABLE, 457 364 .cpu_dfll_data = { 458 365 .tune0_low = 0xffead0ff, 459 366 .tune0_high = 0xffead0ff, ··· 466 373 .process_id = 1, 467 374 .min_millivolts = 818, 468 375 .max_millivolts = 1227, 469 - CPU_CVB_TABLE, 376 + TEGRA210_CPU_CVB_TABLE, 470 377 .cpu_dfll_data = { 471 378 .tune0_low = 0xffead0ff, 472 379 .tune0_high = 0xffead0ff, ··· 479 386 .process_id = -1, 480 387 .min_millivolts = 918, 481 388 .max_millivolts = 1113, 482 - CPU_CVB_TABLE_XA, 389 + TEGRA210_CPU_CVB_TABLE_XA, 483 390 .cpu_dfll_data = { 484 391 .tune0_low = 0xffead0ff, 485 392 .tune1 = 0x17711BD, ··· 490 397 .process_id = 0, 491 398 .min_millivolts = 825, 492 399 .max_millivolts = 1227, 493 - CPU_CVB_TABLE_ODN, 400 + TEGRA210_CPU_CVB_TABLE_ODN, 494 401 .cpu_dfll_data = { 495 402 .tune0_low = 0xffead0ff, 496 403 .tune0_high = 0xffead0ff, ··· 503 410 .process_id = 1, 504 411 .min_millivolts = 825, 505 412 .max_millivolts = 1227, 506 - CPU_CVB_TABLE_ODN, 413 + TEGRA210_CPU_CVB_TABLE_ODN, 507 414 .cpu_dfll_data = { 508 415 .tune0_low = 0xffead0ff, 509 416 .tune0_high = 0xffead0ff, ··· 516 423 .process_id = 0, 517 424 .min_millivolts = 870, 518 425 .max_millivolts = 1227, 519 - CPU_CVB_TABLE, 426 + TEGRA210_CPU_CVB_TABLE, 520 427 .cpu_dfll_data = { 521 428 .tune0_low = 0xffead0ff, 522 429 .tune1 = 0x20091d9, ··· 527 434 .process_id = 1, 528 435 .min_millivolts = 870, 529 436 .max_millivolts = 1227, 530 - CPU_CVB_TABLE, 437 + TEGRA210_CPU_CVB_TABLE, 531 438 .cpu_dfll_data = { 532 439 .tune0_low = 0xffead0ff, 533 440 .tune1 = 0x25501d0, ··· 538 445 .process_id = 0, 539 446 .min_millivolts = 837, 540 447 .max_millivolts = 1227, 541 - CPU_CVB_TABLE, 448 + TEGRA210_CPU_CVB_TABLE, 542 449 .cpu_dfll_data = { 543 450 .tune0_low = 0xffead0ff, 544 451 .tune0_high = 0xffead0ff, ··· 551 458 .process_id = 1, 552 459 .min_millivolts = 837, 553 460 .max_millivolts = 1227, 554 - CPU_CVB_TABLE, 461 + TEGRA210_CPU_CVB_TABLE, 555 462 .cpu_dfll_data = { 556 463 .tune0_low = 0xffead0ff, 557 464 .tune0_high = 0xffead0ff, ··· 564 471 .process_id = 0, 565 472 .min_millivolts = 850, 566 473 .max_millivolts = 1170, 567 - CPU_CVB_TABLE, 474 + TEGRA210_CPU_CVB_TABLE, 568 475 .cpu_dfll_data = { 569 476 .tune0_low = 0xffead0ff, 570 477 .tune0_high = 0xffead0ff, ··· 577 484 .process_id = 1, 578 485 .min_millivolts = 850, 579 486 .max_millivolts = 1170, 580 - CPU_CVB_TABLE, 487 + TEGRA210_CPU_CVB_TABLE, 581 488 .cpu_dfll_data = { 582 489 .tune0_low = 0xffead0ff, 583 490 .tune0_high = 0xffead0ff, ··· 585 492 .tune_high_min_millivolts = 864, 586 493 } 587 494 }, 495 + }; 496 + 497 + static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = { 498 + .cpu_max_freq_table = tegra114_cpu_max_freq_table, 499 + .cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table), 500 + .cpu_cvb_tables = tegra114_cpu_cvb_tables, 501 + .cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables) 588 502 }; 589 503 590 504 static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { ··· 609 509 }; 610 510 611 511 static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { 512 + { 513 + .compatible = "nvidia,tegra114-dfll", 514 + .data = &tegra114_dfll_fcpu_data, 515 + }, 612 516 { 613 517 .compatible = "nvidia,tegra124-dfll", 614 518 .data = &tegra124_dfll_fcpu_data,