Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

x86/apic: Drop struct local_apic

This type predates recorded history in tglx/history.git, making it older
than Feb 5th 2002.

This structure is literally old enough to drink in most juristictions in
the world, and has not been used once in that time.

Lay it to rest in /dev/null.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Steve Wahl <steve.wahl@hpe.com>
Link: https://lore.kernel.org/r/20231102-x86-apic-v1-3-bf049a2a0ed6@citrix.com

authored by

Andrew Cooper and committed by
Borislav Petkov (AMD)
5a7d6d26 855da7cd

-260
-260
arch/x86/include/asm/apicdef.h
··· 172 172 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 173 173 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 174 174 175 - #ifndef __ASSEMBLY__ 176 - /* 177 - * the local APIC register structure, memory mapped. Not terribly well 178 - * tested, but we might eventually use this one in the future - the 179 - * problem why we cannot use it right now is the P5 APIC, it has an 180 - * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 181 - */ 182 - #define u32 unsigned int 183 - 184 - struct local_apic { 185 - 186 - /*000*/ struct { u32 __reserved[4]; } __reserved_01; 187 - 188 - /*010*/ struct { u32 __reserved[4]; } __reserved_02; 189 - 190 - /*020*/ struct { /* APIC ID Register */ 191 - u32 __reserved_1 : 24, 192 - phys_apic_id : 4, 193 - __reserved_2 : 4; 194 - u32 __reserved[3]; 195 - } id; 196 - 197 - /*030*/ const 198 - struct { /* APIC Version Register */ 199 - u32 version : 8, 200 - __reserved_1 : 8, 201 - max_lvt : 8, 202 - __reserved_2 : 8; 203 - u32 __reserved[3]; 204 - } version; 205 - 206 - /*040*/ struct { u32 __reserved[4]; } __reserved_03; 207 - 208 - /*050*/ struct { u32 __reserved[4]; } __reserved_04; 209 - 210 - /*060*/ struct { u32 __reserved[4]; } __reserved_05; 211 - 212 - /*070*/ struct { u32 __reserved[4]; } __reserved_06; 213 - 214 - /*080*/ struct { /* Task Priority Register */ 215 - u32 priority : 8, 216 - __reserved_1 : 24; 217 - u32 __reserved_2[3]; 218 - } tpr; 219 - 220 - /*090*/ const 221 - struct { /* Arbitration Priority Register */ 222 - u32 priority : 8, 223 - __reserved_1 : 24; 224 - u32 __reserved_2[3]; 225 - } apr; 226 - 227 - /*0A0*/ const 228 - struct { /* Processor Priority Register */ 229 - u32 priority : 8, 230 - __reserved_1 : 24; 231 - u32 __reserved_2[3]; 232 - } ppr; 233 - 234 - /*0B0*/ struct { /* End Of Interrupt Register */ 235 - u32 eoi; 236 - u32 __reserved[3]; 237 - } eoi; 238 - 239 - /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 240 - 241 - /*0D0*/ struct { /* Logical Destination Register */ 242 - u32 __reserved_1 : 24, 243 - logical_dest : 8; 244 - u32 __reserved_2[3]; 245 - } ldr; 246 - 247 - /*0E0*/ struct { /* Destination Format Register */ 248 - u32 __reserved_1 : 28, 249 - model : 4; 250 - u32 __reserved_2[3]; 251 - } dfr; 252 - 253 - /*0F0*/ struct { /* Spurious Interrupt Vector Register */ 254 - u32 spurious_vector : 8, 255 - apic_enabled : 1, 256 - focus_cpu : 1, 257 - __reserved_2 : 22; 258 - u32 __reserved_3[3]; 259 - } svr; 260 - 261 - /*100*/ struct { /* In Service Register */ 262 - /*170*/ u32 bitfield; 263 - u32 __reserved[3]; 264 - } isr [8]; 265 - 266 - /*180*/ struct { /* Trigger Mode Register */ 267 - /*1F0*/ u32 bitfield; 268 - u32 __reserved[3]; 269 - } tmr [8]; 270 - 271 - /*200*/ struct { /* Interrupt Request Register */ 272 - /*270*/ u32 bitfield; 273 - u32 __reserved[3]; 274 - } irr [8]; 275 - 276 - /*280*/ union { /* Error Status Register */ 277 - struct { 278 - u32 send_cs_error : 1, 279 - receive_cs_error : 1, 280 - send_accept_error : 1, 281 - receive_accept_error : 1, 282 - __reserved_1 : 1, 283 - send_illegal_vector : 1, 284 - receive_illegal_vector : 1, 285 - illegal_register_address : 1, 286 - __reserved_2 : 24; 287 - u32 __reserved_3[3]; 288 - } error_bits; 289 - struct { 290 - u32 errors; 291 - u32 __reserved_3[3]; 292 - } all_errors; 293 - } esr; 294 - 295 - /*290*/ struct { u32 __reserved[4]; } __reserved_08; 296 - 297 - /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 298 - 299 - /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 300 - 301 - /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 302 - 303 - /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 304 - 305 - /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 306 - 307 - /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 308 - 309 - /*300*/ struct { /* Interrupt Command Register 1 */ 310 - u32 vector : 8, 311 - delivery_mode : 3, 312 - destination_mode : 1, 313 - delivery_status : 1, 314 - __reserved_1 : 1, 315 - level : 1, 316 - trigger : 1, 317 - __reserved_2 : 2, 318 - shorthand : 2, 319 - __reserved_3 : 12; 320 - u32 __reserved_4[3]; 321 - } icr1; 322 - 323 - /*310*/ struct { /* Interrupt Command Register 2 */ 324 - union { 325 - u32 __reserved_1 : 24, 326 - phys_dest : 4, 327 - __reserved_2 : 4; 328 - u32 __reserved_3 : 24, 329 - logical_dest : 8; 330 - } dest; 331 - u32 __reserved_4[3]; 332 - } icr2; 333 - 334 - /*320*/ struct { /* LVT - Timer */ 335 - u32 vector : 8, 336 - __reserved_1 : 4, 337 - delivery_status : 1, 338 - __reserved_2 : 3, 339 - mask : 1, 340 - timer_mode : 1, 341 - __reserved_3 : 14; 342 - u32 __reserved_4[3]; 343 - } lvt_timer; 344 - 345 - /*330*/ struct { /* LVT - Thermal Sensor */ 346 - u32 vector : 8, 347 - delivery_mode : 3, 348 - __reserved_1 : 1, 349 - delivery_status : 1, 350 - __reserved_2 : 3, 351 - mask : 1, 352 - __reserved_3 : 15; 353 - u32 __reserved_4[3]; 354 - } lvt_thermal; 355 - 356 - /*340*/ struct { /* LVT - Performance Counter */ 357 - u32 vector : 8, 358 - delivery_mode : 3, 359 - __reserved_1 : 1, 360 - delivery_status : 1, 361 - __reserved_2 : 3, 362 - mask : 1, 363 - __reserved_3 : 15; 364 - u32 __reserved_4[3]; 365 - } lvt_pc; 366 - 367 - /*350*/ struct { /* LVT - LINT0 */ 368 - u32 vector : 8, 369 - delivery_mode : 3, 370 - __reserved_1 : 1, 371 - delivery_status : 1, 372 - polarity : 1, 373 - remote_irr : 1, 374 - trigger : 1, 375 - mask : 1, 376 - __reserved_2 : 15; 377 - u32 __reserved_3[3]; 378 - } lvt_lint0; 379 - 380 - /*360*/ struct { /* LVT - LINT1 */ 381 - u32 vector : 8, 382 - delivery_mode : 3, 383 - __reserved_1 : 1, 384 - delivery_status : 1, 385 - polarity : 1, 386 - remote_irr : 1, 387 - trigger : 1, 388 - mask : 1, 389 - __reserved_2 : 15; 390 - u32 __reserved_3[3]; 391 - } lvt_lint1; 392 - 393 - /*370*/ struct { /* LVT - Error */ 394 - u32 vector : 8, 395 - __reserved_1 : 4, 396 - delivery_status : 1, 397 - __reserved_2 : 3, 398 - mask : 1, 399 - __reserved_3 : 15; 400 - u32 __reserved_4[3]; 401 - } lvt_error; 402 - 403 - /*380*/ struct { /* Timer Initial Count Register */ 404 - u32 initial_count; 405 - u32 __reserved_2[3]; 406 - } timer_icr; 407 - 408 - /*390*/ const 409 - struct { /* Timer Current Count Register */ 410 - u32 curr_count; 411 - u32 __reserved_2[3]; 412 - } timer_ccr; 413 - 414 - /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 415 - 416 - /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 417 - 418 - /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 419 - 420 - /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 421 - 422 - /*3E0*/ struct { /* Timer Divide Configuration Register */ 423 - u32 divisor : 4, 424 - __reserved_1 : 28; 425 - u32 __reserved_2[3]; 426 - } timer_dcr; 427 - 428 - /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 429 - 430 - } __attribute__ ((packed)); 431 - 432 - #undef u32 433 - 434 175 #ifdef CONFIG_X86_32 435 176 #define BAD_APICID 0xFFu 436 177 #else 437 178 #define BAD_APICID 0xFFFFu 438 179 #endif 439 180 440 - #endif /* !__ASSEMBLY__ */ 441 181 #endif /* _ASM_X86_APICDEF_H */