dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add definition for the clock controller of the CV1800 series SoC.

For CV181X, it has a clock that CV180X does not have. To avoid misuse,
also add a compatible string to identify CV181X series SoC.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://github.com/milkv-duo/duo-files/blob/main/hardware/CV1800B/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Inochi Amaoto and committed by

Stephen Boyd 2 years ago 5a72f071 b85ea95d

+222

2 changed files

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Documentation

devicetree

bindings

clock

sophgo,cv1800-clk.yaml

include

dt-bindings

clock

sophgo,cv1800.h

+46

Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/sophgo,cv1800-clk.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Sophgo CV1800 Series Clock Controller 8 + 9 + maintainers: 10 + - Inochi Amaoto <inochiama@outlook.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - sophgo,cv1800-clk 16 + - sophgo,cv1810-clk 17 + 18 + reg: 19 + maxItems: 1 20 + 21 + clocks: 22 + maxItems: 1 23 + 24 + "#clock-cells": 25 + const: 1 26 + description: 27 + See <dt-bindings/clock/sophgo,cv1800.h> for valid indices. 28 + 29 + required: 30 + - compatible 31 + - reg 32 + - clocks 33 + - "#clock-cells" 34 + 35 + additionalProperties: false 36 + 37 + examples: 38 + - | 39 + clock-controller@3002000 { 40 + compatible = "sophgo,cv1800-clk"; 41 + reg = <0x03002000 0x1000>; 42 + clocks = <&osc>; 43 + #clock-cells = <1>; 44 + }; 45 + 46 + ...

+176

include/dt-bindings/clock/sophgo,cv1800.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 + /* 3 + * Copyright (C) 2023 Sophgo Ltd. 4 + */ 5 + 6 + #ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ 7 + #define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ 8 + 9 + #define CLK_MPLL 0 10 + #define CLK_TPLL 1 11 + #define CLK_FPLL 2 12 + #define CLK_MIPIMPLL 3 13 + #define CLK_A0PLL 4 14 + #define CLK_DISPPLL 5 15 + #define CLK_CAM0PLL 6 16 + #define CLK_CAM1PLL 7 17 + 18 + #define CLK_MIPIMPLL_D3 8 19 + #define CLK_CAM0PLL_D2 9 20 + #define CLK_CAM0PLL_D3 10 21 + 22 + #define CLK_TPU 11 23 + #define CLK_TPU_FAB 12 24 + #define CLK_AHB_ROM 13 25 + #define CLK_DDR_AXI_REG 14 26 + #define CLK_RTC_25M 15 27 + #define CLK_SRC_RTC_SYS_0 16 28 + #define CLK_TEMPSEN 17 29 + #define CLK_SARADC 18 30 + #define CLK_EFUSE 19 31 + #define CLK_APB_EFUSE 20 32 + #define CLK_DEBUG 21 33 + #define CLK_AP_DEBUG 22 34 + #define CLK_XTAL_MISC 23 35 + #define CLK_AXI4_EMMC 24 36 + #define CLK_EMMC 25 37 + #define CLK_EMMC_100K 26 38 + #define CLK_AXI4_SD0 27 39 + #define CLK_SD0 28 40 + #define CLK_SD0_100K 29 41 + #define CLK_AXI4_SD1 30 42 + #define CLK_SD1 31 43 + #define CLK_SD1_100K 32 44 + #define CLK_SPI_NAND 33 45 + #define CLK_ETH0_500M 34 46 + #define CLK_AXI4_ETH0 35 47 + #define CLK_ETH1_500M 36 48 + #define CLK_AXI4_ETH1 37 49 + #define CLK_APB_GPIO 38 50 + #define CLK_APB_GPIO_INTR 39 51 + #define CLK_GPIO_DB 40 52 + #define CLK_AHB_SF 41 53 + #define CLK_AHB_SF1 42 54 + #define CLK_A24M 43 55 + #define CLK_AUDSRC 44 56 + #define CLK_APB_AUDSRC 45 57 + #define CLK_SDMA_AXI 46 58 + #define CLK_SDMA_AUD0 47 59 + #define CLK_SDMA_AUD1 48 60 + #define CLK_SDMA_AUD2 49 61 + #define CLK_SDMA_AUD3 50 62 + #define CLK_I2C 51 63 + #define CLK_APB_I2C 52 64 + #define CLK_APB_I2C0 53 65 + #define CLK_APB_I2C1 54 66 + #define CLK_APB_I2C2 55 67 + #define CLK_APB_I2C3 56 68 + #define CLK_APB_I2C4 57 69 + #define CLK_APB_WDT 58 70 + #define CLK_PWM_SRC 59 71 + #define CLK_PWM 60 72 + #define CLK_SPI 61 73 + #define CLK_APB_SPI0 62 74 + #define CLK_APB_SPI1 63 75 + #define CLK_APB_SPI2 64 76 + #define CLK_APB_SPI3 65 77 + #define CLK_1M 66 78 + #define CLK_CAM0_200 67 79 + #define CLK_PM 68 80 + #define CLK_TIMER0 69 81 + #define CLK_TIMER1 70 82 + #define CLK_TIMER2 71 83 + #define CLK_TIMER3 72 84 + #define CLK_TIMER4 73 85 + #define CLK_TIMER5 74 86 + #define CLK_TIMER6 75 87 + #define CLK_TIMER7 76 88 + #define CLK_UART0 77 89 + #define CLK_APB_UART0 78 90 + #define CLK_UART1 79 91 + #define CLK_APB_UART1 80 92 + #define CLK_UART2 81 93 + #define CLK_APB_UART2 82 94 + #define CLK_UART3 83 95 + #define CLK_APB_UART3 84 96 + #define CLK_UART4 85 97 + #define CLK_APB_UART4 86 98 + #define CLK_APB_I2S0 87 99 + #define CLK_APB_I2S1 88 100 + #define CLK_APB_I2S2 89 101 + #define CLK_APB_I2S3 90 102 + #define CLK_AXI4_USB 91 103 + #define CLK_APB_USB 92 104 + #define CLK_USB_125M 93 105 + #define CLK_USB_33K 94 106 + #define CLK_USB_12M 95 107 + #define CLK_AXI4 96 108 + #define CLK_AXI6 97 109 + #define CLK_DSI_ESC 98 110 + #define CLK_AXI_VIP 99 111 + #define CLK_SRC_VIP_SYS_0 100 112 + #define CLK_SRC_VIP_SYS_1 101 113 + #define CLK_SRC_VIP_SYS_2 102 114 + #define CLK_SRC_VIP_SYS_3 103 115 + #define CLK_SRC_VIP_SYS_4 104 116 + #define CLK_CSI_BE_VIP 105 117 + #define CLK_CSI_MAC0_VIP 106 118 + #define CLK_CSI_MAC1_VIP 107 119 + #define CLK_CSI_MAC2_VIP 108 120 + #define CLK_CSI0_RX_VIP 109 121 + #define CLK_CSI1_RX_VIP 110 122 + #define CLK_ISP_TOP_VIP 111 123 + #define CLK_IMG_D_VIP 112 124 + #define CLK_IMG_V_VIP 113 125 + #define CLK_SC_TOP_VIP 114 126 + #define CLK_SC_D_VIP 115 127 + #define CLK_SC_V1_VIP 116 128 + #define CLK_SC_V2_VIP 117 129 + #define CLK_SC_V3_VIP 118 130 + #define CLK_DWA_VIP 119 131 + #define CLK_BT_VIP 120 132 + #define CLK_DISP_VIP 121 133 + #define CLK_DSI_MAC_VIP 122 134 + #define CLK_LVDS0_VIP 123 135 + #define CLK_LVDS1_VIP 124 136 + #define CLK_PAD_VI_VIP 125 137 + #define CLK_PAD_VI1_VIP 126 138 + #define CLK_PAD_VI2_VIP 127 139 + #define CLK_CFG_REG_VIP 128 140 + #define CLK_VIP_IP0 129 141 + #define CLK_VIP_IP1 130 142 + #define CLK_VIP_IP2 131 143 + #define CLK_VIP_IP3 132 144 + #define CLK_IVE_VIP 133 145 + #define CLK_RAW_VIP 134 146 + #define CLK_OSDC_VIP 135 147 + #define CLK_CAM0_VIP 136 148 + #define CLK_AXI_VIDEO_CODEC 137 149 + #define CLK_VC_SRC0 138 150 + #define CLK_VC_SRC1 139 151 + #define CLK_VC_SRC2 140 152 + #define CLK_H264C 141 153 + #define CLK_APB_H264C 142 154 + #define CLK_H265C 143 155 + #define CLK_APB_H265C 144 156 + #define CLK_JPEG 145 157 + #define CLK_APB_JPEG 146 158 + #define CLK_CAM0 147 159 + #define CLK_CAM1 148 160 + #define CLK_WGN 149 161 + #define CLK_WGN0 150 162 + #define CLK_WGN1 151 163 + #define CLK_WGN2 152 164 + #define CLK_KEYSCAN 153 165 + #define CLK_CFG_REG_VC 154 166 + #define CLK_C906_0 155 167 + #define CLK_C906_1 156 168 + #define CLK_A53 157 169 + #define CLK_CPU_AXI0 158 170 + #define CLK_CPU_GIC 159 171 + #define CLK_XTAL_AP 160 172 + 173 + // Only for CV181x 174 + #define CLK_DISP_SRC_VIP 161 175 + 176 + #endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */