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drm/amdgpu/dce8: fix flash with white screen on monitor

Fixed mc stop and resume hardware programming sequence.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Junwei Zhang and committed by
Alex Deucher 5a3f25db 9ecbe7f5

+7 -60
+7 -60
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 526 526 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 527 527 CRTC_CONTROL, CRTC_MASTER_EN); 528 528 if (crtc_enabled) { 529 - #if 0 530 - u32 frame_count; 531 - int j; 532 - 529 + #if 1 533 530 save->crtc_enabled[i] = true; 534 531 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 535 532 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 536 - amdgpu_display_vblank_wait(adev, i); 537 - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 533 + /*it is correct only for RGB ; black is 0*/ 534 + WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 538 535 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 539 536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 540 - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 541 537 } 542 - /* wait for the next frame */ 543 - frame_count = amdgpu_display_vblank_get_counter(adev, i); 544 - for (j = 0; j < adev->usec_timeout; j++) { 545 - if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 546 - break; 547 - udelay(1); 548 - } 549 - tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 550 - if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 551 - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 552 - WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 553 - } 554 - tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 555 - if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 556 - tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 557 - WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 558 - } 538 + mdelay(20); 559 539 #else 560 540 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 561 541 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); ··· 555 575 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, 556 576 struct amdgpu_mode_mc_save *save) 557 577 { 558 - u32 tmp, frame_count; 559 - int i, j; 578 + u32 tmp; 579 + int i; 560 580 561 581 /* update crtc base addresses */ 562 582 for (i = 0; i < adev->mode_info.num_crtc; i++) { 563 583 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 564 584 upper_32_bits(adev->mc.vram_start)); 565 - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 566 - upper_32_bits(adev->mc.vram_start)); 567 585 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 568 - (u32)adev->mc.vram_start); 569 - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 570 586 (u32)adev->mc.vram_start); 571 587 572 588 if (save->crtc_enabled[i]) { 573 - tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 574 - if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 575 - tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 576 - WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 577 - } 578 - tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 579 - if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 580 - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 581 - WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 582 - } 583 - tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 584 - if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 585 - tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 586 - WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 587 - } 588 - for (j = 0; j < adev->usec_timeout; j++) { 589 - tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 590 - if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 591 - break; 592 - udelay(1); 593 - } 594 589 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 595 590 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 596 - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 597 591 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 598 - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 599 - /* wait for the next frame */ 600 - frame_count = amdgpu_display_vblank_get_counter(adev, i); 601 - for (j = 0; j < adev->usec_timeout; j++) { 602 - if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 603 - break; 604 - udelay(1); 605 - } 606 592 } 593 + mdelay(20); 607 594 } 608 595 609 596 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));