drm/amd/display: Add DP 2.0 BIOS and DMUB Support

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Parse DP2 encoder caps and hpo instance from bios

Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Fangzhi Zuo and committed by

Alex Deucher 4 years ago 5a2730fc d76b12da

+41 -1

7 changed files

expand all

drivers

gpu

drm

amd

display

bios

bios_parser2.c

command_table2.c

dcn30

dcn30_dio_link_encoder.c

inc

link_encoder.h

dmub

inc

dmub_cmd.h

include

bios_parser_types.h

include

atomfirmware.h

+10

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

··· 1604 1604 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1605 1605 info->HDMI_6GB_EN = (record->encodercaps & 1606 1606 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1607 + #if defined(CONFIG_DRM_AMD_DC_DCN) 1608 + info->IS_DP2_CAPABLE = (record->encodercaps & 1609 + ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 1610 + info->DP_UHBR10_EN = (record->encodercaps & 1611 + ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 1612 + info->DP_UHBR13_5_EN = (record->encodercaps & 1613 + ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 1614 + info->DP_UHBR20_EN = (record->encodercaps & 1615 + ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 1616 + #endif 1607 1617 info->DP_IS_USB_C = (record->encodercaps & 1608 1618 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1609 1619

+10

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

··· 340 340 const struct command_table_helper *cmd = bp->cmd_helper; 341 341 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7 = {0}; 342 342 343 + #if defined(CONFIG_DRM_AMD_DC_DCN) 344 + uint8_t hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_0; 345 + 346 + if (dc_is_dp_signal(cntl->signal)) 347 + hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_DP_0; 348 + #endif 349 + 343 350 dig_v1_7.phyid = cmd->phy_id_to_atom(cntl->transmitter); 344 351 dig_v1_7.action = (uint8_t)cntl->action; 345 352 ··· 360 353 dig_v1_7.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel); 361 354 dig_v1_7.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id); 362 355 dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id; 356 + #if defined(CONFIG_DRM_AMD_DC_DCN) 357 + dig_v1_7.HPO_instance = hpo_instance; 358 + #endif 363 359 dig_v1_7.symclk_units.symclk_10khz = cntl->pixel_clock/10; 364 360 365 361 if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c

··· 192 192 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 193 193 bp_cap_info.DP_HBR3_EN; 194 194 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 195 + enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE; 196 + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; 197 + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; 198 + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; 195 199 enc10->base.features.flags.bits.DP_IS_USB_C = 196 200 bp_cap_info.DP_IS_USB_C; 197 201 } else {

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

··· 59 59 uint32_t IS_TPS3_CAPABLE:1; 60 60 uint32_t IS_TPS4_CAPABLE:1; 61 61 uint32_t HDMI_6GB_EN:1; 62 + uint32_t IS_DP2_CAPABLE:1; 63 + uint32_t IS_UHBR10_CAPABLE:1; 64 + uint32_t IS_UHBR13_5_CAPABLE:1; 65 + uint32_t IS_UHBR20_CAPABLE:1; 62 66 uint32_t DP_IS_USB_C:1; 63 67 } bits; 64 68 uint32_t raw;

+1 -1

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

··· 974 974 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 975 975 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 976 976 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 977 - uint8_t reserved0; /**< For future use */ 977 + uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 978 978 uint8_t reserved1; /**< For future use */ 979 979 uint8_t reserved2[3]; /**< For future use */ 980 980 uint32_t reserved3[11]; /**< For future use */

drivers/gpu/drm/amd/display/include/bios_parser_types.h

··· 152 152 enum signal_type signal; 153 153 enum dc_color_depth color_depth; /* not used for DCE6.0 */ 154 154 enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */ 155 + #if defined(CONFIG_DRM_AMD_DC_DCN) 156 + enum tx_ffe_id txffe_sel; /* used for DCN3 */ 157 + enum engine_id hpo_engine_id; /* used for DCN3 */ 158 + #endif 155 159 struct graphics_object_id connector_obj_id; 156 160 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should 157 161 * be pixel clock * deep_color_ratio (in KHz) ··· 323 319 uint32_t DP_HBR2_EN:1; 324 320 uint32_t DP_HBR3_EN:1; 325 321 uint32_t HDMI_6GB_EN:1; 322 + uint32_t IS_DP2_CAPABLE:1; 323 + uint32_t DP_UHBR10_EN:1; 324 + uint32_t DP_UHBR13_5_EN:1; 325 + uint32_t DP_UHBR20_EN:1; 326 326 uint32_t DP_IS_USB_C:1; 327 327 uint32_t RESERVED:27; 328 328 };

drivers/gpu/drm/amd/include/atomfirmware.h

··· 768 768 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 769 769 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 770 770 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 771 + ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. 772 + ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board 773 + ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board 774 + ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board 771 775 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 772 776 }; 773 777