tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: PowerTV: Streamline access to platform device registers
Pre-compute addresses for the basic ASIC registers. This speeds up access
and allows memory for unused configurations to be freed. In addition,
uninitialized register addresses will be returned as NULL to catch bad
usage quickly.
Signed-off-by: David VomLehn <dvomlehn@cisco.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/806/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
David VomLehn
and committed by
Ralf Baechle
59dfa2fc
9c4a6fce
+362
-304
+90
arch/mips/include/asm/mach-powertv/asic_reg_map.h
+90
arch/mips/include/asm/mach-powertv/asic_reg_map.h
···
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/*
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* asic_reg_map.h
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*
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* A macro-enclosed list of the elements for the register_map structure for
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* use in defining and manipulating the structure.
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*
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* Copyright (C) 2009 Cisco Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
20
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22
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*/
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+
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REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
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REGISTER_MAP_ELEMENT(eic_cfg_bits)
26
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REGISTER_MAP_ELEMENT(eic_ready_status)
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REGISTER_MAP_ELEMENT(chipver3)
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REGISTER_MAP_ELEMENT(chipver2)
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REGISTER_MAP_ELEMENT(chipver1)
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REGISTER_MAP_ELEMENT(chipver0)
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REGISTER_MAP_ELEMENT(uart1_intstat)
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REGISTER_MAP_ELEMENT(uart1_inten)
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REGISTER_MAP_ELEMENT(uart1_config1)
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REGISTER_MAP_ELEMENT(uart1_config2)
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REGISTER_MAP_ELEMENT(uart1_divisorhi)
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REGISTER_MAP_ELEMENT(uart1_divisorlo)
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REGISTER_MAP_ELEMENT(uart1_data)
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+
REGISTER_MAP_ELEMENT(uart1_status)
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REGISTER_MAP_ELEMENT(int_stat_3)
40
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REGISTER_MAP_ELEMENT(int_stat_2)
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REGISTER_MAP_ELEMENT(int_stat_1)
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REGISTER_MAP_ELEMENT(int_stat_0)
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REGISTER_MAP_ELEMENT(int_config)
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REGISTER_MAP_ELEMENT(int_int_scan)
45
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REGISTER_MAP_ELEMENT(ien_int_3)
46
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REGISTER_MAP_ELEMENT(ien_int_2)
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REGISTER_MAP_ELEMENT(ien_int_1)
48
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REGISTER_MAP_ELEMENT(ien_int_0)
49
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REGISTER_MAP_ELEMENT(int_level_3_3)
50
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REGISTER_MAP_ELEMENT(int_level_3_2)
51
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REGISTER_MAP_ELEMENT(int_level_3_1)
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REGISTER_MAP_ELEMENT(int_level_3_0)
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REGISTER_MAP_ELEMENT(int_level_2_3)
54
+
REGISTER_MAP_ELEMENT(int_level_2_2)
55
+
REGISTER_MAP_ELEMENT(int_level_2_1)
56
+
REGISTER_MAP_ELEMENT(int_level_2_0)
57
+
REGISTER_MAP_ELEMENT(int_level_1_3)
58
+
REGISTER_MAP_ELEMENT(int_level_1_2)
59
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REGISTER_MAP_ELEMENT(int_level_1_1)
60
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REGISTER_MAP_ELEMENT(int_level_1_0)
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REGISTER_MAP_ELEMENT(int_level_0_3)
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REGISTER_MAP_ELEMENT(int_level_0_2)
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REGISTER_MAP_ELEMENT(int_level_0_1)
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+
REGISTER_MAP_ELEMENT(int_level_0_0)
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REGISTER_MAP_ELEMENT(int_docsis_en)
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REGISTER_MAP_ELEMENT(mips_pll_setup)
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REGISTER_MAP_ELEMENT(usb_fs)
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REGISTER_MAP_ELEMENT(test_bus)
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REGISTER_MAP_ELEMENT(crt_spare)
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REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71
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REGISTER_MAP_ELEMENT(usb2_strap)
72
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REGISTER_MAP_ELEMENT(ehci_hcapbase)
73
+
REGISTER_MAP_ELEMENT(ohci_hc_revision)
74
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REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75
+
REGISTER_MAP_ELEMENT(usb2_control)
76
+
REGISTER_MAP_ELEMENT(usb2_stbus_obc)
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REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78
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REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79
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REGISTER_MAP_ELEMENT(pcie_regs)
80
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REGISTER_MAP_ELEMENT(tim_ch)
81
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REGISTER_MAP_ELEMENT(tim_cl)
82
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REGISTER_MAP_ELEMENT(gpio_dout)
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REGISTER_MAP_ELEMENT(gpio_din)
84
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REGISTER_MAP_ELEMENT(gpio_dir)
85
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REGISTER_MAP_ELEMENT(watchdog)
86
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REGISTER_MAP_ELEMENT(front_panel)
87
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REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88
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REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89
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REGISTER_MAP_ELEMENT(crt_ext_ctl)
90
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REGISTER_MAP_ELEMENT(register_maps)
+52
-85
arch/mips/include/asm/mach-powertv/asic_regs.h
+52
-85
arch/mips/include/asm/mach-powertv/asic_regs.h
···
35
35
#define CRONUS_11 0x0B4C1C21
36
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#define CRONUSLITE_10 0x0B4C1C40
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38
-
#define NAND_FLASH_BASE 0x03000000
39
-
#define ZEUS_IO_BASE 0x09000000
38
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#define NAND_FLASH_BASE 0x03000000
40
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#define CALLIOPE_IO_BASE 0x08000000
41
-
#define CRONUS_IO_BASE 0x09000000
42
-
#define ASIC_IO_SIZE 0x01000000
40
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#define CRONUS_IO_BASE 0x09000000
41
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#define ZEUS_IO_BASE 0x09000000
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+
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#define ASIC_IO_SIZE 0x01000000
43
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/* Definitions for backward compatibility */
45
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#define UART1_INTSTAT uart1_intstat
···
53
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#define UART1_STATUS uart1_status
54
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/* ASIC register enumeration */
56
-
struct register_map {
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u32 eic_slow0_strt_add;
58
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u32 eic_cfg_bits;
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u32 eic_ready_status;
60
-
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u32 chipver3;
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u32 chipver2;
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u32 chipver1;
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u32 chipver0;
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-
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u32 uart1_intstat;
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u32 uart1_inten;
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u32 uart1_config1;
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u32 uart1_config2;
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u32 uart1_divisorhi;
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u32 uart1_divisorlo;
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u32 uart1_data;
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u32 uart1_status;
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-
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u32 int_stat_3;
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u32 int_stat_2;
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u32 int_stat_1;
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u32 int_stat_0;
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u32 int_config;
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u32 int_int_scan;
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u32 ien_int_3;
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u32 ien_int_2;
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u32 ien_int_1;
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u32 ien_int_0;
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u32 int_level_3_3;
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u32 int_level_3_2;
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u32 int_level_3_1;
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u32 int_level_3_0;
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u32 int_level_2_3;
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u32 int_level_2_2;
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u32 int_level_2_1;
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u32 int_level_2_0;
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u32 int_level_1_3;
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u32 int_level_1_2;
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u32 int_level_1_1;
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u32 int_level_1_0;
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u32 int_level_0_3;
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u32 int_level_0_2;
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u32 int_level_0_1;
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u32 int_level_0_0;
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u32 int_docsis_en;
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-
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u32 mips_pll_setup;
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u32 usb_fs;
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u32 test_bus;
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u32 crt_spare;
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u32 usb2_ohci_int_mask;
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u32 usb2_strap;
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u32 ehci_hcapbase;
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u32 ohci_hc_revision;
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u32 bcm1_bs_lmi_steer;
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u32 usb2_control;
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u32 usb2_stbus_obc;
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u32 usb2_stbus_mess_size;
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u32 usb2_stbus_chunk_size;
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u32 pcie_regs;
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u32 tim_ch;
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u32 tim_cl;
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u32 gpio_dout;
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u32 gpio_din;
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u32 gpio_dir;
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u32 watchdog;
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u32 front_panel;
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-
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u32 register_maps;
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union register_map_entry {
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unsigned long phys;
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u32 *virt;
127
58
};
128
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extern enum asic_type asic;
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extern const struct register_map *register_map;
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extern unsigned long asic_phy_base; /* Physical address of ASIC */
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extern unsigned long asic_base; /* Virtual address of ASIC */
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#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
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struct register_map {
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#include <asm/mach-powertv/asic_reg_map.h>
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};
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#undef REGISTER_MAP_ELEMENT
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/**
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* register_map_offset_phys - add an offset to the physical address
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* @map: Pointer to the &struct register_map
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* @offset: Value to add
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*
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* Only adds the base to non-zero physical addresses
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*/
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static inline void register_map_offset_phys(struct register_map *map,
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unsigned long offset)
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{
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#define REGISTER_MAP_ELEMENT(x) do { \
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if (map->x.phys != 0) \
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map->x.phys += offset; \
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} while (false);
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#include <asm/mach-powertv/asic_reg_map.h>
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#undef REGISTER_MAP_ELEMENT
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}
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85
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/**
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* register_map_virtualize - Convert ®ister_map to virtual addresses
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* @map: Pointer to ®ister_map to virtualize
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*/
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static inline void register_map_virtualize(struct register_map *map)
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{
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#define REGISTER_MAP_ELEMENT(x) do { \
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map->x.virt = (!map->x.phys) ? NULL : \
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UNCAC_ADDR(phys_to_virt(map->x.phys)); \
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} while (false);
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#include <asm/mach-powertv/asic_reg_map.h>
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#undef REGISTER_MAP_ELEMENT
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}
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100
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extern struct register_map _asic_register_map;
133
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134
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/*
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* Macros to interface to registers through their ioremapped address
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* asic_reg_offset Returns the offset of a given register from the start
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* of the ASIC address space
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* asic_reg_phys_addr Returns the physical address of the given register
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* asic_reg_addr Returns the iomapped virtual address of the given
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* register.
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*/
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#define asic_reg_offset(x) (register_map->x)
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#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
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#define asic_reg_addr(x) \
145
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((unsigned int *) (asic_base + asic_reg_offset(x)))
108
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#define asic_reg_addr(x) (_asic_register_map.x.virt)
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#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
110
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(unsigned long) asic_reg_addr(x))))
146
111
147
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/*
148
113
* The asic_reg macro is gone. It should be replaced by either asic_read or
+67
-64
arch/mips/powertv/asic/asic-calliope.c
+67
-64
arch/mips/powertv/asic/asic-calliope.c
···
23
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* Description: Defines the platform resources for the SA settop.
24
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*/
25
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#include <linux/init.h>
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#include <asm/mach-powertv/asic.h>
27
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const struct register_map calliope_register_map = {
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.eic_slow0_strt_add = 0x800000,
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.eic_cfg_bits = 0x800038,
31
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.eic_ready_status = 0x80004c,
29
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#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
32
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.chipver3 = 0xA00800,
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.chipver2 = 0xA00804,
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.chipver1 = 0xA00808,
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.chipver0 = 0xA0080c,
31
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const struct register_map calliope_register_map __initdata = {
32
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.eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
33
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.eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
34
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.eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
35
+
36
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.chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
37
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.chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
38
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.chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
39
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.chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
37
40
38
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/* The registers of IRBlaster */
39
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.uart1_intstat = 0xA01800,
40
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.uart1_inten = 0xA01804,
41
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.uart1_config1 = 0xA01808,
42
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.uart1_config2 = 0xA0180C,
43
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.uart1_divisorhi = 0xA01810,
44
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.uart1_divisorlo = 0xA01814,
45
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.uart1_data = 0xA01818,
46
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.uart1_status = 0xA0181C,
42
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.uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
43
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.uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
44
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.uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
45
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.uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
46
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.uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
47
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.uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
48
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.uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
49
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.uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
47
50
48
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.int_stat_3 = 0xA02800,
49
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.int_stat_2 = 0xA02804,
50
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.int_stat_1 = 0xA02808,
51
-
.int_stat_0 = 0xA0280c,
52
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.int_config = 0xA02810,
53
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.int_int_scan = 0xA02818,
54
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.ien_int_3 = 0xA02830,
55
-
.ien_int_2 = 0xA02834,
56
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.ien_int_1 = 0xA02838,
57
-
.ien_int_0 = 0xA0283c,
58
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.int_level_3_3 = 0xA02880,
59
-
.int_level_3_2 = 0xA02884,
60
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.int_level_3_1 = 0xA02888,
61
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.int_level_3_0 = 0xA0288c,
62
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.int_level_2_3 = 0xA02890,
63
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.int_level_2_2 = 0xA02894,
64
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.int_level_2_1 = 0xA02898,
65
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.int_level_2_0 = 0xA0289c,
66
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.int_level_1_3 = 0xA028a0,
67
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.int_level_1_2 = 0xA028a4,
68
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.int_level_1_1 = 0xA028a8,
69
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.int_level_1_0 = 0xA028ac,
70
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.int_level_0_3 = 0xA028b0,
71
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.int_level_0_2 = 0xA028b4,
72
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.int_level_0_1 = 0xA028b8,
73
-
.int_level_0_0 = 0xA028bc,
74
-
.int_docsis_en = 0xA028F4,
51
+
.int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
52
+
.int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
53
+
.int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
54
+
.int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
55
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.int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
56
+
.int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
57
+
.ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
58
+
.ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
59
+
.ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
60
+
.ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
61
+
.int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
62
+
.int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
63
+
.int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
64
+
.int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
65
+
.int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
66
+
.int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
67
+
.int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
68
+
.int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
69
+
.int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
70
+
.int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
71
+
.int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
72
+
.int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
73
+
.int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
74
+
.int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
75
+
.int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
76
+
.int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
77
+
.int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
75
78
76
-
.mips_pll_setup = 0x980000,
77
-
.usb_fs = 0x980030, /* -default 72800028- */
78
-
.test_bus = 0x9800CC,
79
-
.crt_spare = 0x9800d4,
80
-
.usb2_ohci_int_mask = 0x9A000c,
81
-
.usb2_strap = 0x9A0014,
82
-
.ehci_hcapbase = 0x9BFE00,
83
-
.ohci_hc_revision = 0x9BFC00,
84
-
.bcm1_bs_lmi_steer = 0x9E0004,
85
-
.usb2_control = 0x9E0054,
86
-
.usb2_stbus_obc = 0x9BFF00,
87
-
.usb2_stbus_mess_size = 0x9BFF04,
88
-
.usb2_stbus_chunk_size = 0x9BFF08,
79
+
.mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80
+
.usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
81
+
.test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82
+
.crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83
+
.usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
84
+
.usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
85
+
.ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
86
+
.ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
87
+
.bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
88
+
.usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
89
+
.usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
90
+
.usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
91
+
.usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
89
92
90
-
.pcie_regs = 0x000000, /* -doesn't exist- */
91
-
.tim_ch = 0xA02C10,
92
-
.tim_cl = 0xA02C14,
93
-
.gpio_dout = 0xA02c20,
94
-
.gpio_din = 0xA02c24,
95
-
.gpio_dir = 0xA02c2C,
96
-
.watchdog = 0xA02c30,
97
-
.front_panel = 0x000000, /* -not used- */
93
+
.pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
94
+
.tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
95
+
.tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
96
+
.gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
97
+
.gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
98
+
.gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
99
+
.watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
100
+
.front_panel = {.phys = 0x000000}, /* -not used- */
98
101
};
+67
-64
arch/mips/powertv/asic/asic-cronus.c
+67
-64
arch/mips/powertv/asic/asic-cronus.c
···
23
23
* Description: Defines the platform resources for the SA settop.
24
24
*/
25
25
26
+
#include <linux/init.h>
26
27
#include <asm/mach-powertv/asic.h>
27
28
28
-
const struct register_map cronus_register_map = {
29
-
.eic_slow0_strt_add = 0x000000,
30
-
.eic_cfg_bits = 0x000038,
31
-
.eic_ready_status = 0x00004C,
29
+
#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
32
30
33
-
.chipver3 = 0x2A0800,
34
-
.chipver2 = 0x2A0804,
35
-
.chipver1 = 0x2A0808,
36
-
.chipver0 = 0x2A080C,
31
+
const struct register_map cronus_register_map __initdata = {
32
+
.eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
33
+
.eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
34
+
.eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
35
+
36
+
.chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
37
+
.chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
38
+
.chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
39
+
.chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
37
40
38
41
/* The registers of IRBlaster */
39
-
.uart1_intstat = 0x2A1800,
40
-
.uart1_inten = 0x2A1804,
41
-
.uart1_config1 = 0x2A1808,
42
-
.uart1_config2 = 0x2A180C,
43
-
.uart1_divisorhi = 0x2A1810,
44
-
.uart1_divisorlo = 0x2A1814,
45
-
.uart1_data = 0x2A1818,
46
-
.uart1_status = 0x2A181C,
42
+
.uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
43
+
.uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
44
+
.uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
45
+
.uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
46
+
.uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
47
+
.uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
48
+
.uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
49
+
.uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
47
50
48
-
.int_stat_3 = 0x2A2800,
49
-
.int_stat_2 = 0x2A2804,
50
-
.int_stat_1 = 0x2A2808,
51
-
.int_stat_0 = 0x2A280C,
52
-
.int_config = 0x2A2810,
53
-
.int_int_scan = 0x2A2818,
54
-
.ien_int_3 = 0x2A2830,
55
-
.ien_int_2 = 0x2A2834,
56
-
.ien_int_1 = 0x2A2838,
57
-
.ien_int_0 = 0x2A283C,
58
-
.int_level_3_3 = 0x2A2880,
59
-
.int_level_3_2 = 0x2A2884,
60
-
.int_level_3_1 = 0x2A2888,
61
-
.int_level_3_0 = 0x2A288C,
62
-
.int_level_2_3 = 0x2A2890,
63
-
.int_level_2_2 = 0x2A2894,
64
-
.int_level_2_1 = 0x2A2898,
65
-
.int_level_2_0 = 0x2A289C,
66
-
.int_level_1_3 = 0x2A28A0,
67
-
.int_level_1_2 = 0x2A28A4,
68
-
.int_level_1_1 = 0x2A28A8,
69
-
.int_level_1_0 = 0x2A28AC,
70
-
.int_level_0_3 = 0x2A28B0,
71
-
.int_level_0_2 = 0x2A28B4,
72
-
.int_level_0_1 = 0x2A28B8,
73
-
.int_level_0_0 = 0x2A28BC,
74
-
.int_docsis_en = 0x2A28F4,
51
+
.int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
52
+
.int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
53
+
.int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
54
+
.int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
55
+
.int_config = {.phys = CRONUS_ADDR(0x2A2810)},
56
+
.int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
57
+
.ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
58
+
.ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
59
+
.ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
60
+
.ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
61
+
.int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
62
+
.int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
63
+
.int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
64
+
.int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
65
+
.int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
66
+
.int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
67
+
.int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
68
+
.int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
69
+
.int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
70
+
.int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
71
+
.int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
72
+
.int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
73
+
.int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
74
+
.int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
75
+
.int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
76
+
.int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
77
+
.int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
75
78
76
-
.mips_pll_setup = 0x1C0000,
77
-
.usb_fs = 0x1C0018,
78
-
.test_bus = 0x1C00CC,
79
-
.crt_spare = 0x1c00d4,
80
-
.usb2_ohci_int_mask = 0x20000C,
81
-
.usb2_strap = 0x200014,
82
-
.ehci_hcapbase = 0x21FE00,
83
-
.ohci_hc_revision = 0x1E0000,
84
-
.bcm1_bs_lmi_steer = 0x2E0008,
85
-
.usb2_control = 0x2E004C,
86
-
.usb2_stbus_obc = 0x21FF00,
87
-
.usb2_stbus_mess_size = 0x21FF04,
88
-
.usb2_stbus_chunk_size = 0x21FF08,
79
+
.mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80
+
.usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
81
+
.test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82
+
.crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83
+
.usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84
+
.usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85
+
.ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86
+
.ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
87
+
.bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88
+
.usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89
+
.usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
90
+
.usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
91
+
.usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
89
92
90
-
.pcie_regs = 0x220000,
91
-
.tim_ch = 0x2A2C10,
92
-
.tim_cl = 0x2A2C14,
93
-
.gpio_dout = 0x2A2C20,
94
-
.gpio_din = 0x2A2C24,
95
-
.gpio_dir = 0x2A2C2C,
96
-
.watchdog = 0x2A2C30,
97
-
.front_panel = 0x2A3800,
93
+
.pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
94
+
.tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
95
+
.tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
96
+
.gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
97
+
.gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
98
+
.gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
99
+
.watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
100
+
.front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
98
101
};
+67
-64
arch/mips/powertv/asic/asic-zeus.c
+67
-64
arch/mips/powertv/asic/asic-zeus.c
···
23
23
* Description: Defines the platform resources for the SA settop.
24
24
*/
25
25
26
+
#include <linux/init.h>
26
27
#include <asm/mach-powertv/asic.h>
27
28
28
-
const struct register_map zeus_register_map = {
29
-
.eic_slow0_strt_add = 0x000000,
30
-
.eic_cfg_bits = 0x000038,
31
-
.eic_ready_status = 0x00004c,
29
+
#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
32
30
33
-
.chipver3 = 0x280800,
34
-
.chipver2 = 0x280804,
35
-
.chipver1 = 0x280808,
36
-
.chipver0 = 0x28080c,
31
+
const struct register_map zeus_register_map __initdata = {
32
+
.eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
33
+
.eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
34
+
.eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
35
+
36
+
.chipver3 = {.phys = ZEUS_ADDR(0x280800)},
37
+
.chipver2 = {.phys = ZEUS_ADDR(0x280804)},
38
+
.chipver1 = {.phys = ZEUS_ADDR(0x280808)},
39
+
.chipver0 = {.phys = ZEUS_ADDR(0x28080c)},
37
40
38
41
/* The registers of IRBlaster */
39
-
.uart1_intstat = 0x281800,
40
-
.uart1_inten = 0x281804,
41
-
.uart1_config1 = 0x281808,
42
-
.uart1_config2 = 0x28180C,
43
-
.uart1_divisorhi = 0x281810,
44
-
.uart1_divisorlo = 0x281814,
45
-
.uart1_data = 0x281818,
46
-
.uart1_status = 0x28181C,
42
+
.uart1_intstat = {.phys = ZEUS_ADDR(0x281800)},
43
+
.uart1_inten = {.phys = ZEUS_ADDR(0x281804)},
44
+
.uart1_config1 = {.phys = ZEUS_ADDR(0x281808)},
45
+
.uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)},
46
+
.uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)},
47
+
.uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)},
48
+
.uart1_data = {.phys = ZEUS_ADDR(0x281818)},
49
+
.uart1_status = {.phys = ZEUS_ADDR(0x28181C)},
47
50
48
-
.int_stat_3 = 0x282800,
49
-
.int_stat_2 = 0x282804,
50
-
.int_stat_1 = 0x282808,
51
-
.int_stat_0 = 0x28280c,
52
-
.int_config = 0x282810,
53
-
.int_int_scan = 0x282818,
54
-
.ien_int_3 = 0x282830,
55
-
.ien_int_2 = 0x282834,
56
-
.ien_int_1 = 0x282838,
57
-
.ien_int_0 = 0x28283c,
58
-
.int_level_3_3 = 0x282880,
59
-
.int_level_3_2 = 0x282884,
60
-
.int_level_3_1 = 0x282888,
61
-
.int_level_3_0 = 0x28288c,
62
-
.int_level_2_3 = 0x282890,
63
-
.int_level_2_2 = 0x282894,
64
-
.int_level_2_1 = 0x282898,
65
-
.int_level_2_0 = 0x28289c,
66
-
.int_level_1_3 = 0x2828a0,
67
-
.int_level_1_2 = 0x2828a4,
68
-
.int_level_1_1 = 0x2828a8,
69
-
.int_level_1_0 = 0x2828ac,
70
-
.int_level_0_3 = 0x2828b0,
71
-
.int_level_0_2 = 0x2828b4,
72
-
.int_level_0_1 = 0x2828b8,
73
-
.int_level_0_0 = 0x2828bc,
74
-
.int_docsis_en = 0x2828F4,
51
+
.int_stat_3 = {.phys = ZEUS_ADDR(0x282800)},
52
+
.int_stat_2 = {.phys = ZEUS_ADDR(0x282804)},
53
+
.int_stat_1 = {.phys = ZEUS_ADDR(0x282808)},
54
+
.int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)},
55
+
.int_config = {.phys = ZEUS_ADDR(0x282810)},
56
+
.int_int_scan = {.phys = ZEUS_ADDR(0x282818)},
57
+
.ien_int_3 = {.phys = ZEUS_ADDR(0x282830)},
58
+
.ien_int_2 = {.phys = ZEUS_ADDR(0x282834)},
59
+
.ien_int_1 = {.phys = ZEUS_ADDR(0x282838)},
60
+
.ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)},
61
+
.int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)},
62
+
.int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)},
63
+
.int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)},
64
+
.int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)},
65
+
.int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)},
66
+
.int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)},
67
+
.int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)},
68
+
.int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)},
69
+
.int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)},
70
+
.int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)},
71
+
.int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)},
72
+
.int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)},
73
+
.int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)},
74
+
.int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)},
75
+
.int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)},
76
+
.int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)},
77
+
.int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
75
78
76
-
.mips_pll_setup = 0x1a0000,
77
-
.usb_fs = 0x1a0018,
78
-
.test_bus = 0x1a0238,
79
-
.crt_spare = 0x1a0090,
80
-
.usb2_ohci_int_mask = 0x1e000c,
81
-
.usb2_strap = 0x1e0014,
82
-
.ehci_hcapbase = 0x1FFE00,
83
-
.ohci_hc_revision = 0x1FFC00,
84
-
.bcm1_bs_lmi_steer = 0x2C0008,
85
-
.usb2_control = 0x2c01a0,
86
-
.usb2_stbus_obc = 0x1FFF00,
87
-
.usb2_stbus_mess_size = 0x1FFF04,
88
-
.usb2_stbus_chunk_size = 0x1FFF08,
79
+
.mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80
+
.usb_fs = {.phys = ZEUS_ADDR(0x1a0018)},
81
+
.test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82
+
.crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83
+
.usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
84
+
.usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)},
85
+
.ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)},
86
+
.ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)},
87
+
.bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)},
88
+
.usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)},
89
+
.usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)},
90
+
.usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)},
91
+
.usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)},
89
92
90
-
.pcie_regs = 0x200000,
91
-
.tim_ch = 0x282C10,
92
-
.tim_cl = 0x282C14,
93
-
.gpio_dout = 0x282c20,
94
-
.gpio_din = 0x282c24,
95
-
.gpio_dir = 0x282c2C,
96
-
.watchdog = 0x282c30,
97
-
.front_panel = 0x283800,
93
+
.pcie_regs = {.phys = ZEUS_ADDR(0x200000)},
94
+
.tim_ch = {.phys = ZEUS_ADDR(0x282C10)},
95
+
.tim_cl = {.phys = ZEUS_ADDR(0x282C14)},
96
+
.gpio_dout = {.phys = ZEUS_ADDR(0x282c20)},
97
+
.gpio_din = {.phys = ZEUS_ADDR(0x282c24)},
98
+
.gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)},
99
+
.watchdog = {.phys = ZEUS_ADDR(0x282c30)},
100
+
.front_panel = {.phys = ZEUS_ADDR(0x283800)},
98
101
};
+19
-27
arch/mips/powertv/asic/asic_devices.c
+19
-27
arch/mips/powertv/asic/asic_devices.c
···
67
67
68
68
unsigned int platform_features;
69
69
unsigned int platform_family;
70
-
const struct register_map *register_map;
71
-
EXPORT_SYMBOL(register_map); /* Exported for testing */
70
+
struct register_map _asic_register_map;
71
+
EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */
72
72
unsigned long asic_phy_base;
73
73
unsigned long asic_base;
74
74
EXPORT_SYMBOL(asic_base); /* Exported for testing */
···
418
418
{
419
419
}
420
420
421
+
static void __init set_register_map(unsigned long phys_base,
422
+
const struct register_map *map)
423
+
{
424
+
asic_phy_base = phys_base;
425
+
_asic_register_map = *map;
426
+
register_map_virtualize(&_asic_register_map);
427
+
asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
428
+
}
429
+
421
430
/**
422
431
* configure_platform - configuration based on platform type.
423
432
*/
···
440
431
case FAMILY_1500VZF:
441
432
platform_features = FFS_CAPABLE;
442
433
asic = ASIC_CALLIOPE;
443
-
asic_phy_base = CALLIOPE_IO_BASE;
444
-
register_map = &calliope_register_map;
445
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
446
-
ASIC_IO_SIZE);
434
+
set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
447
435
448
436
if (platform_family == FAMILY_1500VZE) {
449
437
gp_resources = non_dvr_vze_calliope_resources;
···
461
455
platform_features = FFS_CAPABLE | PCIE_CAPABLE |
462
456
DISPLAY_CAPABLE;
463
457
asic = ASIC_ZEUS;
464
-
asic_phy_base = ZEUS_IO_BASE;
465
-
register_map = &zeus_register_map;
466
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
467
-
ASIC_IO_SIZE);
458
+
set_register_map(ZEUS_IO_BASE, &zeus_register_map);
468
459
gp_resources = non_dvr_zeus_resources;
469
460
470
461
pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
···
474
471
/* The settop has PCIE but it isn't used, so don't advertise
475
472
* it*/
476
473
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
477
-
asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */
478
-
register_map = &cronus_register_map; /* same as Cronus */
479
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
480
-
ASIC_IO_SIZE);
481
-
gp_resources = non_dvr_cronuslite_resources;
482
474
483
475
/* ASIC version will determine if this is a real CronusLite or
484
476
* Castrati(Cronus) */
···
487
489
else
488
490
asic = ASIC_CRONUSLITE;
489
491
492
+
/* Cronus and Cronus Lite have the same register map */
493
+
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
494
+
gp_resources = non_dvr_cronuslite_resources;
490
495
pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
491
496
"chipversion=0x%08X\n",
492
497
(asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
···
499
498
case FAMILY_4600VZA:
500
499
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
501
500
asic = ASIC_CRONUS;
502
-
asic_phy_base = CRONUS_IO_BASE;
503
-
register_map = &cronus_register_map;
504
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
505
-
ASIC_IO_SIZE);
501
+
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
506
502
gp_resources = non_dvr_cronus_resources;
507
503
508
504
pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
···
510
512
platform_features = DVR_CAPABLE | PCIE_CAPABLE |
511
513
DISPLAY_CAPABLE;
512
514
asic = ASIC_ZEUS;
513
-
asic_phy_base = ZEUS_IO_BASE;
514
-
register_map = &zeus_register_map;
515
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
516
-
ASIC_IO_SIZE);
515
+
set_register_map(ZEUS_IO_BASE, &zeus_register_map);
517
516
gp_resources = dvr_zeus_resources;
518
517
519
518
pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
···
521
526
platform_features = DVR_CAPABLE | PCIE_CAPABLE |
522
527
DISPLAY_CAPABLE;
523
528
asic = ASIC_CRONUS;
524
-
asic_phy_base = CRONUS_IO_BASE;
525
-
register_map = &cronus_register_map;
526
-
asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
527
-
ASIC_IO_SIZE);
529
+
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
528
530
gp_resources = dvr_cronus_resources;
529
531
530
532
pr_info("Platform: 8600/Vz Class B - CRONUS, "