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[ARM] Clean up save_and_disable_irqs macro and allow use of ARMv6 CPSID

save_and_disable_irqs does not need to use mov + msr (which was
introduced to work around a documentation bug which was propagated
into binutils.) Use msr with an immediate constant, and if we're
building for ARMv6 or later, use the new CPSID instruction.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by

Russell King and committed by
Russell King 59d1ff3b be6eb9b7

+8 -5
+2 -2
arch/arm/lib/bitops.h
··· 34 34 and r2, r0, #7 35 35 mov r3, #1 36 36 mov r3, r3, lsl r2 37 - save_and_disable_irqs ip, r2 37 + save_and_disable_irqs ip 38 38 ldrb r2, [r1, r0, lsr #3] 39 39 \instr r2, r2, r3 40 40 strb r2, [r1, r0, lsr #3] ··· 54 54 add r1, r1, r0, lsr #3 55 55 and r3, r0, #7 56 56 mov r0, #1 57 - save_and_disable_irqs ip, r2 57 + save_and_disable_irqs ip 58 58 ldrb r2, [r1] 59 59 tst r2, r0, lsl r3 60 60 \instr r2, r2, r0, lsl r3
+6 -3
include/asm-arm/assembler.h
··· 83 83 * Save the current IRQ state and disable IRQs. Note that this macro 84 84 * assumes FIQs are enabled, and that the processor is in SVC mode. 85 85 */ 86 - .macro save_and_disable_irqs, oldcpsr, temp 86 + .macro save_and_disable_irqs, oldcpsr 87 87 mrs \oldcpsr, cpsr 88 - mov \temp, #PSR_I_BIT | MODE_SVC 89 - msr cpsr_c, \temp 88 + #if __LINUX_ARM_ARCH__ >= 6 89 + cpsid i 90 + #else 91 + msr cpsr_c, #PSR_I_BIT | MODE_SVC 92 + #endif 90 93 .endm 91 94 92 95 /*